<commit_before>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from typing import List, Tuple

from hwt.code import log2ceil, connect, Concat, SwitchLogic, Or
from hwt.hdl.assignment import Assignment
from hwt.hdl.transTmpl import TransTmpl
from hwt.interfaces.std import Handshaked
from hwt.synthesizer.hObjList import HObjList
from hwt.synthesizer.param import Param
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal
from hwt.synthesizer.unit import Unit
from hwtLib.abstract.busEndpoint import BusEndpoint
from hwtLib.amba.axis_comp.builder import AxiSBuilder
from hwtLib.amba.interconnect.common import AxiInterconnectCommon,\
    apply_name
from hwtLib.handshaked.joinFair import HsJoinFairShare
from hwtLib.handshaked.streamNode import StreamNode
from hwtLib.logic.oneHotToBin import oneHotToBin
from hwtLib.types.ctypes import uint8_t


class AxiInterconnectMatrixAddrCrossbar(Unit):
    """
    Component which implements N to M crossbar for AXI address channel.
    If there are multiple masters connected to any slave the access is mannaged by round-robin.

    :ivar order_s_index_for_m_data_out: handshaked interface with index of slave for each master,
        data is send on start of the transaction
    :ivar order_m_index_for_s_data_out: handshaked interface with index of master for each slave,
        data is send on start of the transaction

    .. hwt-schematic:: example_AxiInterconnectMatrixAddrCrossbar
    """

    @staticmethod
    def priorityAck(priorityReg, vldSignals, index):
        return HsJoinFairShare.priorityAck(priorityReg, vldSignals, index)

    def __init__(self, axi_addr_cls):
        self.intfCls = axi_addr_cls
        super(AxiInterconnectMatrixAddrCrossbar, self).__init__()

    def _config(self):
        self.SLAVES = Param([])
        self.MASTERS = Param([])
        self.intfCls._config(self)

    def _declr(self):
        AxiInterconnectCommon._declr(self, has_r=False, has_w=False)
        AxiInterconnectCommon._init_config_flags(self)

        if self.REQUIRED_ORDER_SYNC_M_FOR_S:
            # fifo for master index for each slave so slave knows
            # which master did read and where is should send it
            self.order_m_index_for_s_data_out = HObjList([
                Handshaked()._m() for _ in self.SLAVES])

            for f in self.order_m_index_for_s_data_out:
                f.DATA_WIDTH = self.MASTER_INDEX_WIDTH = log2ceil(
                    len(self.MASTERS))

        if self.REQUIRED_ORDER_SYNC_S_FOR_M:
            # fifo for slave index for each master
            # so master knows where it should expect the data
            self.order_s_index_for_m_data_out = HObjList([
                Handshaked()._m() for _ in self.MASTERS])

            for f in self.order_s_index_for_m_data_out:
                f.DATA_WIDTH = log2ceil(len(self.SLAVES))

    def propagate_addr(self, master_addr_channels, slave_addr_channels)\
            ->List[List[Tuple[RtlSignal, Assignment]]]:
        """
        :return: matrix of addr select, addr assignment for all masters and slaves
                (master X slave)
        """
        slv_en = []
        for mi, slvs in enumerate(self.MASTERS):
            _slv_en = []
            slv_en.append(_slv_en)
            srcAddrSig = master_addr_channels[mi].addr
            for si, (addr, size) in enumerate(self.SLAVES):
                dstAddrSig = slave_addr_channels[si].addr
                if si not in slvs:
                    # case where slave is not mapped to master address space
                    en = 0
                    addr_drive = dstAddrSig(None)
                else:
                    tmpl = TransTmpl(uint8_t[size], bitAddr=addr * 8)
                    # generate optimized address comparator and handle potentialy
                    # different bus address granularity
                    en, addr_drive = BusEndpoint.propagateAddr(
                        self, srcAddrSig, 8, dstAddrSig, 8, tmpl)
                _slv_en.append((en, addr_drive))

        return slv_en
<commit_msg>AxiInterconnectMatrixAddrCrossbar: fix mode with two distinct masters<commit_after>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from typing import List, Tuple

from hwt.code import log2ceil, connect, Concat, SwitchLogic, Or
from hwt.hdl.assignment import Assignment
from hwt.hdl.transTmpl import TransTmpl
from hwt.interfaces.std import Handshaked
from hwt.synthesizer.hObjList import HObjList
from hwt.synthesizer.param import Param
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal
from hwt.synthesizer.unit import Unit
from hwtLib.abstract.busEndpoint import BusEndpoint
from hwtLib.amba.axis_comp.builder import AxiSBuilder
from hwtLib.amba.interconnect.common import AxiInterconnectCommon,\
    apply_name
from hwtLib.handshaked.joinFair import HsJoinFairShare
from hwtLib.handshaked.streamNode import StreamNode
from hwtLib.logic.oneHotToBin import oneHotToBin
from hwtLib.types.ctypes import uint8_t
from hwt.hdl.types.defs import BIT


class AxiInterconnectMatrixAddrCrossbar(Unit):
    """
    Component which implements N to M crossbar for AXI address channel.
    If there are multiple masters connected to any slave the access is mannaged by round-robin.

    :ivar order_s_index_for_m_data_out: handshaked interface with index of slave for each master,
        data is send on start of the transaction
    :ivar order_m_index_for_s_data_out: handshaked interface with index of master for each slave,
        data is send on start of the transaction

    .. hwt-schematic:: example_AxiInterconnectMatrixAddrCrossbar
    """

    @staticmethod
    def priorityAck(priorityReg, vldSignals, index):
        return HsJoinFairShare.priorityAck(priorityReg, vldSignals, index)

    def __init__(self, axi_addr_cls):
        self.intfCls = axi_addr_cls
        super(AxiInterconnectMatrixAddrCrossbar, self).__init__()

    def _config(self):
        self.SLAVES = Param([])
        self.MASTERS = Param([])
        self.intfCls._config(self)

    def _declr(self):
        AxiInterconnectCommon._declr(self, has_r=False, has_w=False)
        AxiInterconnectCommon._init_config_flags(self)

        if self.REQUIRED_ORDER_SYNC_M_FOR_S:
            # fifo for master index for each slave so slave knows
            # which master did read and where is should send it
            self.order_m_index_for_s_data_out = HObjList([
                Handshaked()._m() for _ in self.SLAVES])

            for f in self.order_m_index_for_s_data_out:
                f.DATA_WIDTH = self.MASTER_INDEX_WIDTH = log2ceil(
                    len(self.MASTERS))

        if self.REQUIRED_ORDER_SYNC_S_FOR_M:
            # fifo for slave index for each master
            # so master knows where it should expect the data
            self.order_s_index_for_m_data_out = HObjList([
                Handshaked()._m() for _ in self.MASTERS])

            for f in self.order_s_index_for_m_data_out:
                f.DATA_WIDTH = log2ceil(len(self.SLAVES))

    def propagate_addr(self, master_addr_channels, slave_addr_channels)\
            ->List[List[Tuple[RtlSignal, Assignment]]]:
        """
        :return: matrix of addr select, addr assignment for all masters and slaves
                (master X slave)
        """
        slv_en = []
        for mi, slvs in enumerate(self.MASTERS):
            _slv_en = []
            slv_en.append(_slv_en)
            srcAddrSig = master_addr_channels[mi].addr
            for si, (addr, size) in enumerate(self.SLAVES):
                dstAddrSig = slave_addr_channels[si].addr
                if si not in slvs:
                    # case where slave is not mapped to master address space
                    en = BIT.from_py(0)
                    addr_drive = dstAddrSig(None)
                else:
                    tmpl = TransTmpl(uint8_t[size], bitAddr=addr * 8)
                    # generate optimized address comparator and handle potentialy
                    # different bus address granularity
                    en, addr_drive = BusEndpoint.propagateAddr(
                        self, srcAddrSig, 8, dstAddrSig, 8, tmpl)
                _slv_en.append((en, addr_drive))

        return slv_en

{'fraction_non_alphanumeric': 0.06784409257003654, 'fraction_numerical': 0.002679658952496955, 'mean_word_length': 2.577777777777778, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 5, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1207154', 'n_tokens_mistral': 2527, 'n_tokens_neox': 2429, 'n_words': 658}