<commit_before>module rx_0 {

  # Create axis_constant
  cell pavel-demin:user:axis_constant:1.0 phase_0 {
    AXIS_TDATA_WIDTH 32
  } {
    cfg_data /cfg_slice_0/Dout
    aclk /ps_0/FCLK_CLK0
  }

  # Create dds_compiler
  cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
    DDS_CLOCK_RATE 125
    SPURIOUS_FREE_DYNAMIC_RANGE 138
    FREQUENCY_RESOLUTION 0.2
    PHASE_INCREMENT Streaming
    DSP48_USE Maximal
    HAS_TREADY true
    HAS_PHASE_OUT false
    PHASE_WIDTH 30
    OUTPUT_WIDTH 24
  } {
    S_AXIS_PHASE phase_0/M_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create axis_lfsr
  cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
    aclk /ps_0/FCLK_CLK0
    aresetn /rst_slice_1/Dout
  }

  # Create cmpy
  cell xilinx.com:ip:cmpy:6.0 mult_0 {
    FLOWCONTROL Blocking
    APORTWIDTH.VALUE_SRC USER
    BPORTWIDTH.VALUE_SRC USER
    APORTWIDTH 14
    BPORTWIDTH 24
    ROUNDMODE Random_Rounding
    OUTPUTWIDTH 24
  } {
    S_AXIS_A /bcast_0/M00_AXIS
    S_AXIS_B dds_0/M_AXIS_DATA
    S_AXIS_CTRL lfsr_0/M_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create axis_broadcaster
  cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
    S_TDATA_NUM_BYTES.VALUE_SRC USER
    M_TDATA_NUM_BYTES.VALUE_SRC USER
    S_TDATA_NUM_BYTES 6
    M_TDATA_NUM_BYTES 3
    M00_TDATA_REMAP {tdata[47:24]}
    M01_TDATA_REMAP {tdata[23:0]}
  } {
    S_AXIS mult_0/M_AXIS_DOUT
    aclk /ps_0/FCLK_CLK0
    aresetn /rst_0/peripheral_aresetn
  }

  # Create cic_compiler
  cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
    INPUT_DATA_WIDTH.VALUE_SRC USER
    FILTER_TYPE Decimation
    NUMBER_OF_STAGES 6
    FIXED_OR_INITIAL_RATE 3125
    INPUT_SAMPLE_FREQUENCY 125
    CLOCK_FREQUENCY 125
    INPUT_DATA_WIDTH 24
    QUANTIZATION Truncation
    OUTPUT_DATA_WIDTH 24
    USE_XTREME_DSP_SLICE false
  } {
    S_AXIS_DATA bcast_0/M00_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create cic_compiler<commit_msg>boost multiplier output in sdr_transceiver_dds/rx_0<commit_after>module rx_0 {

  # Create axis_constant
  cell pavel-demin:user:axis_constant:1.0 phase_0 {
    AXIS_TDATA_WIDTH 32
  } {
    cfg_data /cfg_slice_0/Dout
    aclk /ps_0/FCLK_CLK0
  }

  # Create dds_compiler
  cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
    DDS_CLOCK_RATE 125
    SPURIOUS_FREE_DYNAMIC_RANGE 138
    FREQUENCY_RESOLUTION 0.2
    PHASE_INCREMENT Streaming
    DSP48_USE Maximal
    HAS_TREADY true
    HAS_PHASE_OUT false
    PHASE_WIDTH 30
    OUTPUT_WIDTH 24
  } {
    S_AXIS_PHASE phase_0/M_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create axis_lfsr
  cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
    aclk /ps_0/FCLK_CLK0
    aresetn /rst_slice_1/Dout
  }

  # Create cmpy
  cell xilinx.com:ip:cmpy:6.0 mult_0 {
    FLOWCONTROL Blocking
    APORTWIDTH.VALUE_SRC USER
    BPORTWIDTH.VALUE_SRC USER
    APORTWIDTH 14
    BPORTWIDTH 24
    ROUNDMODE Random_Rounding
    OUTPUTWIDTH 25
  } {
    S_AXIS_A /bcast_0/M00_AXIS
    S_AXIS_B dds_0/M_AXIS_DATA
    S_AXIS_CTRL lfsr_0/M_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create axis_broadcaster
  cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
    S_TDATA_NUM_BYTES.VALUE_SRC USER
    M_TDATA_NUM_BYTES.VALUE_SRC USER
    S_TDATA_NUM_BYTES 8
    M_TDATA_NUM_BYTES 3
    M00_TDATA_REMAP {tdata[55:32]}
    M01_TDATA_REMAP {tdata[23:0]}
  } {
    S_AXIS mult_0/M_AXIS_DOUT
    aclk /ps_0/FCLK_CLK0
    aresetn /rst_0/peripheral_aresetn
  }

  # Create cic_compiler
  cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
    INPUT_DATA_WIDTH.VALUE_SRC USER
    FILTER_TYPE Decimation
    NUMBER_OF_STAGES 6
    FIXED_OR_INITIAL_RATE 3125
    INPUT_SAMPLE_FREQUENCY 125
    CLOCK_FREQUENCY 125
    INPUT_DATA_WIDTH 24
    QUANTIZATION Truncation
    OUTPUT_DATA_WIDTH 24
    USE_XTREME_DSP_SLICE false
  } {
    S_AXIS_DATA bcast_0/M00_AXIS
    aclk /ps_0/FCLK_CLK0
  }

  # Create cic_compiler
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