<commit_before>
from __future__ import absolute_import, division

from math import fmod
from fractions import gcd

import myhdl
from myhdl import always_comb

from rhea.system import Reset
from ..device_clock_mgmt_prim import device_clock_mgmt_prim


@myhdl.block
def device_clock_mgmt(clkmgmt):
    
    # assign the individual clocks in th epll_intf to the 
    # clock bit-vector (interface mappings)
    number_of_outputs = len(clkmgmt.output_frequencies)

    # generate the correct polarity reset regardless of the reset
    # type attached to the interface.  If the interface does not 
    # have a reset create a state "no reset")\.  Reset syncros 
    # are handled external to this module
    reseti = Reset(0, active=1, async=True)
    reset = Reset(0, active=1, async=True)
    stuck_reset = False
    if clkmgmt.reset is None:
        stuck_reset = True
    else:
        reset = clkmgmt.reset
    clkmgmt.reset = reseti
    active = reseti.active

    @always_comb
    def beh_assign():
        for ii in range(number_of_outputs):
            clkmgmt.clocks[ii].next = clkmgmt.clocksout[ii]

        if stuck_reset:
            reseti.next = False
        elif active == 0:
            reseti.next = not reset
        else:
            reseti.next = reset

    # attach the intended Verilog code to the block, the
    # Verilog code will be inserted instead of device_clock_mgmt_prim
    # converted.        
    device_clock_mgmt_prim.verilog_code = clock_mgmt_verilog_code(clkmgmt)
    prim_inst = device_clock_mgmt_prim(clkmgmt)

    return prim_inst


def mmcm_parameters(cifreq=100e6, cofreqs=[100e6, 125e6, 180e6]):
    """
    """
    search, M = True, 1
    best = [M, 10]
    
    def isint(x):
        return fmod(x, 1) == 0

    while search and M < 64:
        M = M + 1
        fb = M*cifreq
        # @todo: need to add "D", if geater use a
        # @todo: reasonable "D" value
        vco_freq_mhz = fb/1e6
        if vco_freq_mhz < 600 or vco_freq_mhz > 1250:
            continue
            
        d = [fb/cf for cf in cofreqs]
        if False in list(map(isint, d)):
            search = True
            w = sum([fmod(dd, 1) for dd in d])
            if w < best[1]:
                best = [M, w]
        else:
            search = False

    print(M)
    odiv = [int(round(fb/cf)) for cf in cofreqs]
    print(odiv)
    return M, odiv


def clock_mgmt_verilog_code(clkmgmt):<commit_msg>Removing debug prints from xilinx clock management pll calculations. (#48)<commit_after>
from __future__ import absolute_import, division

from math import fmod
from fractions import gcd

import myhdl
from myhdl import always_comb

from rhea.system import Reset
from ..device_clock_mgmt_prim import device_clock_mgmt_prim


@myhdl.block
def device_clock_mgmt(clkmgmt):
    
    # assign the individual clocks in th epll_intf to the 
    # clock bit-vector (interface mappings)
    number_of_outputs = len(clkmgmt.output_frequencies)

    # generate the correct polarity reset regardless of the reset
    # type attached to the interface.  If the interface does not 
    # have a reset create a state "no reset")\.  Reset syncros 
    # are handled external to this module
    reseti = Reset(0, active=1, async=True)
    reset = Reset(0, active=1, async=True)
    stuck_reset = False
    if clkmgmt.reset is None:
        stuck_reset = True
    else:
        reset = clkmgmt.reset
    clkmgmt.reset = reseti
    active = reseti.active

    @always_comb
    def beh_assign():
        for ii in range(number_of_outputs):
            clkmgmt.clocks[ii].next = clkmgmt.clocksout[ii]

        if stuck_reset:
            reseti.next = False
        elif active == 0:
            reseti.next = not reset
        else:
            reseti.next = reset

    # attach the intended Verilog code to the block, the
    # Verilog code will be inserted instead of device_clock_mgmt_prim
    # converted.        
    device_clock_mgmt_prim.verilog_code = clock_mgmt_verilog_code(clkmgmt)
    prim_inst = device_clock_mgmt_prim(clkmgmt)

    return prim_inst


def mmcm_parameters(cifreq=100e6, cofreqs=[100e6, 125e6, 180e6]):
    """
    """
    search, M = True, 1
    best = [M, 10]
    
    def isint(x):
        return fmod(x, 1) == 0

    while search and M < 64:
        M = M + 1
        fb = M*cifreq
        # @todo: need to add "D", if geater use a
        # @todo: reasonable "D" value
        vco_freq_mhz = fb/1e6
        if vco_freq_mhz < 600 or vco_freq_mhz > 1250:
            continue
            
        d = [fb/cf for cf in cofreqs]
        if False in list(map(isint, d)):
            search = True
            w = sum([fmod(dd, 1) for dd in d])
            if w < best[1]:
                best = [M, w]
        else:
            search = False

    odiv = [int(round(fb/cf)) for cf in cofreqs]
    return M, odiv


def clock_mgmt_verilog_code(clkmgmt):
{'fraction_non_alphanumeric': 0.07865628840639083, 'fraction_numerical': 0.016796394920114706, 'mean_word_length': 2.288215488215488, 'pattern_counts': {'":': 0, '<': 9, '<?xml version=': 0, '>': 5, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4769239', 'n_tokens_mistral': 1722, 'n_tokens_neox': 1590, 'n_words': 490}