<commit_before>// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`

`include "prim_assert.sv"

module rstmgr_reg_top (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,
  // To HW
  output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write
  input  rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read

  // Integrity check errors
  output logic intg_err_o,

  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);

  import rstmgr_reg_pkg::* ;

  localparam int AW = 7;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [27:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(28)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  assign tl_reg_h2d = tl_i;
  assign tl_o_pre   = tl_reg_d2h;

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    .error_i (reg_error)
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic alert_test_we;
  logic alert_test_fatal_fault_wd;
  logic alert_test_fatal_cnsty_fault_wd;
  logic reset_req_we;
  logic [3:0] reset_req_qs;
  logic [3:0] reset_req_wd;
  logic reset_info_we;
  logic reset_info_por_qs;
  logic reset_info_por_wd;
  logic reset_info_low_power_exit_qs;
  logic reset_info_low_power_exit_wd;
  logic reset_info_ndm_reset_qs;
  logic reset_info_ndm_reset_wd;
  logic reset_info_sw_reset_qs;
  logic reset_info_sw_reset_wd;
  logic [3:0] reset_info_hw_req_qs;
  logic [3:0] reset_info_hw_req_wd;
  logic alert_regwen_we;
  logic alert_regwen_qs;
  logic alert_regwen_wd;
  logic alert_info_ctrl_we;
  logic alert_info_ctrl_en_qs;
  logic alert_info_ctrl_en_wd;
  logic [3:0] alert_info_ctrl_index_qs;
  logic [3:0] alert_info_ctrl_index_wd;
  logic alert_info_attr_re;
  logic [3:0] alert_info_attr_qs;
  logic alert_info_re;
  logic [31:0] alert_info_qs;
  logic cpu_regwen_we;
  logic cpu_regwen_qs;
  logic cpu_regwen_wd;
  logic cpu_info_ctrl_we;
  logic cpu_info_ctrl_en_qs;
  logic cpu_info_ctrl_en_wd;
  logic [3:0] cpu_info_ctrl_index_qs;
  logic [3:0] cpu_info_ctrl_index_wd;
  logic cpu_info_attr_re;
  logic [3:0] cpu_info_attr_qs;
  logic cpu_info_re;
  logic [31:0] cpu_info_qs;
  logic sw_rst_regwen_0_we;
  logic sw_rst_regwen_0_qs;
  logic sw_rst_regwen_0_wd;
  logic sw_rst_regwen_1_we;
  logic sw_rst_regwen_1_qs;
  logic sw_rst_regwen_1_wd;
  logic sw_rst_regwen_2_we;
  logic sw_rst_regwen_2_qs;
  logic sw_rst_regwen_2_wd;
  logic sw_rst_regwen_3_we;
  logic sw_rst_regwen_3_qs;
  logic sw_rst_regwen_3_wd;
  logic sw_rst_regwen_4_we;
  logic sw_rst_regwen_4_qs;
  logic sw_rst_regwen_4_wd;
  logic sw_rst_regwen_5_we;
  logic sw_rst_regwen_5_qs;
  logic sw_rst_regwen_5_wd;
  logic sw_rst_regwen_6_we;
  logic sw_rst_regwen_6_qs;
  logic sw_rst_regwen_6_wd;
  logic sw_rst_regwen_7_we;
  logic sw_rst_regwen_7_qs;
  logic sw_rst_regwen_7_wd;
  logic sw_rst_ctrl_n_0_we;
  logic sw_rst_ctrl_n_0_qs;
  logic sw_rst_ctrl_n_0_wd;
  logic sw_rst_ctrl_n_1_we;
  logic sw_rst_ctrl_n_1_qs;
  logic sw_rst_ctrl_n_1_wd;
  logic sw_rst_ctrl_n_2_we;
  logic sw_rst_ctrl_n_2_qs;
  logic sw_rst_ctrl_n_2_wd;
  logic sw_rst_ctrl_n_3_we;
  logic sw_rst_ctrl_n_3_qs;
  logic sw_rst_ctrl_n_3_wd;
  logic sw_rst_ctrl_n_4_we;
  logic sw_rst_ctrl_n_4_qs;
  logic sw_rst_ctrl_n_4_wd;
  logic sw_rst_ctrl_n_5_we;
  logic sw_rst_ctrl_n_5_qs;
  logic sw_rst_ctrl_n_5_wd;
  logic sw_rst_ctrl_n_6_we;
  logic sw_rst_ctrl_n_6_qs;
  logic sw_rst_ctrl_n_6_wd;
  logic sw_rst_ctrl_n_7_we;
  logic sw_rst_ctrl_n_7_qs;
  logic sw_rst_ctrl_n_7_wd;
  logic err_code_we;
  logic err_code_reg_intg_err_qs;
  logic err_code_reg_intg_err_wd;
  logic err_code_reset_consistency_err_qs;
  logic err_code_reset_consistency_err_wd;

  // Register instances
  // R[alert_test]: V(True)
  logic alert_test_qe;
  logic [1:0] alert_test_flds_we;
  assign alert_test_qe = &alert_test_flds_we;
  //   F[fatal_fault]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_fault (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_fault_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[0]),
    .q      (reg2hw.alert_test.fatal_fault.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;

  //   F[fatal_cnsty_fault]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_cnsty_fault (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_cnsty_fault_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[1]),
    .q      (reg2hw.alert_test.fatal_cnsty_fault.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe;


  // R[reset_req]: V(False)
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h9)
  ) u_reset_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_req_we),
    .wd     (reset_req_wd),

    // from internal hardware
    .de     (hw2reg.reset_req.de),
    .d      (hw2reg.reset_req.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_req_qs)
  );


  // R[reset_info]: V(False)
  //   F[por]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h1)
  ) u_reset_info_por (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_por_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_por_qs)
  );

  //   F[low_power_exit]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_low_power_exit (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_low_power_exit_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.low_power_exit.de),
    .d      (hw2reg.reset_info.low_power_exit.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_low_power_exit_qs)
  );

  //   F[ndm_reset]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_ndm_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_ndm_reset_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.ndm_reset.de),
    .d      (hw2reg.reset_info.ndm_reset.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_ndm_reset_qs)
  );

  //   F[sw_reset]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_sw_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_sw_reset_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.sw_reset.de),
    .d      (hw2reg.reset_info.sw_reset.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_info.sw_reset.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_sw_reset_qs)
  );

  //   F[hw_req]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (4'h0)
  ) u_reset_info_hw_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_hw_req_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.hw_req.de),
    .d      (hw2reg.reset_info.hw_req.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_info.hw_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_hw_req_qs)
  );


  // R[alert_regwen]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_alert_regwen (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_regwen_we),
    .wd     (alert_regwen_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (alert_regwen_qs)
  );


  // R[alert_info_ctrl]: V(False)
  // Create REGWEN-gated WE signal
  logic alert_info_ctrl_gated_we;
  assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs;
  //   F[en]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_alert_info_ctrl_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_info_ctrl_gated_we),
    .wd     (alert_info_ctrl_en_wd),

    // from internal hardware
    .de     (hw2reg.alert_info_ctrl.en.de),
    .d      (hw2reg.alert_info_ctrl.en.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.alert_info_ctrl.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (alert_info_ctrl_en_qs)
  );

  //   F[index]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0)
  ) u_alert_info_ctrl_index (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_info_ctrl_gated_we),
    .wd     (alert_info_ctrl_index_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.alert_info_ctrl.index.q),
    .ds     (),

    // to register interface (read)
    .qs     (alert_info_ctrl_index_qs)
  );


  // R[alert_info_attr]: V(True)
  prim_subreg_ext #(
    .DW    (4)
  ) u_alert_info_attr (
    .re     (alert_info_attr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.alert_info_attr.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (alert_info_attr_qs)
  );


  // R[alert_info]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_alert_info (
    .re     (alert_info_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.alert_info.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (alert_info_qs)
  );


  // R[cpu_regwen]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_cpu_regwen (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_regwen_we),
    .wd     (cpu_regwen_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_regwen_qs)
  );


  // R[cpu_info_ctrl]: V(False)
  // Create REGWEN-gated WE signal
  logic cpu_info_ctrl_gated_we;
  assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs;
  //   F[en]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_cpu_info_ctrl_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_info_ctrl_gated_we),
    .wd     (cpu_info_ctrl_en_wd),

    // from internal hardware
    .de     (hw2reg.cpu_info_ctrl.en.de),
    .d      (hw2reg.cpu_info_ctrl.en.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cpu_info_ctrl.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_info_ctrl_en_qs)
  );

  //   F[index]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0)
  ) u_cpu_info_ctrl_index (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_info_ctrl_gated_we),
    .wd     (cpu_info_ctrl_index_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cpu_info_ctrl.index.q),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_info_ctrl_index_qs)
  );


  // R[cpu_info_attr]: V(True)
  prim_subreg_ext #(
    .DW    (4)
  ) u_cpu_info_attr (
    .re     (cpu_info_attr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.cpu_info_attr.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (cpu_info_attr_qs)
  );


  // R[cpu_info]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_cpu_info (
    .re     (cpu_info_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.cpu_info.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (cpu_info_qs)
  );


  // Subregister 0 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_0]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_0_we),
    .wd     (sw_rst_regwen_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_0_qs)
  );


  // Subregister 1 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_1]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_1_we),
    .wd     (sw_rst_regwen_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_1_qs)
  );


  // Subregister 2 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_2]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_2_we),
    .wd     (sw_rst_regwen_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_2_qs)
  );


  // Subregister 3 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_3]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_3_we),
    .wd     (sw_rst_regwen_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_3_qs)
  );


  // Subregister 4 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_4]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_4_we),
    .wd     (sw_rst_regwen_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_4_qs)
  );


  // Subregister 5 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_5]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_5_we),
    .wd     (sw_rst_regwen_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_5_qs)
  );


  // Subregister 6 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_6]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_6_we),
    .wd     (sw_rst_regwen_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_6_qs)
  );


  // Subregister 7 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_7]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_7_we),
    .wd     (sw_rst_regwen_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),

    // to register interface (read)
    .qs     (sw_rst_regwen_7_qs)
  );


  // Subregister 0 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_0]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_0_gated_we;
  assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_0_gated_we),
    .wd     (sw_rst_ctrl_n_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_0_qs)
  );


  // Subregister 1 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_1]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_1_gated_we;
  assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_1_gated_we),
    .wd     (sw_rst_ctrl_n_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_1_qs)
  );


  // Subregister 2 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_2]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_2_gated_we;
  assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_2_gated_we),
    .wd     (sw_rst_ctrl_n_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_2_qs)
  );


  // Subregister 3 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_3]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_3_gated_we;
  assign sw_rst_ctrl_n_3_gated_we = sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_3_gated_we),
    .wd     (sw_rst_ctrl_n_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_3_qs)
  );


  // Subregister 4 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_4]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_4_gated_we;
  assign sw_rst_ctrl_n_4_gated_we = sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_4_gated_we),
    .wd     (sw_rst_ctrl_n_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_4_qs)
  );


  // Subregister 5 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_5]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_5_gated_we;
  assign sw_rst_ctrl_n_5_gated_we = sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_5_gated_we),
    .wd     (sw_rst_ctrl_n_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_5_qs)
  );


  // Subregister 6 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_6]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_6_gated_we;
  assign sw_rst_ctrl_n_6_gated_we = sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_6_gated_we),
    .wd     (sw_rst_ctrl_n_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_6_qs)
  );


  // Subregister 7 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_7]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_7_gated_we;
  assign sw_rst_ctrl_n_7_gated_we = sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_7_gated_we),
    .wd     (sw_rst_ctrl_n_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[7].q),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_7_qs)
  );


  // R[err_code]: V(False)
  //   F[reg_intg_err]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_err_code_reg_intg_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (err_code_we),
    .wd     (err_code_reg_intg_err_wd),

    // from internal hardware
    .de     (hw2reg.err_code.reg_intg_err.de),
    .d      (hw2reg.err_code.reg_intg_err.d),
<commit_msg>[top/autogen] Add missing autogen file<commit_after>// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`

`include "prim_assert.sv"

module rstmgr_reg_top (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,
  // To HW
  output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write
  input  rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read

  // Integrity check errors
  output logic intg_err_o,

  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);

  import rstmgr_reg_pkg::* ;

  localparam int AW = 7;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [27:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(28)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  assign tl_reg_h2d = tl_i;
  assign tl_o_pre   = tl_reg_d2h;

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    .error_i (reg_error)
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic alert_test_we;
  logic alert_test_fatal_fault_wd;
  logic alert_test_fatal_cnsty_fault_wd;
  logic reset_req_we;
  logic [3:0] reset_req_qs;
  logic [3:0] reset_req_wd;
  logic reset_info_we;
  logic reset_info_por_qs;
  logic reset_info_por_wd;
  logic reset_info_low_power_exit_qs;
  logic reset_info_low_power_exit_wd;
  logic reset_info_ndm_reset_qs;
  logic reset_info_ndm_reset_wd;
  logic reset_info_sw_reset_qs;
  logic reset_info_sw_reset_wd;
  logic [3:0] reset_info_hw_req_qs;
  logic [3:0] reset_info_hw_req_wd;
  logic alert_regwen_we;
  logic alert_regwen_qs;
  logic alert_regwen_wd;
  logic alert_info_ctrl_we;
  logic alert_info_ctrl_en_qs;
  logic alert_info_ctrl_en_wd;
  logic [3:0] alert_info_ctrl_index_qs;
  logic [3:0] alert_info_ctrl_index_wd;
  logic alert_info_attr_re;
  logic [3:0] alert_info_attr_qs;
  logic alert_info_re;
  logic [31:0] alert_info_qs;
  logic cpu_regwen_we;
  logic cpu_regwen_qs;
  logic cpu_regwen_wd;
  logic cpu_info_ctrl_we;
  logic cpu_info_ctrl_en_qs;
  logic cpu_info_ctrl_en_wd;
  logic [3:0] cpu_info_ctrl_index_qs;
  logic [3:0] cpu_info_ctrl_index_wd;
  logic cpu_info_attr_re;
  logic [3:0] cpu_info_attr_qs;
  logic cpu_info_re;
  logic [31:0] cpu_info_qs;
  logic sw_rst_regwen_0_we;
  logic sw_rst_regwen_0_qs;
  logic sw_rst_regwen_0_wd;
  logic sw_rst_regwen_1_we;
  logic sw_rst_regwen_1_qs;
  logic sw_rst_regwen_1_wd;
  logic sw_rst_regwen_2_we;
  logic sw_rst_regwen_2_qs;
  logic sw_rst_regwen_2_wd;
  logic sw_rst_regwen_3_we;
  logic sw_rst_regwen_3_qs;
  logic sw_rst_regwen_3_wd;
  logic sw_rst_regwen_4_we;
  logic sw_rst_regwen_4_qs;
  logic sw_rst_regwen_4_wd;
  logic sw_rst_regwen_5_we;
  logic sw_rst_regwen_5_qs;
  logic sw_rst_regwen_5_wd;
  logic sw_rst_regwen_6_we;
  logic sw_rst_regwen_6_qs;
  logic sw_rst_regwen_6_wd;
  logic sw_rst_regwen_7_we;
  logic sw_rst_regwen_7_qs;
  logic sw_rst_regwen_7_wd;
  logic sw_rst_ctrl_n_0_we;
  logic sw_rst_ctrl_n_0_qs;
  logic sw_rst_ctrl_n_0_wd;
  logic sw_rst_ctrl_n_1_we;
  logic sw_rst_ctrl_n_1_qs;
  logic sw_rst_ctrl_n_1_wd;
  logic sw_rst_ctrl_n_2_we;
  logic sw_rst_ctrl_n_2_qs;
  logic sw_rst_ctrl_n_2_wd;
  logic sw_rst_ctrl_n_3_we;
  logic sw_rst_ctrl_n_3_qs;
  logic sw_rst_ctrl_n_3_wd;
  logic sw_rst_ctrl_n_4_we;
  logic sw_rst_ctrl_n_4_qs;
  logic sw_rst_ctrl_n_4_wd;
  logic sw_rst_ctrl_n_5_we;
  logic sw_rst_ctrl_n_5_qs;
  logic sw_rst_ctrl_n_5_wd;
  logic sw_rst_ctrl_n_6_we;
  logic sw_rst_ctrl_n_6_qs;
  logic sw_rst_ctrl_n_6_wd;
  logic sw_rst_ctrl_n_7_we;
  logic sw_rst_ctrl_n_7_qs;
  logic sw_rst_ctrl_n_7_wd;
  logic err_code_we;
  logic err_code_reg_intg_err_qs;
  logic err_code_reg_intg_err_wd;
  logic err_code_reset_consistency_err_qs;
  logic err_code_reset_consistency_err_wd;

  // Register instances
  // R[alert_test]: V(True)
  logic alert_test_qe;
  logic [1:0] alert_test_flds_we;
  assign alert_test_qe = &alert_test_flds_we;
  //   F[fatal_fault]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_fault (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_fault_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[0]),
    .q      (reg2hw.alert_test.fatal_fault.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;

  //   F[fatal_cnsty_fault]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_cnsty_fault (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_cnsty_fault_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[1]),
    .q      (reg2hw.alert_test.fatal_cnsty_fault.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe;


  // R[reset_req]: V(False)
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h9)
  ) u_reset_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_req_we),
    .wd     (reset_req_wd),

    // from internal hardware
    .de     (hw2reg.reset_req.de),
    .d      (hw2reg.reset_req.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_req_qs)
  );


  // R[reset_info]: V(False)
  //   F[por]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h1)
  ) u_reset_info_por (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_por_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_por_qs)
  );

  //   F[low_power_exit]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_low_power_exit (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_low_power_exit_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.low_power_exit.de),
    .d      (hw2reg.reset_info.low_power_exit.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_low_power_exit_qs)
  );

  //   F[ndm_reset]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_ndm_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_ndm_reset_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.ndm_reset.de),
    .d      (hw2reg.reset_info.ndm_reset.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_ndm_reset_qs)
  );

  //   F[sw_reset]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_reset_info_sw_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_sw_reset_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.sw_reset.de),
    .d      (hw2reg.reset_info.sw_reset.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_info.sw_reset.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_sw_reset_qs)
  );

  //   F[hw_req]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (4'h0)
  ) u_reset_info_hw_req (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (reset_info_we),
    .wd     (reset_info_hw_req_wd),

    // from internal hardware
    .de     (hw2reg.reset_info.hw_req.de),
    .d      (hw2reg.reset_info.hw_req.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.reset_info.hw_req.q),
    .ds     (),

    // to register interface (read)
    .qs     (reset_info_hw_req_qs)
  );


  // R[alert_regwen]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_alert_regwen (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_regwen_we),
    .wd     (alert_regwen_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (alert_regwen_qs)
  );


  // R[alert_info_ctrl]: V(False)
  // Create REGWEN-gated WE signal
  logic alert_info_ctrl_gated_we;
  assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs;
  //   F[en]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_alert_info_ctrl_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_info_ctrl_gated_we),
    .wd     (alert_info_ctrl_en_wd),

    // from internal hardware
    .de     (hw2reg.alert_info_ctrl.en.de),
    .d      (hw2reg.alert_info_ctrl.en.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.alert_info_ctrl.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (alert_info_ctrl_en_qs)
  );

  //   F[index]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0)
  ) u_alert_info_ctrl_index (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (alert_info_ctrl_gated_we),
    .wd     (alert_info_ctrl_index_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.alert_info_ctrl.index.q),
    .ds     (),

    // to register interface (read)
    .qs     (alert_info_ctrl_index_qs)
  );


  // R[alert_info_attr]: V(True)
  prim_subreg_ext #(
    .DW    (4)
  ) u_alert_info_attr (
    .re     (alert_info_attr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.alert_info_attr.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (alert_info_attr_qs)
  );


  // R[alert_info]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_alert_info (
    .re     (alert_info_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.alert_info.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (alert_info_qs)
  );


  // R[cpu_regwen]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_cpu_regwen (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_regwen_we),
    .wd     (cpu_regwen_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_regwen_qs)
  );


  // R[cpu_info_ctrl]: V(False)
  // Create REGWEN-gated WE signal
  logic cpu_info_ctrl_gated_we;
  assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs;
  //   F[en]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_cpu_info_ctrl_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_info_ctrl_gated_we),
    .wd     (cpu_info_ctrl_en_wd),

    // from internal hardware
    .de     (hw2reg.cpu_info_ctrl.en.de),
    .d      (hw2reg.cpu_info_ctrl.en.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cpu_info_ctrl.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_info_ctrl_en_qs)
  );

  //   F[index]: 7:4
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0)
  ) u_cpu_info_ctrl_index (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cpu_info_ctrl_gated_we),
    .wd     (cpu_info_ctrl_index_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cpu_info_ctrl.index.q),
    .ds     (),

    // to register interface (read)
    .qs     (cpu_info_ctrl_index_qs)
  );


  // R[cpu_info_attr]: V(True)
  prim_subreg_ext #(
    .DW    (4)
  ) u_cpu_info_attr (
    .re     (cpu_info_attr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.cpu_info_attr.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (cpu_info_attr_qs)
  );


  // R[cpu_info]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_cpu_info (
    .re     (cpu_info_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.cpu_info.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (cpu_info_qs)
  );


  // Subregister 0 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_0]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_0_we),
    .wd     (sw_rst_regwen_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_0_qs)
  );


  // Subregister 1 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_1]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_1_we),
    .wd     (sw_rst_regwen_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_1_qs)
  );


  // Subregister 2 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_2]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_2_we),
    .wd     (sw_rst_regwen_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_2_qs)
  );


  // Subregister 3 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_3]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_3_we),
    .wd     (sw_rst_regwen_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_3_qs)
  );


  // Subregister 4 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_4]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_4_we),
    .wd     (sw_rst_regwen_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_4_qs)
  );


  // Subregister 5 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_5]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_5_we),
    .wd     (sw_rst_regwen_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_5_qs)
  );


  // Subregister 6 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_6]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_6_we),
    .wd     (sw_rst_regwen_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_6_qs)
  );


  // Subregister 7 of Multireg sw_rst_regwen
  // R[sw_rst_regwen_7]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1)
  ) u_sw_rst_regwen_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_regwen_7_we),
    .wd     (sw_rst_regwen_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_regwen_7_qs)
  );


  // Subregister 0 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_0]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_0_gated_we;
  assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_0_gated_we),
    .wd     (sw_rst_ctrl_n_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_0_qs)
  );


  // Subregister 1 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_1]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_1_gated_we;
  assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_1_gated_we),
    .wd     (sw_rst_ctrl_n_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_1_qs)
  );


  // Subregister 2 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_2]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_2_gated_we;
  assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_2_gated_we),
    .wd     (sw_rst_ctrl_n_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_2_qs)
  );


  // Subregister 3 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_3]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_3_gated_we;
  assign sw_rst_ctrl_n_3_gated_we = sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_3_gated_we),
    .wd     (sw_rst_ctrl_n_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_3_qs)
  );


  // Subregister 4 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_4]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_4_gated_we;
  assign sw_rst_ctrl_n_4_gated_we = sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_4_gated_we),
    .wd     (sw_rst_ctrl_n_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_4_qs)
  );


  // Subregister 5 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_5]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_5_gated_we;
  assign sw_rst_ctrl_n_5_gated_we = sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_5_gated_we),
    .wd     (sw_rst_ctrl_n_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_5_qs)
  );


  // Subregister 6 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_6]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_6_gated_we;
  assign sw_rst_ctrl_n_6_gated_we = sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_6_gated_we),
    .wd     (sw_rst_ctrl_n_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_6_qs)
  );


  // Subregister 7 of Multireg sw_rst_ctrl_n
  // R[sw_rst_ctrl_n_7]: V(False)
  // Create REGWEN-gated WE signal
  logic sw_rst_ctrl_n_7_gated_we;
  assign sw_rst_ctrl_n_7_gated_we = sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs;
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_sw_rst_ctrl_n_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (sw_rst_ctrl_n_7_gated_we),
    .wd     (sw_rst_ctrl_n_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.sw_rst_ctrl_n[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (sw_rst_ctrl_n_7_qs)
  );


  // R[err_code]: V(False)
  //   F[reg_intg_err]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_err_code_reg_intg_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (err_code_we),
    .wd     (err_code_reg_intg_err_wd),

    // from internal hardware
    .de     (hw2reg.err_code.reg_intg_err.de),
    .d      (hw2reg.err_code.reg_intg_err.d),

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