<commit_before>/* Title:   SparcRegClassInfo.h    -*- C++ -*-
   Author:  <NAME>
   Date:    Aug 20, 01
   Purpose: Contains the description of integer register class of Sparc
*/


#ifndef SPARC_REG_INFO_CLASS_H
#define SPARC_REG_INFO_CLASS_H

#include "llvm/Target/MachineRegInfo.h"
#include "llvm/CodeGen/IGNode.h"

//-----------------------------------------------------------------------------
// Integer Register Class
//-----------------------------------------------------------------------------


// Int register names in same order as enum in class SparcIntRegOrder

static string const IntRegNames[] = 
  {  
    "o0", "o1", "o2", "o3", "o4", "o5",       "o7",
    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
    "i0", "i1", "i2", "i3", "i4", "i5",  
    "g0", "g1", "g2", "g3", "g4", "g5",  "g6", "g7", 
    "i6", "i7", "o6" }; 



class SparcIntRegOrder{ 

 public:

  enum RegsInPrefOrder   // colors possible for a LR (in preferred order)
   { 
     // --- following colors are volatile across function calls
     // %g0 can't be used for coloring - always 0
                     
     //%g1-%g5  (g6-7 are reserved for system)  
     o0, o1, o2, o3, o4, o5, o7,  // %o0-%o5, 

     // %o6 is sp, 
     // all %0's can get modified by a call

     // --- following colors are NON-volatile across function calls
      
     l0, l1, l2, l3, l4, l5, l6, l7,    //  %l0-%l7
     i0, i1, i2, i3, i4, i5,         // %i0-%i5: i's need not be preserved 
      
     // %i6 is the fp - so not allocated
     // %i7 is the ret address by convention - can be used for others

     // max # of colors reg coloring  can allocate (NumOfAvailRegs)

     // --- following colors are not available for allocation within this phase
     // --- but can appear for pre-colored ranges 

     g0,  g1, g2, g3, g4, g5, g6, g7, i6, i7,  o6

     //*** NOTE: If we decide to use globals, some of them are volatile 
     //**** see sparc64ABI (change isRegVloatile method below)
 

   };

  // max # of colors reg coloring  can allocate
  static unsigned int const NumOfAvailRegs = g0;

  static unsigned int const StartOfNonVolatileRegs = l0;
  static unsigned int const StartOfAllRegs = o0;
  static unsigned int const NumOfAllRegs = o6 + 1; 


  static const string  getRegName(const unsigned reg) {
    assert( reg < NumOfAllRegs );
    return IntRegNames[reg];
  }

};



class SparcIntRegClass : public MachineRegClassInfo
{
 public:

  SparcIntRegClass(unsigned ID) 
    : MachineRegClassInfo(ID, 
			  SparcIntRegOrder::NumOfAvailRegs,
			  SparcIntRegOrder::NumOfAllRegs)
    {  }

  void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;

  inline bool isRegVolatile(const int Reg) const {
    return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs); 
  }

};<commit_msg>Reordered registers slightly to simplify a new check. Added a function to map between the caller's and callee's register windows.<commit_after>/* Title:   SparcRegClassInfo.h    -*- C++ -*-
   Author:  <NAME>
   Date:    Aug 20, 01
   Purpose: Contains the description of integer register class of Sparc
*/


#ifndef SPARC_REG_INFO_CLASS_H
#define SPARC_REG_INFO_CLASS_H

#include "llvm/Target/MachineRegInfo.h"
#include "llvm/CodeGen/IGNode.h"

//-----------------------------------------------------------------------------
// Integer Register Class
//-----------------------------------------------------------------------------


// Int register names in same order as enum in class SparcIntRegOrder

static string const IntRegNames[] = 
  {  
    "o0", "o1", "o2", "o3", "o4", "o5",       "o7",
    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
    "i0", "i1", "i2", "i3", "i4", "i5",  
    "i6", "i7",
    "g0", "g1", "g2", "g3", "g4", "g5",  "g6", "g7", 
    "o6" }; 



class SparcIntRegOrder{ 

 public:

  enum RegsInPrefOrder   // colors possible for a LR (in preferred order)
   { 
     // --- following colors are volatile across function calls
     // %g0 can't be used for coloring - always 0
                     
     //%g1-%g5  (g6-7 are reserved for system)  
     o0, o1, o2, o3, o4, o5, o7,  // %o0-%o5, 

     // %o6 is sp, 
     // all %0's can get modified by a call

     // --- following colors are NON-volatile across function calls
      
     l0, l1, l2, l3, l4, l5, l6, l7,    //  %l0-%l7
     i0, i1, i2, i3, i4, i5,         // %i0-%i5: i's need not be preserved 
      
     // %i6 is the fp - so not allocated
     // %i7 is the ret address by convention - can be used for others

     // max # of colors reg coloring  can allocate (NumOfAvailRegs)

     // --- following colors are not available for allocation within this phase
     // --- but can appear for pre-colored ranges 

     i6, i7, g0,  g1, g2, g3, g4, g5, g6, g7, o6
     
     //*** NOTE: If we decide to use globals, some of them are volatile 
     //**** see sparc64ABI (change isRegVloatile method below)
 

   };

  // max # of colors reg coloring  can allocate
  static unsigned int const NumOfAvailRegs = g0;

  static unsigned int const StartOfNonVolatileRegs = l0;
  static unsigned int const StartOfAllRegs = o0;
  static unsigned int const NumOfAllRegs = o6 + 1; 


  static const string  getRegName(const unsigned reg) {
    assert( reg < NumOfAllRegs );
    return IntRegNames[reg];
  }

  static unsigned int getRegNumInCallersWindow(const unsigned reg) {
    if (reg <= l7 || reg == o6) {
      assert(0 && "registers o0-o7 and l0-l7 are not visible in caller");
      return reg;
    }
    if (reg <= i7)
      return reg - (i0 - o0);
    assert((reg >= g0 || reg <= g7) && "Unrecognized integer register number");
      return reg;
  }
};



class SparcIntRegClass : public MachineRegClassInfo
{
 public:

  SparcIntRegClass(unsigned ID) 
    : MachineRegClassInfo(ID, 
			  SparcIntRegOrder::NumOfAvailRegs,
			  SparcIntRegOrder::NumOfAllRegs)
    {  }

  void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;

  inline bool isRegVolatile(const int Reg) const {
    return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs); 
  }

};
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