<commit_before>; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck --check-prefixes=CHECK,VMOVSR %s
; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp %s -o - | FileCheck --check-prefixes=CHECK,NEON %s

define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
  %1 = fcmp nsz olt float undef, 0.000000e+00
  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
  ret float %2
}
; CHECK-LABEL: foo0
; CHECK: vcmpe.f32 {{s[0-9]+}}, #0


define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
  br i1 undef, label %.end, label %1

  %2 = fcmp nsz olt float undef, 1.000000e+00
  %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
  br label %.end

.end:
  %4 = phi float [ undef, %0 ], [ %3, %1]
  ret float %4
}
; CHECK-LABEL: float1
; CHECK: vmov.f32 [[FPREG:s[0-9]+]], #1.000000e+00
; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}

define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
  %1 = fcmp nsz olt float undef, 128.000000e+00
  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
  ret float %2
}
; CHECK-LABEL: float128
; CHECK: mov.w [[REG:r[0-9]+]], #1124073472
; VMOVSR: vmov [[FPREG:s[0-9]+]], [[REG]]
; VMOVSR: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
; NEON: vmov d2, [[REG]], [[REG]]
; NEON: vcmpe.f32 s4, {{s[0-9]+}}


define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
  %1 = fcmp nsz olt double undef, 1.000000e+00
  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
  ret double %2
}
; CHECK-LABEL: double1
; CHECK: vmov.f64 [[FPREG:d[0-9]+]], #1.000000e+00
; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}

define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
  %1 = fcmp nsz olt double undef, 128.000000e+00
  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
  ret double %2
}
; CHECK-LABEL: double128
; CHECK: movs [[REGH:r[0-9]+]], #0
; CHECK: movt [[REGH]], #16480
; CHECK: movs [[REGL:r[0-9]+]], #0
; CHECK: vmov [[FPREG:d[0-9]+]], [[REGL]], [[REGH]]
; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
<commit_msg>[ARM] Regenerate execute-only float comparison tests<commit_after>; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR
; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON

define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
; CHECK-LABEL: foo0:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    vmov.f32 s0, #5.000000e-01
; CHECK-NEXT:    vmov.f32 s2, #-5.000000e-01
; CHECK-NEXT:    vcmpe.f32 s0, #0
; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-NEXT:    it mi
; CHECK-NEXT:    vmovmi.f32 s0, s2
; CHECK-NEXT:    bx lr
  %1 = fcmp nsz olt float undef, 0.000000e+00
  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
  ret float %2
}

define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
; CHECK-LABEL: float1:
; CHECK:       @ %bb.0: @ %.end
; CHECK-NEXT:    vmov.f32 s0, #1.000000e+00
; CHECK-NEXT:    vmov.f32 s2, #5.000000e-01
; CHECK-NEXT:    vmov.f32 s4, #-5.000000e-01
; CHECK-NEXT:    vcmpe.f32 s0, s0
; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-NEXT:    vselgt.f32 s0, s4, s2
; CHECK-NEXT:    bx lr
  br i1 undef, label %.end, label %1

  %2 = fcmp nsz olt float undef, 1.000000e+00
  %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
  br label %.end

.end:
  %4 = phi float [ undef, %0 ], [ %3, %1]
  ret float %4
}

define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
; VMOVSR-LABEL: float128:
; VMOVSR:       @ %bb.0:
; VMOVSR-NEXT:    mov.w r0, #1124073472
; VMOVSR-NEXT:    vmov.f32 s2, #5.000000e-01
; VMOVSR-NEXT:    vmov s0, r0
; VMOVSR-NEXT:    vmov.f32 s4, #-5.000000e-01
; VMOVSR-NEXT:    vcmpe.f32 s0, s0
; VMOVSR-NEXT:    vmrs APSR_nzcv, fpscr
; VMOVSR-NEXT:    vselgt.f32 s0, s4, s2
; VMOVSR-NEXT:    bx lr
;
; NEON-LABEL: float128:
; NEON:       @ %bb.0:
; NEON-NEXT:    vmov.f32 s0, #5.000000e-01
; NEON-NEXT:    mov.w r0, #1124073472
; NEON-NEXT:    vmov d2, r0, r0
; NEON-NEXT:    vmov.f32 s2, #-5.000000e-01
; NEON-NEXT:    vcmpe.f32 s4, s0
; NEON-NEXT:    vmrs APSR_nzcv, fpscr
; NEON-NEXT:    vselgt.f32 s0, s2, s0
; NEON-NEXT:    bx lr
  %1 = fcmp nsz olt float undef, 128.000000e+00
  %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
  ret float %2
}

define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
; CHECK-LABEL: double1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
; CHECK-NEXT:    vmov.f64 d18, #1.000000e+00
; CHECK-NEXT:    vcmpe.f64 d18, d16
; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
; CHECK-NEXT:    vselgt.f64 d0, d17, d16
; CHECK-NEXT:    bx lr
  %1 = fcmp nsz olt double undef, 1.000000e+00
  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
  ret double %2
}

define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
; CHECK-LABEL: double128:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
; CHECK-NEXT:    movs r0, #0
; CHECK-NEXT:    movt r0, #16480
; CHECK-NEXT:    movs r1, #0
; CHECK-NEXT:    vmov d18, r1, r0
; CHECK-NEXT:    vcmpe.f64 d18, d16
; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
; CHECK-NEXT:    vselgt.f64 d0, d17, d16
; CHECK-NEXT:    bx lr
  %1 = fcmp nsz olt double undef, 128.000000e+00
  %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
  ret double %2
}
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