<commit_before>/*
 *  nextpnr -- Next Generation Place and Route
 *
 *  Copyright (C) 2018  gatecat <<EMAIL>>
 *  Copyright (C) 2021  <NAME> <<EMAIL>>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include <fstream>

#include "bitstream.h"
#include "config.h"
#include "nextpnr.h"
#include "util.h"

NEXTPNR_NAMESPACE_BEGIN

// These seem simple enough to do inline for now.
namespace BaseConfigs {
void config_empty_lcmxo2_1200hc(ChipConfig &cc)
{
    cc.chip_name = "LCMXO2-1200HC";

    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);

    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
    cc.tiles["PT4:CFG0"].add_unknown(5, 36);

    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
}
} // namespace BaseConfigs

// Convert an absolute wire name to a relative Trellis one
static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
{
    std::string basename = ctx->tile_info(wire)->wire_data[wire.index].name.get();
    std::string prefix2 = basename.substr(0, 2);
    std::string prefix7 = basename.substr(0, 7);
    int max_col = ctx->chip_info->width - 1;

    // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose
    // relative coords push them outside the bounds of the chip.
    auto is_pio_wire = [](std::string name) {
        return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
                name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
                name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
                name.find("JCE") != std::string::npos || name.find("JCLK") != std::string::npos ||
                name.find("JLSR") != std::string::npos || name.find("JONEG") != std::string::npos ||
                name.find("JOPOS") != std::string::npos || name.find("JTS") != std::string::npos ||
                name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
                // Connections to global mux
                name.find("JINCK") != std::string::npos);
    };

    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
        return basename;

    if (prefix2 == "U_" || prefix2 == "D_") {
        // We needded to keep U_ and D_ prefixes to generate the routing
        // graph connections properly, but in truth they are not relevant
        // outside of the center row of tiles as far as the database is
        // concerned. So convert U_/D_ prefixes back to G_ if not in the
        // center row.

        // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
        // add a center row/col field to chipdb?
        if (loc.y == 6)
            return basename;
        else
            return "G_" + basename.substr(2);
    }

    if (loc == wire.location) {
        // TODO: JINCK is not currently handled by this.
        if (is_pio_wire(basename)) {
            if (wire.location.x == 0)
                return "W1_" + basename;
            else if (wire.location.x == max_col)
                return "E1_" + basename;
        }<commit_msg>machxo2: Correct which PIO wires get adjusted when writing text bitstream. Add verbose logging for adjustments.<commit_after>/*
 *  nextpnr -- Next Generation Place and Route
 *
 *  Copyright (C) 2018  gatecat <<EMAIL>>
 *  Copyright (C) 2021  <NAME> <<EMAIL>>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include <fstream>
#include <iostream>

#include "bitstream.h"
#include "config.h"
#include "nextpnr.h"
#include "util.h"

NEXTPNR_NAMESPACE_BEGIN

// These seem simple enough to do inline for now.
namespace BaseConfigs {
void config_empty_lcmxo2_1200hc(ChipConfig &cc)
{
    cc.chip_name = "LCMXO2-1200HC";

    cc.tiles["EBR_R6C11:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C15:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C18:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C21:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C2:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C5:EBR1"].add_unknown(0, 12);
    cc.tiles["EBR_R6C8:EBR1"].add_unknown(0, 12);

    cc.tiles["PT4:CFG0"].add_unknown(5, 30);
    cc.tiles["PT4:CFG0"].add_unknown(5, 32);
    cc.tiles["PT4:CFG0"].add_unknown(5, 36);

    cc.tiles["PT7:CFG3"].add_unknown(5, 18);
}
} // namespace BaseConfigs

// Convert an absolute wire name to a relative Trellis one
static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
{
    std::string basename = ctx->tile_info(wire)->wire_data[wire.index].name.get();
    std::string prefix2 = basename.substr(0, 2);
    std::string prefix7 = basename.substr(0, 7);
    int max_col = ctx->chip_info->width - 1;

    // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose
    // relative coords push them outside the bounds of the chip.
    // Indents are based on wires proximity/purpose.
    auto is_pio_wire = [](std::string name) {
        return (name.find("DI") != std::string::npos || name.find("JDI") != std::string::npos ||
                    name.find("PADD") != std::string::npos || name.find("INDD") != std::string::npos ||
                    name.find("IOLDO") != std::string::npos || name.find("IOLTO") != std::string::npos ||
                // JCE0-3, JCLK0-3, JLSR0-3 connect to PIO wires named JCEA-D, JCLKA-D, JLSRA-D.
                name.find("JCEA") != std::string::npos || name.find("JCEB") != std::string::npos ||
                    name.find("JCEC") != std::string::npos || name.find("JCED") != std::string::npos ||
                    name.find("JCLKA") != std::string::npos || name.find("JCLKB") != std::string::npos ||
                    name.find("JCLKC") != std::string::npos || name.find("JCLKD") != std::string::npos ||
                    name.find("JLSRA") != std::string::npos || name.find("JLSRB") != std::string::npos ||
                    name.find("JLSRC") != std::string::npos || name.find("JLSRD") != std::string::npos ||
                name.find("JONEG") != std::string::npos || name.find("JOPOS") != std::string::npos ||
                    name.find("JTS") != std::string::npos ||
                name.find("JIN") != std::string::npos || name.find("JIP") != std::string::npos ||
                // Connections to global mux
                name.find("JINCK") != std::string::npos);
    };

    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
        return basename;

    if (prefix2 == "U_" || prefix2 == "D_") {
        // We needded to keep U_ and D_ prefixes to generate the routing
        // graph connections properly, but in truth they are not relevant
        // outside of the center row of tiles as far as the database is
        // concerned. So convert U_/D_ prefixes back to G_ if not in the
        // center row.

        // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
        // add a center row/col field to chipdb?
        if (loc.y == 6)
            return basename;
        else
            return "G_" + basename.substr(2);
    }

    if (loc == wire.location) {
        // TODO: JINCK is not currently handled by this.
        if (is_pio_wire(basename)) {
            if (wire.location.x == 0) {
                std::string pio_name = "W1_" + basename;
                if (ctx->verbose)
                    log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", \
                        ctx->nameOfWire(wire), pio_name.c_str());
                return pio_name;
            } else if (wire.location.x == max_col) {
                std::string pio_name = "E1_" + basename;
                if (ctx->verbose)
                    log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", \
                        ctx->nameOfWire(wire), pio_name.c_str());
                return pio_name;
            }
        }
{'fraction_non_alphanumeric': 0.14382490880667015, 'fraction_numerical': 0.02324127149557061, 'mean_word_length': 2.7528353539303874, 'pattern_counts': {'":': 0, '<': 16, '<?xml version=': 0, '>': 28, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1835272', 'n_tokens_mistral': 3333, 'n_tokens_neox': 3118, 'n_words': 868}