<commit_before>/*
 * DRA752 thermal data.
 *
 * Copyright (C) 2013 Texas Instruments Inc.
 * Contact:
 *	<NAME> <<EMAIL>>
 *	<NAME> <<EMAIL>>
 *
 * This file is partially autogenerated.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 */

#include "ti-thermal.h"
#include "ti-bandgap.h"
#include "dra752-bandgap.h"

/*
 * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
 * IVA and DSPEVE need to describe the individual registers and
 * bit fields.
 */

/*
 * DRA752 CORE thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_core_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
};

/*
 * DRA752 IVA thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_iva_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
};

/*
 * DRA752 MPU thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_mpu_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
};

/*
 * DRA752 DSPEVE thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_dspeve_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
};

/*
 * DRA752 GPU thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_gpu_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,<commit_msg>thermal: ti-soc-thermal: Initialize counter_delay field for TI DRA752 sensors<commit_after>/*
 * DRA752 thermal data.
 *
 * Copyright (C) 2013 Texas Instruments Inc.
 * Contact:
 *	<NAME> <<EMAIL>>
 *	<NAME> <<EMAIL>>
 *
 * This file is partially autogenerated.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 */

#include "ti-thermal.h"
#include "ti-bandgap.h"
#include "dra752-bandgap.h"

/*
 * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
 * IVA and DSPEVE need to describe the individual registers and
 * bit fields.
 */

/*
 * DRA752 CORE thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_core_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
};

/*
 * DRA752 IVA thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_iva_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
};

/*
 * DRA752 MPU thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_mpu_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
};

/*
 * DRA752 DSPEVE thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_dspeve_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
	.tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
	.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
	.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
	.ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
	.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
	.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
	.ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
	.ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
};

/*
 * DRA752 GPU thermal sensor register offsets and bit-fields
 */
static struct temp_sensor_registers
dra752_gpu_temp_sensor_registers = {
	.temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
	.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
	.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
	.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
{'fraction_non_alphanumeric': 0.05869035179380007, 'fraction_numerical': 0.059851387437594335, 'mean_word_length': 8.212299465240642, 'pattern_counts': {'":': 0, '<': 15, '<?xml version=': 0, '>': 15, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7482235', 'n_tokens_mistral': 8701, 'n_tokens_neox': 8119, 'n_words': 865}