<commit_before>/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 *
 * GIC Register Definitions
 *
 */
#ifndef _ASM_GICREGS_H
#define _ASM_GICREGS_H

#undef	GICISBYTELITTLEENDIAN
#define GICISWORDLITTLEENDIAN

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0

#if CONFIG_SMP
#define GIC_NUM_INTRS			(24 + NR_CPUS * 2)
#else
#define GIC_NUM_INTRS			32
#endif

#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr)		(*(volatile unsigned int *) (addr))
#define REG(base, offs)		REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys)	REG32((unsigned long)(base) + (phys))

/* Accessors */
#define GIC_REG(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ADDR(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset)

#define GIC_ABS_REG(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ABS_ADDR(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset)

#ifdef GICISBYTELITTLEENDIAN
#define GICREAD(reg, data)	(data) = (reg), (data) = le32_to_cpu(data)
#define GICWRITE(reg, data)	(reg) = cpu_to_le32(data)
#define GICBIS(reg, bits)			\
	({unsigned int data;			\
		GICREAD(reg, data);		\<commit_msg>MIPS: Fix compile for !CONFIG_SMP<commit_after>/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 *
 * GIC Register Definitions
 *
 */
#ifndef _ASM_GICREGS_H
#define _ASM_GICREGS_H

#undef	GICISBYTELITTLEENDIAN
#define GICISWORDLITTLEENDIAN

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0

#ifdef CONFIG_SMP
#define GIC_NUM_INTRS			(24 + NR_CPUS * 2)
#else
#define GIC_NUM_INTRS			32
#endif

#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr)		(*(volatile unsigned int *) (addr))
#define REG(base, offs)		REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys)	REG32((unsigned long)(base) + (phys))

/* Accessors */
#define GIC_REG(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ADDR(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset)

#define GIC_ABS_REG(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ABS_ADDR(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset)

#ifdef GICISBYTELITTLEENDIAN
#define GICREAD(reg, data)	(data) = (reg), (data) = le32_to_cpu(data)
#define GICWRITE(reg, data)	(reg) = cpu_to_le32(data)
#define GICBIS(reg, bits)			\
	({unsigned int data;			\
		GICREAD(reg, data);		\
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