<commit_before>FLTCPU
======
## Introduction ##
The fltfpga CPU is a simple RISC processor core. We could have used an
ARM clone, RISC-V, OpenRISC or a number of different CPU cores. But what
is the fun with that?

Anyway, the CPU is a 32-bit CPU with a very limited instruction set. The
machines has a shared code and data memory to allow dymanic/self
modifying code, use data as code and other fun things. I/O including
is memory mapped too. Oh and the program counter (PC) and return address
(RET) are of course normal registers so one can manipulate the PC and
RET from SW. Running code backwards by shifting the PC? Jumping by
setting RET and do a RTS? Should be doable.

The machine reads 32-bit aligned words. But can write independent bytes
(one to four) to memory.

The first version of the machine will only support integer arithmetic.


## Architecture ##
- Endianness:    Big endian, 32-bit data words.
- Address space: At least 24 bits. Word oriented.
- Registers:     32 or 64 registers, 32 bits wide.
- Opcodes:       Max 64 opcodes.
- Instructions:  Always a single word (32 bits)
- Execution:     Single scalar, in order and variable number of cycles. No delay slots or API visible pipeline artifacts.
- Status:        Separate register.


## Register map ##
32 registers in total. All registers are directly writeable by SW. This means that one can easily jump, change status regs, manipulate return addresses.

- r00: Zero registers (ZERO). Will always return zero.
- r01..r28: General registers (GP01..GP28).
- r29: status register (STATUS). (zero, carry, equal etc...) Not a complete register. Only the specified bits are actually there.
- r30: return address (RET).
- r31: program counter (PC).


## Instruction types and structure ##
- reg, reg -> reg operations
  (AND, OR, XOR, ADD, SUB, MUL)
  6 bit opcode, 5 bit dst, 5 bit src0, 5 bit src0 = 6 + 15 = 21 + x bits

- reg -> reg operations
  (ROL, ROR, ASL, ASR, NOT, RD, WR)<commit_msg>Added note about that the return register is a stack.<commit_after>FLTCPU
======
## Introduction ##
The fltfpga CPU is a simple RISC processor core. We could have used an
ARM clone, RISC-V, OpenRISC or a number of different CPU cores. But what
is the fun with that?

Anyway, the CPU is a 32-bit CPU with a very limited instruction set. The
machines has a shared code and data memory to allow dymanic/self
modifying code, use data as code and other fun things. I/O including
is memory mapped too. Oh and the program counter (PC) and return address
(RET) are of course normal registers so one can manipulate the PC and
RET from SW. Running code backwards by shifting the PC? Jumping by
setting RET and do a RTS? Should be doable.

The machine reads 32-bit aligned words. But can write independent bytes
(one to four) to memory.

The first version of the machine will only support integer arithmetic.


## Architecture ##
- Endianness:    Big endian, 32-bit data words.
- Address space: At least 24 bits. Word oriented.
- Registers:     32 or 64 registers, 32 bits wide.
- Opcodes:       Max 64 opcodes.
- Instructions:  Always a single word (32 bits)
- Execution:     Single scalar, in order and variable number of cycles. No delay slots or API visible pipeline artifacts.
- Status:        Separate register.


## Register map ##
32 registers in total. All registers are directly writeable by SW. This means that one can easily jump, change status regs, manipulate return addresses.

- r00: Zero registers (ZERO). Will always return zero.
- r01..r28: General registers (GP01..GP28).
- r29: status register (STATUS). (zero, carry, equal etc...) Not a complete register. Only the specified bits are actually there.
- r30: return address (RET). Is actualla a Top Of Stack (TOS) element. JSR pushes. RTS pops. Any other writes just updates the TOS.
- r31: program counter (PC).


## Instruction types and structure ##
- reg, reg -> reg operations
  (AND, OR, XOR, ADD, SUB, MUL)
  6 bit opcode, 5 bit dst, 5 bit src0, 5 bit src0 = 6 + 15 = 21 + x bits

- reg -> reg operations
  (ROL, ROR, ASL, ASR, NOT, RD, WR)
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