<commit_before># Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

import logging
import re
import subprocess
from pathlib import Path

from . import utils

log = logging.getLogger(__name__)


class VerilatorSimOpenTitan:
    UART0_SPEED = 7200  # see device/lib/arch/device_sim_verilator.c

    def __init__(self,
                 sim_path: Path,
                 rom_vmem_path: Path,
                 otp_img_path: Path,
                 work_dir: Path,
                 boot_timeout: int = 120,
                 test_timeout: int = 600):
        """ A verilator simulation of an OpenTitan toplevel """
        assert sim_path.is_file()
        self._sim_path = sim_path

        self.p_sim = None
<commit_msg>[ci] Increase timeouts in Verilator simulation<commit_after># Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

import logging
import re
import subprocess
from pathlib import Path

from . import utils

log = logging.getLogger(__name__)


class VerilatorSimOpenTitan:
    UART0_SPEED = 7200  # see device/lib/arch/device_sim_verilator.c

    def __init__(self,
                 sim_path: Path,
                 rom_vmem_path: Path,
                 otp_img_path: Path,
                 work_dir: Path,
                 boot_timeout: int = 4*60,
                 test_timeout: int = 20*60):
        """ A verilator simulation of an OpenTitan toplevel """
        assert sim_path.is_file()
        self._sim_path = sim_path

        self.p_sim = None

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