<commit_before>yosys -import
if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
yosys -import  ;# ingest plugin commands

read_verilog dsp_macc.v
design -save read

set TOP "macc_simple"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:*

set TOP "macc_simple_clr"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:\$lut
select -assert-count 2 t:*

set TOP "macc_simple_arst"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:*

set TOP "macc_simple_ena"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:*

set TOP "macc_simple_arst_clr_ena"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:\$lut
select -assert-count 2 t:*

set TOP "macc_simple_preacc"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:*

set TOP "macc_simple_preacc_clr"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:dsp_t1_10x9x32
select -assert-count 1 t:\$lut
select -assert-count 2 t:*
<commit_msg>Renamed the target DSP cells in the MACC inference test<commit_after>yosys -import
if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
yosys -import  ;# ingest plugin commands

read_verilog dsp_macc.v
design -save read

set TOP "macc_simple"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:*

set TOP "macc_simple_clr"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:\$lut
select -assert-count 2 t:*

set TOP "macc_simple_arst"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:*

set TOP "macc_simple_ena"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:*

set TOP "macc_simple_arst_clr_ena"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:\$lut
select -assert-count 2 t:*

set TOP "macc_simple_preacc"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:*

set TOP "macc_simple_preacc_clr"
design -load read
hierarchy -top $TOP
synth_quicklogic -family qlf_k6n10f -top $TOP
yosys cd $TOP
select -assert-count 1 t:QL_DSP2
select -assert-count 1 t:\$lut
select -assert-count 2 t:*

{'fraction_non_alphanumeric': 0.0904922042188933, 'fraction_numerical': 0.03821461326811373, 'mean_word_length': 4.508417508417509, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5931242', 'n_tokens_mistral': 1449, 'n_tokens_neox': 1334, 'n_words': 421}