<commit_before>
#include <hw/cpu/cpu.h>
#include <stdint.h>

#if TARGET_MSDOS == 32
typedef unsigned char *VGA_RAM_PTR;
typedef uint16_t *VGA_ALPHA_PTR;
#else
typedef unsigned char far *VGA_RAM_PTR;
typedef uint16_t far *VGA_ALPHA_PTR;
#endif

/* vga_flags */
#define VGA_IS_TANDY			0x02	/* Tandy/PCjr */
#define VGA_IS_HGC			0x04
#define VGA_IS_MCGA			0x08
#define VGA_IS_VGA			0x10
#define VGA_IS_EGA			0x20
#define VGA_IS_CGA			0x40
#define VGA_IS_MDA			0x80
#define VGA_IS_AMSTRAD			0x100

/* sequencer index */
#define VGA_AC_ENABLE			0x20

/* graphics controller regs */
#define VGA_GC_DATA_ROTATE_OP_NONE		(0 << 3)
#define VGA_GC_DATA_ROTATE_OP_AND		(1 << 3)
#define VGA_GC_DATA_ROTATE_OP_OR		(2 << 3)
#define VGA_GC_DATA_ROTATE_OP_XOR		(3 << 3)

/* font manipulation vars */
#define VGA_EGA_BYTES_PER_CHAR_BITMAP		32
#define VGA_EGA_BYTES_PER_CHAR_BITMAP_SHIFT	5

/* EGA/VGA memory map bits */
enum {
	VGA_MEMMAP_A0000_128K=0,
	VGA_MEMMAP_A0000_64K,
	VGA_MEMMAP_B0000_32K,
	VGA_MEMMAP_B8000_32K
};

enum {
	VGA_CGA_MODE_40WIDE=0,
	VGA_CGA_MODE_80WIDE=0x01,
	VGA_CGA_MODE_GRAPHICS=0x02,
	VGA_CGA_MODE_BW=0x04,
	VGA_CGA_MODE_VIDEO_ENABLE=0x08,
	VGA_CGA_MODE_VIDEO_640=0x10,
	VGA_CGA_MODE_NO_BLINKING=0x20
};

/* sequencer registers */
enum {
	VGA_SC_MAP_MASK=2
};

/* graphics controller registers */
enum {
	VGA_GC_ENABLE_SET_RESET=0,
	VGA_GC_SET_RESET=1,
	VGA_GC_DATA_ROTATE=3,
	VGA_GC_MODE=5,
	VGA_GC_BIT_MASK=8
};

enum { /* CGA palette selection (320x200x4) */
	VGA_CGA_PALETTE_GR_BR_RD=0,
	VGA_CGA_PALETTE_CY_MA_WH=1
};

enum { /* color select (text=border color  320x200=background    640x200=foreground */
	VGA_CGA_PALETTE_CS_BLUE=(1U << 0U),
	VGA_CGA_PALETTE_CS_GREEN=(1U << 1U),
	VGA_CGA_PALETTE_CS_RED=(1U << 2U),
	VGA_CGA_PALETTE_CS_INTENSITY=(1U << 3U),
	VGA_CGA_PALETTE_CS_ALT_INTENSITY=(1U << 4U)
};

extern VGA_RAM_PTR	vga_graphics_ram;
extern VGA_RAM_PTR	vga_graphics_ram_fence;
extern VGA_ALPHA_PTR	vga_alpha_ram;
extern VGA_ALPHA_PTR	vga_alpha_ram_fence;

extern uint32_t		vga_clock_rates[4];
extern unsigned char	vga_pos_x,vga_pos_y,vga_color;
extern unsigned char	vga_width,vga_height;
extern unsigned char	vga_alpha_mode;
extern unsigned char	vga_hgc_type;
extern unsigned int	vga_base_3x0;
extern unsigned long	vga_ram_base;
extern unsigned long	vga_ram_size;
extern unsigned char	vga_stride;
extern unsigned short	vga_flags;
extern unsigned char	vga_9wide;

unsigned char int10_getmode();
void vga_write(const char *msg);
void int10_setmode(unsigned char mode);
void update_state_vga_memory_map_select(unsigned char c);
unsigned char vga_force_read(const VGA_RAM_PTR p);
void vga_force_write(VGA_RAM_PTR p,const unsigned char c);
void vga_force_write_w(VGA_ALPHA_PTR p,const unsigned short c);
int check_vga_3C0();
void vga_sync_hw_cursor();
void vga_sync_bios_cursor();
void update_state_vga_memory_map_select(unsigned char c);
void vga_set_memory_map(unsigned char c);
void vga_bios_set_80x50_text();
void update_state_from_vga();
int probe_vga();
void vga_write_state_DEBUG(FILE *f);
void vga_relocate_crtc(unsigned char color);
void vga_switch_to_mono();
void vga_switch_to_color();
void vga_turn_on_hgc();
void vga_turn_off_hgc();
void vga_set_cga_palette_and_background(unsigned char pal,unsigned char color);
void vga_set_cga_mode(unsigned char b);
void vga_tandy_setpalette(unsigned char i,unsigned char c);
void vga_enable_256color_modex();
void vga_set_stride(unsigned int stride);
void vga_set_start_location(unsigned int offset);
void vga_set_ypan_sub(unsigned char c);
void vga_set_xpan(unsigned char c);
void vga_splitscreen(unsigned int v);
void vga_alpha_switch_to_font_plane();
void vga_alpha_switch_from_font_plane();
void vga_set_9wide(unsigned char en);
void vga_select_charset_a_b(unsigned short a,unsigned short b);
void vga_correct_crtc_mode(struct vga_mode_params *p);
void vga_write_crtc_mode(struct vga_mode_params *p);
void vga_read_crtc_mode(struct vga_mode_params *p);

static inline unsigned char vga_read_CRTC(unsigned char i) {
	outp(vga_base_3x0+4,i);
	return inp(vga_base_3x0+5);
}

static inline unsigned char vga_read_GC(unsigned char i) {
	outp(0x3CE,i);
	return inp(0x3CF);
}

static inline unsigned char vga_read_sequencer(unsigned char i) {
	outp(0x3C4,i);
	return inp(0x3C5);
}

static inline void vga_write_sequencer(unsigned char i,unsigned char c) {
	outp(0x3C4,i);
	outp(0x3C5,c);
}

static inline void vga_write_GC(unsigned char i,unsigned char c) {
	outp(0x3CE,i);
	outp(0x3CF,c);
}

static inline void vga_write_CRTC(unsigned char i,unsigned char c) {
	outp(vga_base_3x0+4,i);
	outp(vga_base_3x0+5,c);
}

static inline void vga_write_color(unsigned char c) {
	vga_color = c;
}

static inline void vga_read_PAL(unsigned char i,unsigned char *p,unsigned int count) {
	count *= 3;
	outp(0x3C7,i);
	while (count-- > 0) *p++ = inp(0x3C9);
}

static inline void vga_write_PAL(unsigned char i,unsigned char *p,unsigned int count) {
	count *= 3;
	outp(0x3C8,i);
	while (count-- > 0) outp(0x3C9,*p++);
}

/* NTS: VGA hardware treats bit 5 of the index as a "screen enable".
 *      When the caller is done reprogramming it is expected to or the index by VGA_AC_ENABLE */
static inline void vga_write_AC(unsigned char i,unsigned char c) {
	inp(vga_base_3x0+0xA); /* reset flipflop */
	outp(0x3C0,i);
	outp(0x3C0,c);
	inp(vga_base_3x0+0xA);
}

static inline unsigned char vga_read_AC(unsigned char i) {
	unsigned char c;

	inp(vga_base_3x0+0xA);
	outp(0x3C0,i|0x20);
	c = inp(0x3C1);
	inp(vga_base_3x0+0xA);<commit_msg>bugfix to follow VGA specification and fix AC palette reading problems on S3 cards.<commit_after>
#include <hw/cpu/cpu.h>
#include <stdint.h>

#if TARGET_MSDOS == 32
typedef unsigned char *VGA_RAM_PTR;
typedef uint16_t *VGA_ALPHA_PTR;
#else
typedef unsigned char far *VGA_RAM_PTR;
typedef uint16_t far *VGA_ALPHA_PTR;
#endif

/* vga_flags */
#define VGA_IS_TANDY			0x02	/* Tandy/PCjr */
#define VGA_IS_HGC			0x04
#define VGA_IS_MCGA			0x08
#define VGA_IS_VGA			0x10
#define VGA_IS_EGA			0x20
#define VGA_IS_CGA			0x40
#define VGA_IS_MDA			0x80
#define VGA_IS_AMSTRAD			0x100

/* sequencer index */
#define VGA_AC_ENABLE			0x20

/* graphics controller regs */
#define VGA_GC_DATA_ROTATE_OP_NONE		(0 << 3)
#define VGA_GC_DATA_ROTATE_OP_AND		(1 << 3)
#define VGA_GC_DATA_ROTATE_OP_OR		(2 << 3)
#define VGA_GC_DATA_ROTATE_OP_XOR		(3 << 3)

/* font manipulation vars */
#define VGA_EGA_BYTES_PER_CHAR_BITMAP		32
#define VGA_EGA_BYTES_PER_CHAR_BITMAP_SHIFT	5

/* EGA/VGA memory map bits */
enum {
	VGA_MEMMAP_A0000_128K=0,
	VGA_MEMMAP_A0000_64K,
	VGA_MEMMAP_B0000_32K,
	VGA_MEMMAP_B8000_32K
};

enum {
	VGA_CGA_MODE_40WIDE=0,
	VGA_CGA_MODE_80WIDE=0x01,
	VGA_CGA_MODE_GRAPHICS=0x02,
	VGA_CGA_MODE_BW=0x04,
	VGA_CGA_MODE_VIDEO_ENABLE=0x08,
	VGA_CGA_MODE_VIDEO_640=0x10,
	VGA_CGA_MODE_NO_BLINKING=0x20
};

/* sequencer registers */
enum {
	VGA_SC_MAP_MASK=2
};

/* graphics controller registers */
enum {
	VGA_GC_ENABLE_SET_RESET=0,
	VGA_GC_SET_RESET=1,
	VGA_GC_DATA_ROTATE=3,
	VGA_GC_MODE=5,
	VGA_GC_BIT_MASK=8
};

enum { /* CGA palette selection (320x200x4) */
	VGA_CGA_PALETTE_GR_BR_RD=0,
	VGA_CGA_PALETTE_CY_MA_WH=1
};

enum { /* color select (text=border color  320x200=background    640x200=foreground */
	VGA_CGA_PALETTE_CS_BLUE=(1U << 0U),
	VGA_CGA_PALETTE_CS_GREEN=(1U << 1U),
	VGA_CGA_PALETTE_CS_RED=(1U << 2U),
	VGA_CGA_PALETTE_CS_INTENSITY=(1U << 3U),
	VGA_CGA_PALETTE_CS_ALT_INTENSITY=(1U << 4U)
};

extern VGA_RAM_PTR	vga_graphics_ram;
extern VGA_RAM_PTR	vga_graphics_ram_fence;
extern VGA_ALPHA_PTR	vga_alpha_ram;
extern VGA_ALPHA_PTR	vga_alpha_ram_fence;

extern uint32_t		vga_clock_rates[4];
extern unsigned char	vga_pos_x,vga_pos_y,vga_color;
extern unsigned char	vga_width,vga_height;
extern unsigned char	vga_alpha_mode;
extern unsigned char	vga_hgc_type;
extern unsigned int	vga_base_3x0;
extern unsigned long	vga_ram_base;
extern unsigned long	vga_ram_size;
extern unsigned char	vga_stride;
extern unsigned short	vga_flags;
extern unsigned char	vga_9wide;

unsigned char int10_getmode();
void vga_write(const char *msg);
void int10_setmode(unsigned char mode);
void update_state_vga_memory_map_select(unsigned char c);
unsigned char vga_force_read(const VGA_RAM_PTR p);
void vga_force_write(VGA_RAM_PTR p,const unsigned char c);
void vga_force_write_w(VGA_ALPHA_PTR p,const unsigned short c);
int check_vga_3C0();
void vga_sync_hw_cursor();
void vga_sync_bios_cursor();
void update_state_vga_memory_map_select(unsigned char c);
void vga_set_memory_map(unsigned char c);
void vga_bios_set_80x50_text();
void update_state_from_vga();
int probe_vga();
void vga_write_state_DEBUG(FILE *f);
void vga_relocate_crtc(unsigned char color);
void vga_switch_to_mono();
void vga_switch_to_color();
void vga_turn_on_hgc();
void vga_turn_off_hgc();
void vga_set_cga_palette_and_background(unsigned char pal,unsigned char color);
void vga_set_cga_mode(unsigned char b);
void vga_tandy_setpalette(unsigned char i,unsigned char c);
void vga_enable_256color_modex();
void vga_set_stride(unsigned int stride);
void vga_set_start_location(unsigned int offset);
void vga_set_ypan_sub(unsigned char c);
void vga_set_xpan(unsigned char c);
void vga_splitscreen(unsigned int v);
void vga_alpha_switch_to_font_plane();
void vga_alpha_switch_from_font_plane();
void vga_set_9wide(unsigned char en);
void vga_select_charset_a_b(unsigned short a,unsigned short b);
void vga_correct_crtc_mode(struct vga_mode_params *p);
void vga_write_crtc_mode(struct vga_mode_params *p);
void vga_read_crtc_mode(struct vga_mode_params *p);

static inline unsigned char vga_read_CRTC(unsigned char i) {
	outp(vga_base_3x0+4,i);
	return inp(vga_base_3x0+5);
}

static inline unsigned char vga_read_GC(unsigned char i) {
	outp(0x3CE,i);
	return inp(0x3CF);
}

static inline unsigned char vga_read_sequencer(unsigned char i) {
	outp(0x3C4,i);
	return inp(0x3C5);
}

static inline void vga_write_sequencer(unsigned char i,unsigned char c) {
	outp(0x3C4,i);
	outp(0x3C5,c);
}

static inline void vga_write_GC(unsigned char i,unsigned char c) {
	outp(0x3CE,i);
	outp(0x3CF,c);
}

static inline void vga_write_CRTC(unsigned char i,unsigned char c) {
	outp(vga_base_3x0+4,i);
	outp(vga_base_3x0+5,c);
}

static inline void vga_write_color(unsigned char c) {
	vga_color = c;
}

static inline void vga_read_PAL(unsigned char i,unsigned char *p,unsigned int count) {
	count *= 3;
	outp(0x3C7,i);
	while (count-- > 0) *p++ = inp(0x3C9);
}

static inline void vga_write_PAL(unsigned char i,unsigned char *p,unsigned int count) {
	count *= 3;
	outp(0x3C8,i);
	while (count-- > 0) outp(0x3C9,*p++);
}

/* NTS: VGA hardware treats bit 5 of the index as a "screen enable".
 *      When the caller is done reprogramming it is expected to or the index by VGA_AC_ENABLE */
static inline void vga_write_AC(unsigned char i,unsigned char c) {
	inp(vga_base_3x0+0xA); /* reset flipflop */
	outp(0x3C0,i);
	outp(0x3C0,c);
	inp(vga_base_3x0+0xA);
}

static inline unsigned char vga_read_AC(unsigned char i) {
	unsigned char c;

	/* NTS: Reading the palette registers must occur this way because
	 *      an old S3 Virge DX card I have will misread the values
	 *      when PAS=1 otherwise. */

	inp(vga_base_3x0+0xA);	/* reset latch */
	outp(0x3C0,i&(~0x20));	/* index with PAS=0 */
	c = inp(0x3C1);
	outp(0x3C0,i|0x20);	/* index with PAS=1 */
	inp(vga_base_3x0+0xA);	/* reset latch */

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