<commit_before>#ifndef SpMVAcceleratorDriver_H
#define SpMVAcceleratorDriver_H
#include <assert.h>
class SpMVAcceleratorDriver {
public:
 SpMVAcceleratorDriver(volatile unsigned int * baseAddr) {
  m_baseAddr = baseAddr; assert(signature() == m_signature);};
 // read+write register: startInit index: 4
 void startInit(unsigned int v) {m_baseAddr[4] = v;};
 unsigned int startInit() {return m_baseAddr[4];};
 // read+write register: startRegular index: 5
 void startRegular(unsigned int v) {m_baseAddr[5] = v;};
 unsigned int startRegular() {return m_baseAddr[5];};
 // read+write register: startWrite index: 6
 void startWrite(unsigned int v) {m_baseAddr[6] = v;};
 unsigned int startWrite() {return m_baseAddr[6];};
 // read+write register: numRows index: 7
 void numRows(unsigned int v) {m_baseAddr[7] = v;};
 unsigned int numRows() {return m_baseAddr[7];};
 // read+write register: numCols index: 8
 void numCols(unsigned int v) {m_baseAddr[8] = v;};
 unsigned int numCols() {return m_baseAddr[8];};
 // read+write register: numNZ index: 9
 void numNZ(unsigned int v) {m_baseAddr[9] = v;};
 unsigned int numNZ() {return m_baseAddr[9];};
 // read+write register: baseColPtr index: 10
 void baseColPtr(unsigned int v) {m_baseAddr[10] = v;};
 unsigned int baseColPtr() {return m_baseAddr[10];};
 // read+write register: baseRowInd index: 11
 void baseRowInd(unsigned int v) {m_baseAddr[11] = v;};
 unsigned int baseRowInd() {return m_baseAddr[11];};
 // read+write register: baseNZData index: 12
 void baseNZData(unsigned int v) {m_baseAddr[12] = v;};
 unsigned int baseNZData() {return m_baseAddr[12];};
 // read+write register: baseInputVec index: 13
 void baseInputVec(unsigned int v) {m_baseAddr[13] = v;};
 unsigned int baseInputVec() {return m_baseAddr[13];};
 // read+write register: baseOutputVec index: 14
 void baseOutputVec(unsigned int v) {m_baseAddr[14] = v;};
 unsigned int baseOutputVec() {return m_baseAddr[14];};
 // read+write register: thresColPtr index: 15
 void thresColPtr(unsigned int v) {m_baseAddr[15] = v;};
 unsigned int thresColPtr() {return m_baseAddr[15];};
 // read+write register: thresRowInd index: 16
 void thresRowInd(unsigned int v) {m_baseAddr[16] = v;};
 unsigned int thresRowInd() {return m_baseAddr[16];};
 // read+write register: thresNZData index: 17
 void thresNZData(unsigned int v) {m_baseAddr[17] = v;};
 unsigned int thresNZData() {return m_baseAddr[17];};
 // read+write register: thresInputVec index: 18
 void thresInputVec(unsigned int v) {m_baseAddr[18] = v;};
 unsigned int thresInputVec() {return m_baseAddr[18];};
 // read+write register: statBackend index: 1
 void statBackend(unsigned int v) {m_baseAddr[1] = v;};
 unsigned int statBackend() {return m_baseAddr[1];};
 // read+write register: statFrontend index: 2
 void statFrontend(unsigned int v) {m_baseAddr[2] = v;};
 unsigned int statFrontend() {return m_baseAddr[2];};
 // read+write register: hazardStalls index: 3
 void hazardStalls(unsigned int v) {m_baseAddr[3] = v;};
 unsigned int hazardStalls() {return m_baseAddr[3];};
 // read+write register: signature index: 0
 void signature(unsigned int v) {m_baseAddr[0] = v;};
 unsigned int signature() {return m_baseAddr[0];};

protected:
 volatile unsigned int * m_baseAddr;
 const static unsigned int m_signature = 0xcbbb437f;
};
#endif
<commit_msg>also update reg driver for bw mon stats<commit_after>#ifndef SpMVAcceleratorDriver_H
#define SpMVAcceleratorDriver_H
#include <assert.h>
class SpMVAcceleratorDriver {
public:
 SpMVAcceleratorDriver(volatile unsigned int * baseAddr) {
  m_baseAddr = baseAddr; assert(signature() == m_signature);};
 // read+write register: startInit index: 6
 void startInit(unsigned int v) {m_baseAddr[6] = v;};
 unsigned int startInit() {return m_baseAddr[6];};
 // read+write register: startRegular index: 7
 void startRegular(unsigned int v) {m_baseAddr[7] = v;};
 unsigned int startRegular() {return m_baseAddr[7];};
 // read+write register: startWrite index: 8
 void startWrite(unsigned int v) {m_baseAddr[8] = v;};
 unsigned int startWrite() {return m_baseAddr[8];};
 // read+write register: numRows index: 9
 void numRows(unsigned int v) {m_baseAddr[9] = v;};
 unsigned int numRows() {return m_baseAddr[9];};
 // read+write register: numCols index: 10
 void numCols(unsigned int v) {m_baseAddr[10] = v;};
 unsigned int numCols() {return m_baseAddr[10];};
 // read+write register: numNZ index: 11
 void numNZ(unsigned int v) {m_baseAddr[11] = v;};
 unsigned int numNZ() {return m_baseAddr[11];};
 // read+write register: baseColPtr index: 12
 void baseColPtr(unsigned int v) {m_baseAddr[12] = v;};
 unsigned int baseColPtr() {return m_baseAddr[12];};
 // read+write register: baseRowInd index: 13
 void baseRowInd(unsigned int v) {m_baseAddr[13] = v;};
 unsigned int baseRowInd() {return m_baseAddr[13];};
 // read+write register: baseNZData index: 14
 void baseNZData(unsigned int v) {m_baseAddr[14] = v;};
 unsigned int baseNZData() {return m_baseAddr[14];};
 // read+write register: baseInputVec index: 15
 void baseInputVec(unsigned int v) {m_baseAddr[15] = v;};
 unsigned int baseInputVec() {return m_baseAddr[15];};
 // read+write register: baseOutputVec index: 16
 void baseOutputVec(unsigned int v) {m_baseAddr[16] = v;};
 unsigned int baseOutputVec() {return m_baseAddr[16];};
 // read+write register: thresColPtr index: 17
 void thresColPtr(unsigned int v) {m_baseAddr[17] = v;};
 unsigned int thresColPtr() {return m_baseAddr[17];};
 // read+write register: thresRowInd index: 18
 void thresRowInd(unsigned int v) {m_baseAddr[18] = v;};
 unsigned int thresRowInd() {return m_baseAddr[18];};
 // read+write register: thresNZData index: 19
 void thresNZData(unsigned int v) {m_baseAddr[19] = v;};
 unsigned int thresNZData() {return m_baseAddr[19];};
 // read+write register: thresInputVec index: 20
 void thresInputVec(unsigned int v) {m_baseAddr[20] = v;};
 unsigned int thresInputVec() {return m_baseAddr[20];};
 // read+write register: statBackend index: 1
 void statBackend(unsigned int v) {m_baseAddr[1] = v;};
 unsigned int statBackend() {return m_baseAddr[1];};
 // read+write register: statFrontend index: 2
 void statFrontend(unsigned int v) {m_baseAddr[2] = v;};
 unsigned int statFrontend() {return m_baseAddr[2];};
 // read+write register: hazardStalls index: 3
 void hazardStalls(unsigned int v) {m_baseAddr[3] = v;};
 unsigned int hazardStalls() {return m_baseAddr[3];};
 // read+write register: bwMon_totalCycles index: 4
 void bwMon_totalCycles(unsigned int v) {m_baseAddr[4] = v;};
 unsigned int bwMon_totalCycles() {return m_baseAddr[4];};
 // read+write register: bwMon_activeCycles index: 5
 void bwMon_activeCycles(unsigned int v) {m_baseAddr[5] = v;};
 unsigned int bwMon_activeCycles() {return m_baseAddr[5];};
 // read+write register: signature index: 0
 void signature(unsigned int v) {m_baseAddr[0] = v;};
 unsigned int signature() {return m_baseAddr[0];};

protected:
 volatile unsigned int * m_baseAddr;
 const static unsigned int m_signature = 0x52b212c5;
};
#endif

{'fraction_non_alphanumeric': 0.135293278150421, 'fraction_numerical': 0.0272584558298844, 'mean_word_length': 5.897637795275591, 'pattern_counts': {'":': 0, '<': 5, '<?xml version=': 0, '>': 5, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2868384', 'n_tokens_mistral': 2485, 'n_tokens_neox': 2355, 'n_words': 705}