<commit_before>; example name[@variant]            options..................................
minimal@test                        arch=dpdk hugepages=64   model=v1model smem x_emit 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt

v1model-simplest                    arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
vss-example                         arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
bit48-field-in-action               arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd

smgw                                arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=smgw
vsmgw-no-typedef                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=smgw
;vsmgw-no-typedef@test              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=smgw     ctrcfg=examples/smgw_table2.txt
vsmgw-no-typedef@test2              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=smgw     ctrcfg=examples/smgw_table2.txt

portfwd                             arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd
l2fwd                               arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt
l2fwd@test                          arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
l2fwd-gen                           arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt
l2fwd-gen@test                      arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
l3fwd-with-chksm                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-with-chksm@test               arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm                      arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm@test                 arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm-gen                  arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm-gen@test             arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3-routing-full                     arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt

l2-switch-test@pipeline             arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd
portfwd@pipeline                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd
l3fwd@pipeline                      arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd
bng                                 arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd

test-setValid-1@test                arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-setValid-2@test                arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-setInvalid-1@test              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-isValid-1@test                 arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal

test-assign-header-instance@test    arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal

test-checksum@test                  arch=dpdk hugepages=256  model=v1model smem 2cores 0ports   noeal
test-smem@test                      arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
vsmgw-no-typedef@test               arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=vsmgw
vsmgw@test                          arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=vsmgw

nop@test                            arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt

psa-l2fwd@test                      arch=dpdk hugepages=64   model=psa     smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt<commit_msg>Add configurations for new test cases<commit_after>; example name[@variant]            options..................................
minimal@test                        arch=dpdk hugepages=64   model=v1model smem x_emit 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt

v1model-simplest                    arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
vss-example                         arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
bit48-field-in-action               arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd

smgw                                arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=smgw
vsmgw-no-typedef                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=smgw
;vsmgw-no-typedef@test              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=smgw     ctrcfg=examples/smgw_table2.txt
vsmgw-no-typedef@test2              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=smgw     ctrcfg=examples/smgw_table2.txt

portfwd                             arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd
l2fwd                               arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt
l2fwd@test                          arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
vEPG@test                           arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
l2fwd-gen                           arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt
l2fwd-gen@test                      arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
l3fwd-with-chksm                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-with-chksm@test               arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm                      arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm@test                 arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm-gen                  arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3fwd-wo-chksm-gen@test             arch=dpdk hugepages=2048 model=v1model smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
l3-routing-full                     arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt

l2-switch-test@pipeline             arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l2fwd
portfwd@pipeline                    arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd
l3fwd@pipeline                      arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=l3fwd
bng                                 arch=dpdk hugepages=2048 model=v1model smem 2cores 2x2ports       ctr=portfwd

test-setValid-1@test                arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-setValid-2@test                arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-setInvalid-1@test              arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal
test-isValid-1@test                 arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal

test-assign-header-instance@test    arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal

test-checksum@test                  arch=dpdk hugepages=256  model=v1model smem 2cores 0ports   noeal
test-smem@test                      arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd
vsmgw-no-typedef@test               arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=vsmgw
vsmgw@test                          arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=vsmgw

nop@test                            arch=dpdk hugepages=64   model=v1model smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_table.txt

psa-l2fwd@test                      arch=dpdk hugepages=64   model=psa     smem 2cores 0ports   noeal ctr=l2fwd    ctrcfg=examples/l2fwd_test_table.txt
psa-l3fwd-with-chksm@test           arch=dpdk hugepages=2048 model=psa     smem 2cores 0ports   noeal ctr=l3fwd    ctrcfg=examples/l3fwd_table.txt
{'fraction_non_alphanumeric': 0.06401439001163899, 'fraction_numerical': 0.06052269601100413, 'mean_word_length': 2.4233973198116625, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 2, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1008536', 'n_tokens_mistral': 3810, 'n_tokens_neox': 3404, 'n_words': 658}