<commit_before>; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2,fma | FileCheck %s

define float @fneg_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: fneg_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; CHECK-NEXT:    vxorps %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fneg <4 x float> %x
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fneg_v4f64(<4 x double> %x) nounwind {
; CHECK-LABEL: fneg_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vbroadcastsd {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; CHECK-NEXT:    vxorps %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fneg <4 x double> %x
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fadd_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fadd_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vaddss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fadd <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fadd_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fadd_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fadd <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fsub_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fsub_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsubss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fsub <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fsub_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fsub_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fsub <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fmul_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fmul_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fmul <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fmul_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fmul_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fmul <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fdiv_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fdiv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vdivss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fdiv <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fdiv_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fdiv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fdiv <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @frem_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: frem_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    jmp fmodf # TAILCALL
  %v = frem <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @frem_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: frem_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    # kill: def $xmm1 killed $xmm1 killed $ymm1
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    jmp fmod # TAILCALL
  %v = frem <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define i1 @fcmp_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fcmp_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vucomiss %xmm1, %xmm0
; CHECK-NEXT:    seta %al
; CHECK-NEXT:    retq
  %v = fcmp ogt <4 x float> %x, %y
  %r = extractelement <4 x i1> %v, i32 0
  ret i1 %r
}

define i1 @fcmp_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fcmp_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vucomisd %xmm0, %xmm1
; CHECK-NEXT:    setb %al
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fcmp ugt <4 x double> %x, %y
  %r = extractelement <4 x i1> %v, i32 0
  ret i1 %r
}

define float @fsqrt_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: fsqrt_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fsqrt_v4f64(<4 x double> %x) nounwind {
; CHECK-LABEL: fsqrt_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq<commit_msg>[x86] add tests for extract of FP select; NFC<commit_after>; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2,fma | FileCheck %s

define float @fneg_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: fneg_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; CHECK-NEXT:    vxorps %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fneg <4 x float> %x
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fneg_v4f64(<4 x double> %x) nounwind {
; CHECK-LABEL: fneg_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vbroadcastsd {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; CHECK-NEXT:    vxorps %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fneg <4 x double> %x
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fadd_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fadd_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vaddss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fadd <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fadd_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fadd_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fadd <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fsub_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fsub_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsubss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fsub <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fsub_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fsub_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsubsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fsub <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fmul_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fmul_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fmul <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fmul_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fmul_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fmul <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @fdiv_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fdiv_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vdivss %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = fdiv <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fdiv_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fdiv_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fdiv <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define float @frem_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: frem_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    jmp fmodf # TAILCALL
  %v = frem <4 x float> %x, %y
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @frem_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: frem_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    # kill: def $xmm1 killed $xmm1 killed $ymm1
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    jmp fmod # TAILCALL
  %v = frem <4 x double> %x, %y
  %r = extractelement <4 x double> %v, i32 0
  ret double %r
}

define i1 @fcmp_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
; CHECK-LABEL: fcmp_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vucomiss %xmm1, %xmm0
; CHECK-NEXT:    seta %al
; CHECK-NEXT:    retq
  %v = fcmp ogt <4 x float> %x, %y
  %r = extractelement <4 x i1> %v, i32 0
  ret i1 %r
}

define i1 @fcmp_v4f64(<4 x double> %x, <4 x double> %y) nounwind {
; CHECK-LABEL: fcmp_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vucomisd %xmm0, %xmm1
; CHECK-NEXT:    setb %al
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %v = fcmp ugt <4 x double> %x, %y
  %r = extractelement <4 x i1> %v, i32 0
  ret i1 %r
}

define float @select_fcmp_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) nounwind {
; CHECK-LABEL: select_fcmp_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcmpneq_oqps %xmm1, %xmm0, %xmm0
; CHECK-NEXT:    vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; CHECK-NEXT:    retq
  %c = fcmp one <4 x float> %x, %y
  %s = select <4 x i1> %c, <4 x float> %z, <4 x float> %w
  %r = extractelement <4 x float> %s, i32 0
  ret float %r
}

define double @select_fcmp_v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %z, <4 x double> %w) nounwind {
; CHECK-LABEL: select_fcmp_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcmpnltpd %ymm0, %ymm1, %ymm0
; CHECK-NEXT:    vblendvpd %ymm0, %ymm2, %ymm3, %ymm0
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %c = fcmp ule <4 x double> %x, %y
  %s = select <4 x i1> %c, <4 x double> %z, <4 x double> %w
  %r = extractelement <4 x double> %s, i32 0
  ret double %r
}

define float @fsqrt_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: fsqrt_v4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    retq
  %v = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
  %r = extractelement <4 x float> %v, i32 0
  ret float %r
}

define double @fsqrt_v4f64(<4 x double> %x) nounwind {
; CHECK-LABEL: fsqrt_v4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsqrtsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
{'fraction_non_alphanumeric': 0.16588107324147933, 'fraction_numerical': 0.060097897026831035, 'mean_word_length': 2.9859104046242773, 'pattern_counts': {'":': 0, '<': 141, '<?xml version=': 0, '>': 139, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7233470', 'n_tokens_mistral': 5373, 'n_tokens_neox': 5081, 'n_words': 1477}