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# RISC-V 双周简报 (2018-05-25)

要点新闻：


## RV新闻


## 技术讨论

### 为什么RISC-V定义的PPN和VPN位数不一致

在RISC-V的特权指令级定义中，一个内存页的大小为4KB，地址偏移量为12比特，但是在RV32系统中，一个页表项（VPN和PPN）却只有10比特。这是因为一个PTE（page table entry）的大小为32比特，其地址是4B对齐的，没有必要记录最低的2比特PTE地址。 
同时，VPN[1]为10比特，但是PPN[1]却为12比特。这是为了在32位系统中支持最高64GB（34比特物理地址）的内存。
一个虚拟地址空间的最大大小为4GB，但是通过将10位的VPN[1]映射到12位的PPN[1]就可以实现多个虚拟地址空间合用64GB实际内存。

Link: sw-dev上的讨论： [链接](https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/B1cpWatkhVw/ktLfyYYJAQAJ)

### 自由的RISC-V (Libre RISC-V)？

<NAME> 和 <NAME> 想成立一个 Libre RISC-V 的组织来维护自由的RISC-V，以保证RISC-V的logo只被用于开放系统。

> **<NAME>**： Also, some organization needs to be the "face" of the approach and protect the "open general-purpose RISC-V" logo to ensure that it is only used on systems that actually meet the purpose.  I was hoping that the Libre RISC-V group might be interested in the idea, if the RISC-V Foundation does not itself take that role.

然而，这个假设和RISC-V的初衷是违背的。 RISC-V是RISC-V基金会的商标。只要符合RISC-V标准，即使不是会员的非商业使用也可以自由使用该商标。

> **Krste**: RISC-V is a trademark of the Foundation.  Non-commercial use is
granted to non-members for systems that follow the RISC-V standards.

最初加州伯克利的RISC指令集现在已经算进入公有领域，可以被免费使用。但是使用这些指令集的系统不能直接被称作为RISC-V系统，除非该系统符合RISC-V标准。
如果Libre RISC-V不符合上面的原则，就不应该是被称为RISC-V。

> The RISC ISA that was originally designed at Berkeley is effectively
public domain, and derivatives can be developed and used freely.  But
they cannot be called RISC-V, or use RISC-V in their name, except if
they follow Foundation guidelines.  If "Libre RISC-V" is not following
the guidelines, then the project should change it's name.

关于RISC-V名字的使用规则，是为了防止歧义、社区分散和商标劫持。

> The policy around the name was set up to avoid confusion,
> fragmentation, and/or hijacking.

我(Krste)正式地说，RISC-V基金会致力于推广最广泛的软件多样性，并不限制RISC-V的使用。

> For the record, the Foundation is interested in having the largest
> possible variety of software run on RISC-V, and not in restricting
> uses of RISC-V.

一个目的是使能彻底免费和开放的硬件设计，不隐藏任何软件和固件。另一个目的则是使能彻底封闭的硬件设计。
这两个目的并不矛盾。这两个用途对在不同场景下维护安全和自由都至关重要。

> One goal is to enable completely free and open hardware designs, with
> no hidden software or firmware. Another is to enable completely locked-down hardware designs.
> These goals are not contradictory.  Both are valuable for preserving
> freedoms and security in different scenarios.

- isa-dev上的讨论： [链接](https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/WzJjmIEXvVk/dhhZ--OACgAJ)

## 代码更新

## 安全点评<commit_msg>firmsim opensource.<commit_after>---
layout: default
---

# RISC-V 双周简报 (2018-05-25)

要点新闻：


## RV新闻


## 技术讨论

### 为什么RISC-V定义的PPN和VPN位数不一致

在RISC-V的特权指令级定义中，一个内存页的大小为4KB，地址偏移量为12比特，但是在RV32系统中，一个页表项（VPN和PPN）却只有10比特。这是因为一个PTE（page table entry）的大小为32比特，其地址是4B对齐的，没有必要记录最低的2比特PTE地址。 
同时，VPN[1]为10比特，但是PPN[1]却为12比特。这是为了在32位系统中支持最高64GB（34比特物理地址）的内存。
一个虚拟地址空间的最大大小为4GB，但是通过将10位的VPN[1]映射到12位的PPN[1]就可以实现多个虚拟地址空间合用64GB实际内存。

Link: sw-dev上的讨论： [链接](https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/B1cpWatkhVw/ktLfyYYJAQAJ)

### 自由的RISC-V (Libre RISC-V)？

<NAME> 和 <NAME> 想成立一个 Libre RISC-V 的组织来维护自由的RISC-V，以保证RISC-V的logo只被用于开放系统。

> **<NAME>**： Also, some organization needs to be the "face" of the approach and protect the "open general-purpose RISC-V" logo to ensure that it is only used on systems that actually meet the purpose.  I was hoping that the Libre RISC-V group might be interested in the idea, if the RISC-V Foundation does not itself take that role.

然而，这个假设和RISC-V的初衷是违背的。 RISC-V是RISC-V基金会的商标。只要符合RISC-V标准，即使不是会员的非商业使用也可以自由使用该商标。

> **Krste**: RISC-V is a trademark of the Foundation.  Non-commercial use is
granted to non-members for systems that follow the RISC-V standards.

最初加州伯克利的RISC指令集现在已经算进入公有领域，可以被免费使用。但是使用这些指令集的系统不能直接被称作为RISC-V系统，除非该系统符合RISC-V标准。
如果Libre RISC-V不符合上面的原则，就不应该是被称为RISC-V。

> The RISC ISA that was originally designed at Berkeley is effectively
public domain, and derivatives can be developed and used freely.  But
they cannot be called RISC-V, or use RISC-V in their name, except if
they follow Foundation guidelines.  If "Libre RISC-V" is not following
the guidelines, then the project should change it's name.

关于RISC-V名字的使用规则，是为了防止歧义、社区分散和商标劫持。

> The policy around the name was set up to avoid confusion,
> fragmentation, and/or hijacking.

我(Krste)正式地说，RISC-V基金会致力于推广最广泛的软件多样性，并不限制RISC-V的使用。

> For the record, the Foundation is interested in having the largest
> possible variety of software run on RISC-V, and not in restricting
> uses of RISC-V.

一个目的是使能彻底免费和开放的硬件设计，不隐藏任何软件和固件。另一个目的则是使能彻底封闭的硬件设计。
这两个目的并不矛盾。这两个用途对在不同场景下维护安全和自由都至关重要。

> One goal is to enable completely free and open hardware designs, with
> no hidden software or firmware. Another is to enable completely locked-down hardware designs.
> These goals are not contradictory.  Both are valuable for preserving
> freedoms and security in different scenarios.

- isa-dev上的讨论： [链接](https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/WzJjmIEXvVk/dhhZ--OACgAJ)

## 代码更新

### FireSim宣布开源

FireSim能够在亚马逊F1云上通过FPGA来加速周期精确的基于rocket-chip的始终速率从十几MHz到数百MHz级别的仿真。（150MHz下的4核仿真，或者大约10MHz下的1024或4096个节点的使用数据中心的网络通信和接近16TB内存进行的仿真）

Github repo: [https://github.com/firesim/firesim](https://github.com/firesim/firesim)
Docs: [https://docs.fires.im](https://docs.fires.im)

在这一版的Release中其支持两个Case:

1. 单节点并行仿真（不需要仿真网络）：跑一遍SPECInt 2017大约需要一天的时间，也可以boot Fedora。
2. 数据中心/集群上的仿真：通过以太网连接的、指令周期精确的超多核心的仿真。
  - ISCA 2018 论文 [http://t.cn/R129Xzz](https://sagark.org/assets/pubs/firesim-isca2018.pdf)
  - ISCA 2018 lightning talk: [http://y2u.be/4XwoSe5c8lY](https://www.youtube.com/watch?v=4XwoSe5c8lY)
  - 项目中的脚步和文档可以在云上验证。 [http://t.cn/R129HQw](https://docs.fires.im/en/latest/Advanced-Usage/Workloads/ISCA-2018-Experiments.html)

有人问和gem5的关系:

> The end goal is similar to gem5 - ultimately we want to collect performance results for some hardware design - but the approaches are different. 
> 
> In FireSim, the simulator is automatically derived from the RTL that describes a hardware design, in this case Rocket Chip (although the methodology is not specific to Rocket Chip). So the simulator "implements" the RISC-V ISA as an artifact of the fact that it is modeling Rocket Cores (that implement RISC-V) on the FPGA. Similarly, we can plug-in "BOOM Chips" and model those without extra effort, since the simulation is derived from the RTL (this is a WIP, should show up on a branch soon).
> 
> With our automation, we're aiming to achieve the ease-of-use of gem5, but with the performance of FPGA-accelerated simulation, all while being derived from real hardware implementations rather than handwritten abstract-models.

点评：群头必须告诉你的是，未来半导体公司必须开始重视云计算能给我们的生产力所带来的改进，从AWS F1到国内云计算厂商都开始部署FPGA云，尽管这些云99%都不是用来做IC仿真加速或者验证的，但是正式因为有了其他99%的应用，才能有效的拉低云上FPGA的价格，从而有效的降低研发成本和提高生产力，我认为这也是Agile Hardware Developtment中重要的一个环节。

Link: [Google Group讨论](https://groups.google.com/a/groups.riscv.org/forum/?utm_medium=email&utm_source=footer#!msg/hw-dev/6rK_aTjyijI/jPaz99PgAAAJ)

## 安全点评
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