<commit_before><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="nv50_defs.xml" />

<bitset name="nv98_fuc_intr" inline="yes">
	<bitfield pos="0" name="PERIODIC"/>
	<bitfield pos="1" name="WATCHDOG"/>
	<bitfield pos="2" name="FIFO_DATA"/>
	<bitfield pos="3" name="CHANNEL_SWITCH"/>
	<bitfield pos="4" name="EXIT"/>
	<bitfield pos="6" name="USER1"/> <!-- there are more... -->
	<bitfield pos="9" name="XFER_FAULT"/>
</bitset>

<bitset name="NV98_FUC_BREAK_MASK">
	<bitfield pos="7" name="BREAKPOINT"/>
</bitset>

<group name="nv98_fucbase">
	<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x004" name="INTR_ACK" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x008" name="INTR" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x010" name="INTR_EN_SET" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x014" name="INTR_EN_CLR" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x018" name="INTR_EN" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x01c" name="INTR_ROUTING">
		<doc>
			Each interrupt has 2 bits in here, and its handling
			is determined by their combination:
			<ul>
			<li>M1 = 0, M2 = 0: fuc interrupt 0</li>
			<li>M1 = 0, M2 = 1: fuc interrupt 1</li>
			<li>M1 = 1, M2 = 0: PMC HOST/DAEMON interrupt</li>
			<li>M1 = 1, M2 = 1: PMC UNK1 interrupt [NVC0+ only]</li>
			</ul>
		</doc>
		<bitfield low="0" high="15" name="M1" type="nv98_fuc_intr"/>
		<bitfield low="16" high="31" name="M2" type="nv98_fuc_intr"/>
	</reg32>
	<!-- the following are conspiciously absent from PGRAPH. -->
	<reg32 offset="0x020" name="PERIODIC_PERIOD"/>
	<reg32 offset="0x024" name="PERIODIC_TIME"/>
	<reg32 offset="0x028" name="PERIODIC_ENABLE"/>
	<reg32 offset="0x02c" name="TIME_LOW"/>
	<reg32 offset="0x030" name="TIME_HIGH"/>
	<reg32 offset="0x034" name="WATCHDOG_TIME"/>
	<reg32 offset="0x038" name="WATCHDOG_ENABLE"/>

	<reg32 offset="0x040" name="SCRATCH" length="2"/>

	<reg32 offset="0x048" name="ACCESS_EN">
		<bitfield pos="0" name="CHANNEL_SWITCH"/>
		<bitfield pos="1" name="FIFO"/>
	</reg32>
	<!-- 4c also related to FIFO/switching -->

	<!-- the following two are also conspiciously absent from PGRAPH. -->
	<reg32 offset="0x050" name="CHANNEL_CUR">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x054" name="CHANNEL_NEXT">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x058" name="CHANNEL_TRIGGER">
		<bitfield pos="0" name="UNLOAD"/>
		<bitfield pos="1" name="LOAD"/>
	</reg32>

	<reg32 offset="0x064" name="FIFO_DATA"/>
	<reg32 offset="0x068" name="FIFO_CMD">
		<bitfield low="0" high="10" name="MTHD" shr="2"/>
		<bitfield low="11" high="13" name="SUBC"/> <!-- guess... -->
		<bitfield pos="14" name="NONINCR"/> <!-- even bigger guess... -->
	</reg32>
	<reg32 offset="0x070" name="FIFO_OCCUPIED"/>
	<reg32 offset="0x074" name="FIFO_ACK">
		<doc>Write 1 to go to next command.</doc>
	</reg32>
	<reg32 offset="0x078" name="FIFO_LIMIT">
		<doc>Up to 0x10</doc>
	</reg32>
	<reg32 offset="0x07c" name="SUBENGINE_RESET"/>

	<reg32 offset="0x088" name="PM_SIGNAL">
		<bitfield pos="0" name="0"/>
		<bitfield pos="1" name="1"/>
		<bitfield pos="2" name="2"/>
		<bitfield pos="3" name="3"/>
		<bitfield pos="4" name="4"/>
		<bitfield pos="5" name="5"/>
		<bitfield pos="16" name="WRCACHE_FLUSH"/>
		<bitfield pos="17" name="PM_TRIGGER"/>
	</reg32>
	<enum name="nv98_fuc_pm_mode" inline="yes">
		<value value="0" name="PULSE"/>
		<value value="1" name="CONTINUOUS"/>
	</enum>
	<reg32 offset="0x08c" name="PM_MODE">
		<bitfield pos="0" name="0" type="nv98_fuc_pm_mode"/>
		<bitfield pos="1" name="1" type="nv98_fuc_pm_mode"/>
		<bitfield pos="2" name="2" type="nv98_fuc_pm_mode"/>
		<bitfield pos="3" name="3" type="nv98_fuc_pm_mode"/>
		<bitfield pos="4" name="4" type="nv98_fuc_pm_mode"/>
		<bitfield pos="5" name="5" type="nv98_fuc_pm_mode"/>
	</reg32>

	<reg32 offset="0x098" name="BREAKPOINT" length="2" variants="NVA3-">
		<bitfield low="0" high="23" name="PC"/>
		<bitfield pos="30" name="SKIP_ONE"/>
		<bitfield pos="31" name="ENABLED"/>
	</reg32>

	<reg32 offset="0x0a8" name="PM_SEL_V4" variants="NVD9-"> <!-- v4+ only -->
		<!-- XXX: bitfields probably wrong for v4 -->
		<bitfield low="0" high="3" name="0"/> <!-- from ??? -->
		<bitfield low="4" high="7" name="1"/> <!-- from ??? -->
		<bitfield low="8" high="11" name="2"/> <!-- from USER signals -->
		<bitfield low="12" high="15" name="3"/> <!-- from USER signals -->
		<bitfield low="17" high="31" name="UNK17"/>
	</reg32>

	<reg32 offset="0x0ac" name="HOST_IO_INDEX_V4" variants="NVD9-"/> <!-- XXX: wtf are the high 6 bits for? -->

	<reg32 offset="0x100" name="UC_CTRL">
		<bitfield pos="1" name="START_TRIGGER"/>
		<bitfield pos="2" name="RESET_UNK2_TRIGGER"/>
		<bitfield pos="3" name="RESET_UNK3_TRIGGER"/>
		<bitfield pos="4" name="STOPPED"/>
		<bitfield pos="5" name="SLEEPING"/>
	</reg32>
<commit_msg>fµc: Nailed down PAUSE stuff.<commit_after><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="nv50_defs.xml" />

<bitset name="nv98_fuc_intr" inline="yes">
	<bitfield pos="0" name="PERIODIC"/>
	<bitfield pos="1" name="WATCHDOG"/>
	<bitfield pos="2" name="FIFO_DATA"/>
	<bitfield pos="3" name="CHANNEL_SWITCH"/>
	<bitfield pos="4" name="EXIT"/>
	<bitfield pos="5" name="PAUSE"/>
	<bitfield pos="6" name="USER1"/>
	<bitfield pos="7" name="USER2"/>
</bitset>

<bitset name="NV98_FUC_BREAK_MASK">
	<bitfield pos="7" name="BREAKPOINT"/>
</bitset>

<group name="nv98_fucbase">
	<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x004" name="INTR_ACK" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x008" name="INTR" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x010" name="INTR_EN_SET" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x014" name="INTR_EN_CLR" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x018" name="INTR_EN" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x01c" name="INTR_ROUTING">
		<doc>
			Each interrupt has 2 bits in here, and its handling
			is determined by their combination:
			<ul>
			<li>M1 = 0, M2 = 0: fuc interrupt 0</li>
			<li>M1 = 0, M2 = 1: fuc interrupt 1</li>
			<li>M1 = 1, M2 = 0: PMC HOST/DAEMON interrupt</li>
			<li>M1 = 1, M2 = 1: PMC UNK1 interrupt [NVC0+ only]</li>
			</ul>
		</doc>
		<bitfield low="0" high="15" name="M1" type="nv98_fuc_intr"/>
		<bitfield low="16" high="31" name="M2" type="nv98_fuc_intr"/>
	</reg32>
	<!-- the following are conspiciously absent from PGRAPH. -->
	<reg32 offset="0x020" name="PERIODIC_PERIOD"/>
	<reg32 offset="0x024" name="PERIODIC_TIME"/>
	<reg32 offset="0x028" name="PERIODIC_ENABLE"/>
	<reg32 offset="0x02c" name="TIME_LOW"/>
	<reg32 offset="0x030" name="TIME_HIGH"/>
	<reg32 offset="0x034" name="WATCHDOG_TIME"/>
	<reg32 offset="0x038" name="WATCHDOG_ENABLE"/>

	<reg32 offset="0x040" name="SCRATCH0"/>
	<reg32 offset="0x044" name="SCRATCH1"/>
	<reg32 offset="0x048" name="ACCESS_EN">
		<bitfield pos="0" name="CHANNEL_SWITCH"/>
		<bitfield pos="1" name="FIFO"/>
	</reg32>
	<reg32 offset="0x04c" name="STATUS_BUSY"/> <!-- bits depend on engine -->

	<!-- the following two are also conspiciously absent from PGRAPH. -->
	<reg32 offset="0x050" name="CHANNEL_CUR">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x054" name="CHANNEL_NEXT">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x058" name="CHANNEL_TRIGGER">
		<bitfield pos="0" name="UNLOAD"/>
		<bitfield pos="1" name="LOAD"/>
	</reg32>
	<reg32 offset="0x05c" name="STATUS_PAUSE">
		<bitfield low="0" high="15" name="PAUSED_MASK"/>
		<bitfield pos="16" name="FAULTED"/>
		<bitfield pos="17" name="PAUSED"/>
	</reg32>

	<reg32 offset="0x064" name="FIFO_DATA"/>
	<reg32 offset="0x068" name="FIFO_CMD">
		<bitfield low="0" high="10" name="MTHD" shr="2"/>
		<bitfield low="11" high="13" name="SUBC"/> <!-- guess... -->
		<bitfield pos="14" name="NONINCR"/> <!-- even bigger guess... -->
	</reg32>
	<reg32 offset="0x070" name="FIFO_OCCUPIED"/>
	<reg32 offset="0x074" name="FIFO_ACK">
		<doc>Write 1 to go to next command.</doc>
	</reg32>
	<reg32 offset="0x078" name="FIFO_LIMIT">
		<doc>Up to 0x10</doc>
	</reg32>
	<reg32 offset="0x07c" name="SUBENGINE_RESET"/>
	<reg32 offset="0x080" name="SCRATCH2"/>
	<reg32 offset="0x084" name="SCRATCH3"/>
	<reg32 offset="0x088" name="PM_SIGNAL">
		<bitfield pos="0" name="0"/>
		<bitfield pos="1" name="1"/>
		<bitfield pos="2" name="2"/>
		<bitfield pos="3" name="3"/>
		<bitfield pos="4" name="4"/>
		<bitfield pos="5" name="5"/>
		<bitfield pos="16" name="WRCACHE_FLUSH"/>
		<bitfield pos="17" name="PM_TRIGGER"/>
	</reg32>
	<enum name="nv98_fuc_pm_mode" inline="yes">
		<value value="0" name="PULSE"/>
		<value value="1" name="CONTINUOUS"/>
	</enum>
	<reg32 offset="0x08c" name="PM_MODE">
		<bitfield pos="0" name="0" type="nv98_fuc_pm_mode"/>
		<bitfield pos="1" name="1" type="nv98_fuc_pm_mode"/>
		<bitfield pos="2" name="2" type="nv98_fuc_pm_mode"/>
		<bitfield pos="3" name="3" type="nv98_fuc_pm_mode"/>
		<bitfield pos="4" name="4" type="nv98_fuc_pm_mode"/>
		<bitfield pos="5" name="5" type="nv98_fuc_pm_mode"/>
	</reg32>
	<reg32 offset="0x090" name="UNK090">
		<bitfield low="0" high="15" name="UNK0"/>
		<bitfield pos="16" name="UNK16" variants="NVA3-"/>
	</reg32>
	<reg32 offset="0x094" name="UNK094" variants="NVA3-"/>
	<reg32 offset="0x098" name="BREAKPOINT" length="2" variants="NVA3-">
		<bitfield low="0" high="23" name="PC"/>
		<bitfield pos="30" name="SKIP_ONE"/>
		<bitfield pos="31" name="ENABLED"/>
	</reg32>
	<reg32 offset="0x0a0" name="UNK0A0" variants="NVA3-" type="boolean"/>
	<reg32 offset="0x0a4" name="PAUSE_CONTROL" variants="NVA3-">
		<bitfield pos="0" name="UNK0"/>
		<bitfield pos="1" name="PAUSE_TRIGGER"/>
		<bitfield pos="2" name="UNPAUSE_TRIGGER"/>
		<bitfield pos="8" name="PAUSE_REQ"/>
		<bitfield pos="9" name="PAUSE_DONE"/>
	</reg32>
	<reg32 offset="0x0a8" name="PM_SEL_V4" variants="NVD9-"> <!-- v4+ only -->
		<!-- XXX: bitfields probably wrong for v4 -->
		<bitfield low="0" high="3" name="0"/> <!-- from ??? -->
		<bitfield low="4" high="7" name="1"/> <!-- from ??? -->
		<bitfield low="8" high="11" name="2"/> <!-- from USER signals -->
		<bitfield low="12" high="15" name="3"/> <!-- from USER signals -->
		<bitfield low="17" high="31" name="UNK17"/>
	</reg32>
	<reg32 offset="0x0ac" name="HOST_IO_INDEX_V4" variants="NVD9-"/> <!-- XXX: wtf are the high 6 bits for? -->

	<reg32 offset="0x100" name="UC_CTRL">
		<bitfield pos="1" name="START_TRIGGER"/>
		<bitfield pos="2" name="RESET_UNK2_TRIGGER"/>
		<bitfield pos="3" name="RESET_UNK3_TRIGGER"/>
		<bitfield pos="4" name="STOPPED"/>
		<bitfield pos="5" name="SLEEPING"/>
	</reg32>

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