<commit_before>..  _welcome:

Welcome to SyDPy
==================================

SyDPy project started in an attempt to customize the MyHDL Python package to my needs as FPGA designer. After realization that I have already done too much tweaking, I decided to write my own package from ground-up, but kept some of the MyHDL syntax for hardware description. The following are major differences to MyHDL:

- SyDPy enables TLM (Transaction Level Modelling)
- Signals are abstracted into channels. Information in the same channels can be accessed by different processes using different protocols (on various levels of abstraction) without the need of user conversion modules.
- Introduced global simulator configuration where user module parameters can be set using qualified names. Wildcards also supported.
- Modules can have multiple architectures, they can be checked one against another easily.
- Simulator kernel is extendible by registering callbacks to simulator events.
- Basic randomization, sequencing and scoreboarding supported.

Tutorial
================

Start with the short tutorial: :ref:'tutorial'

.. toctree::
   :maxdepth: 2

   roadmap<commit_msg>- Trying to fix page references<commit_after>..  _welcome:

Welcome to SyDPy
==================================

SyDPy project started in an attempt to customize the MyHDL Python package to my needs as FPGA designer. After realization that I have already done too much tweaking, I decided to write my own package from ground-up, but kept some of the MyHDL syntax for hardware description. The following are major differences to MyHDL:

- SyDPy enables TLM (Transaction Level Modelling)
- Signals are abstracted into channels. Information in the same channels can be accessed by different processes using different protocols (on various levels of abstraction) without the need of user conversion modules.
- Introduced global simulator configuration where user module parameters can be set using qualified names. Wildcards also supported.
- Modules can have multiple architectures, they can be checked one against another easily.
- Simulator kernel is extendible by registering callbacks to simulator events.
- Basic randomization, sequencing and scoreboarding supported.

Tutorial
================

Start with the short tutorial :ref:`tutorial`

.. toctree::
   :maxdepth: 2

   roadmap
{'fraction_non_alphanumeric': 0.07819804504887377, 'fraction_numerical': 0.0008499787505312367, 'mean_word_length': 4.9294710327455915, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6571331', 'n_tokens_mistral': 558, 'n_tokens_neox': 509, 'n_words': 310}