<commit_before>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hdl_toolkit.bitmask import mask
from hdl_toolkit.interfaces.std import Signal, HandshakeSync, VectSignal
from hdl_toolkit.interfaces.utils import log2ceil, propagateClkRstn
from hdl_toolkit.synthesizer.codeOps import If, Switch, connect
from hdl_toolkit.synthesizer.param import Param
from hwtLib.axi.axi_datapump_base import Axi_datapumpBase
from hwtLib.handshaked.fifo import HandshakedFifo
from hwtLib.interfaces.amba import (Axi4_r, AxiStream_withId)
from hwtLib.interfaces.amba_constants import RESP_OKAY
from hwtLib.handshaked.streamNode import streamSync


class TransEndInfo(HandshakeSync):
    def _config(self):
        self.DATA_WIDTH = Param(64)
    
    def _declr(self):
        # rem is number of bits in last word which is valid - 1
        self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8))

        self.propagateLast = Signal()
        HandshakeSync._declr(self)

class Axi_rDatapump(Axi_datapumpBase):
    """
    Foward req to axi ar channel 
    and collect data to data channel form axi r channel 
    
    This unit simplifies axi interface,
    blocks data channel when there is no request pending
    and contains frame merging logic if is required
    
    if req len is wider transaction is internally splited to multiple
    transactions, but read data are single packet as requested 
    
    errorRead stays high when there was error on axi r channel
    it will not affect unit functionality
    \n""" + Axi_datapumpBase.__doc__


    def _config(self):
        super()._config()
        
        self.DEFAULT_ID = Param(0)
        self.USER_WIDTH = Param(2)  # if 0 is used user signal completly disapears
        
    def _declr(self):
        super()._declr()  # add clk, rst, axi addr channel and req channel
        with self._asExtern():
            with self._paramsShared():
                self.r = Axi4_r()
                self.rOut = AxiStream_withId()
                
                self.errorRead = Signal()
        
        with self._paramsShared():
            f = self.sizeRmFifo = HandshakedFifo(TransEndInfo)
            f.DEPTH.set(self.MAX_TRANS_OVERLAP)
    
    
    def arIdHandler(self, lastReqDispatched):
        a = self.a
        req_idBackup = self._reg("req_idBackup", self.req.id._dtype)
        If(lastReqDispatched,
            req_idBackup ** self.req.id,
            a.id ** self.req.id <commit_msg>rm deprecated code<commit_after>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hdl_toolkit.bitmask import mask
from hdl_toolkit.interfaces.std import Signal, HandshakeSync, VectSignal
from hdl_toolkit.interfaces.utils import log2ceil, propagateClkRstn
from hdl_toolkit.synthesizer.codeOps import If, Switch, connect
from hdl_toolkit.synthesizer.param import Param
from hwtLib.axi.axi_datapump_base import Axi_datapumpBase
from hwtLib.handshaked.fifo import HandshakedFifo
from hwtLib.interfaces.amba import (Axi4_r, AxiStream_withId)
from hwtLib.interfaces.amba_constants import RESP_OKAY
from hwtLib.handshaked.streamNode import streamSync


class TransEndInfo(HandshakeSync):
    def _config(self):
        self.DATA_WIDTH = Param(64)
    
    def _declr(self):
        # rem is number of bits in last word which is valid - 1
        self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8))

        self.propagateLast = Signal()
        HandshakeSync._declr(self)

class Axi_rDatapump(Axi_datapumpBase):
    """
    Foward req to axi ar channel 
    and collect data to data channel form axi r channel 
    
    This unit simplifies axi interface,
    blocks data channel when there is no request pending
    and contains frame merging logic if is required
    
    if req len is wider transaction is internally splited to multiple
    transactions, but read data are single packet as requested 
    
    errorRead stays high when there was error on axi r channel
    it will not affect unit functionality
    \n""" + Axi_datapumpBase.__doc__

    def _declr(self):
        super()._declr()  # add clk, rst, axi addr channel and req channel
        with self._asExtern():
            with self._paramsShared():
                self.r = Axi4_r()
                self.rOut = AxiStream_withId()
                
                self.errorRead = Signal()
        
        with self._paramsShared():
            f = self.sizeRmFifo = HandshakedFifo(TransEndInfo)
            f.DEPTH.set(self.MAX_TRANS_OVERLAP)
    
    
    def arIdHandler(self, lastReqDispatched):
        a = self.a
        req_idBackup = self._reg("req_idBackup", self.req.id._dtype)
        If(lastReqDispatched,
            req_idBackup ** self.req.id,
            a.id ** self.req.id 
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