<commit_before>create_project -force -part $::env(XRAY_PART) design design

read_verilog $::env(FUZDIR)/top.v
synth_design -top top

set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]

create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0

place_design
route_design

# write_checkpoint -force design.dcp

source "$::env(XRAY_DIR)/utils/utils.tcl"

set fp [open "../../todo.txt" r]
set todo_lines {}
for {gets $fp line} {$line != ""} {gets $fp line} {
    lappend todo_lines [split $line .]
}
close $fp

set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]

set fp [open "design.txt" w]

for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
    set line [lindex $todo_lines $idx]
    puts "== $idx: $line"

    set tile_type [lindex $line 0]
    set dst_wire [lindex $line 1]
    set src_wire [lindex $line 2]

    set mylut [create_cell -reference LUT1 mylut_$idx]

    set mynet [create_net mynet_$idx]
    connect_net -net $mynet -objects "$mylut/I0 $mylut/O"

    set tries 0
    while {1} {
        set tile_idx [expr $tries + [expr $idx * 3]]
        incr tries

        if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $tile_idx]; set other_tile [lindex $int_r_tiles $idx]}
        if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $tile_idx]; set other_tile [lindex $int_l_tiles $idx]}

        puts "PIP Tile: $tile"

        set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
                -of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
<commit_msg>Increase number of tiles available for retries for 057.<commit_after>create_project -force -part $::env(XRAY_PART) design design

read_verilog $::env(FUZDIR)/top.v
synth_design -top top

set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]

create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0

place_design
route_design

# write_checkpoint -force design.dcp

source "$::env(XRAY_DIR)/utils/utils.tcl"

set fp [open "../../todo.txt" r]
set todo_lines {}
for {gets $fp line} {$line != ""} {gets $fp line} {
    lappend todo_lines [split $line .]
}
close $fp

# each run can fail up to three times so we need to prepare 3*todo_lines tiles to work on
set tiles [expr 3 * [llength $todo_lines]]

set int_l_tiles [randsample_list $tiles [filter [pblock_tiles roi] {TYPE == INT_L}]]
set int_r_tiles [randsample_list $tiles [filter [pblock_tiles roi] {TYPE == INT_R}]]

set fp [open "design.txt" w]

for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
    set line [lindex $todo_lines $idx]
    puts "== $idx: $line"

    set tile_type [lindex $line 0]
    set dst_wire [lindex $line 1]
    set src_wire [lindex $line 2]

    set mylut [create_cell -reference LUT1 mylut_$idx]

    set mynet [create_net mynet_$idx]
    connect_net -net $mynet -objects "$mylut/I0 $mylut/O"

    set tries 0
    while {1} {
        set tile_idx [expr $tries + [expr $idx * 3]]
        incr tries

        if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $tile_idx]; set other_tile [lindex $int_r_tiles $idx]}
        if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $tile_idx]; set other_tile [lindex $int_l_tiles $idx]}

        puts "PIP Tile: $tile"

        set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
                -of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]

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{'dir': 'git-commits-cleaned', 'id': '7197437', 'n_tokens_mistral': 1661, 'n_tokens_neox': 1611, 'n_words': 444}