<commit_before><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />

<bitset name="nv98_fuc_intr" inline="yes">
	<bitfield pos="2" name="FIFO_DATA"/>
	<bitfield pos="3" name="CHANNEL_SWITCH"/>
	<bitfield pos="4" name="EXIT"/>
	<bitfield pos="6" name="USER1"/> <!-- there are more... -->
</bitset>

<group name="nv98_fucbase">
	<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x004" name="INTR_ACK" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x008" name="INTR" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x010" name="INTR_EN_SET" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x014" name="INTR_EN_CLR" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x018" name="INTR_EN" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x01c" name="INTR_DISPATCH">
		<doc>
			Each interrupt has 2 bits in here, and its handling
			is determined by their combination:
			<ul>
			<li>M1 = 0, M2 = 0: fuc interrupt 0</li>
			<li>M1 = 0, M2 = 1: fuc interrupt 1</li>
			<li>M1 = 1, M2 = 0: host interrupt</li>
			<li>M1 = 1, M2 = 1: ignored</li>
			</ul>
		</doc>
		<bitfield low="0" high="15" name="M1" type="nv98_fuc_intr"/>
		<bitfield low="16" high="31" name="M2" type="nv98_fuc_intr"/>
	</reg32>

	<!-- the following two are conspiciously absent from PGRAPH. -->
	<reg32 offset="0x02c" name="TIME_LOW"/>
	<reg32 offset="0x030" name="TIME_HIGH"/>

	<reg32 offset="0x040" name="SCRATCH" length="2"/>

	<reg32 offset="0x048" name="ACCESS_EN">
		<bitfield pos="0" name="CHANNEL_SWITCH"/>
		<bitfield pos="1" name="FIFO"/>
	</reg32>
	<!-- 4c also related to FIFO/switching -->

	<!-- the following two are also conspiciously absent from PGRAPH. -->
	<reg32 offset="0x050" name="CHANNEL_CUR">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x054" name="CHANNEL_NEXT">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>

	<reg32 offset="0x064" name="FIFO_DATA"/>
	<reg32 offset="0x068" name="FIFO_CMD">
		<bitfield low="0" high="10" name="MTHD" shr="2"/>
		<bitfield low="11" high="13" name="SUBC"/> <!-- guess... -->
		<bitfield pos="14" name="NONINCR"/> <!-- even bigger guess... -->
	</reg32>
	<reg32 offset="0x070" name="FIFO_OCCUPIED"/>
	<reg32 offset="0x074" name="FIFO_HEAD_ADVANCE">
		<doc>Write 1 to go to next command.</doc>
	</reg32>
	<reg32 offset="0x078" name="FIFO_LIMIT">
		<doc>Up to 0x10</doc>
	</reg32>

	<reg32 offset="0x100" name="CTRL">
		<bitfield pos="1" name="START_TRIGGER"/>
	</reg32>

	<reg32 offset="0x104" name="ENTRY"/>

	<reg32 offset="0x108" name="CAPS">
		<bitfield low="0" high="8" name="CODE_SIZE" shr="8"/>
		<bitfield low="9" high="16" name="DATA_SIZE" shr="8"/>
	</reg32>

	<reg32 offset="0x110" name="XFER_EXT_BASE" shr="8"/>
	<reg32 offset="0x114" name="XFER_FUC_ADDR"/>
	<reg32 offset="0x118" name="XFER_CTRL">
		<bitfield pos="4" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/>
		</bitfield>
		<bitfield pos="5" name="DIR">
			<value value="0" name="LOAD"/>
			<value value="1" name="STORE"/>
		</bitfield>
		<bitfield low="8" high="10" name="SIZE">
			<value value="2" name="16"/>
			<value value="3" name="32"/>
			<value value="4" name="64"/>
			<value value="5" name="128"/>
			<value value="6" name="256"/>
		</bitfield>
		<bitfield low="12" high="14" name="TARGET"/>
	</reg32>
	<reg32 offset="0x11c" name="XFER_EXT_ADDR">
		<doc>Also virtual address for code.</doc>
	</reg32>

	<reg32 offset="0x180" name="CODE_INDEX" variants="NVA3-">
		<bitfield high="15" low="2" name="PHYS_ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
		<bitfield pos="28" name="UNK28"/>
	</reg32>
	<reg32 offset="0x184" name="CODE" variants="NVA3-"/>
	<reg32 offset="0x188" name="CODE_VIRT_ADDR" shr="8" variants="NVA3-"/>
	<reg32 offset="0x1c0" name="DATA_INDEX" variants="NVA3-">
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
	</reg32>
	<reg32 offset="0x1c4" name="DATA" variants="NVA3-"/>

	<reg32 offset="0xff0" name="PC"/>
	<reg32 offset="0xff4" name="UPLOAD"/>
	<reg32 offset="0xff8" name="UPLOAD_ADDR">
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="20" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/> <!-- pre-NVA3 only? -->
		</bitfield>
		<bitfield pos="21" name="READBACK"/>
		<bitfield pos="28" name="UNK28"/>
		<bitfield pos="29" name="CODE_BUSY"/>
	</reg32>
	<reg32 offset="0xffc" name="HOST_MMIO_INDEX"/>
</group>

<group name="nv98_fuc_targets">
	<reg32 offset="0x600" length="8" name="TARGET" variants="NV50:NVC0">
		<doc>Note that target 7 is hardwired to point to context DMAobj.</doc>
		<bitfield low="0" high="15" name="INST" shr="4"/>
		<bitfield low="24" high="26" name="TYPE">
			<value value="0" name="DMAOBJ"/>
			<value value="4" name="VRAM"/>
			<value value="5" name="SYSRAM"/>
			<value value="6" name="SYSRAM_NO_SNOOP"/>
		</bitfield>
		<bitfield pos="30" name="VALID"/>
		<bitfield pos="31" name="UNK31"/>
	</reg32>
	<reg32 offset="0x600" length="8" name="TARGET" variants="NVC0-">
		<bitfield low="0" high="2" name="TYPE">
			<value value="0" name="VM"/>
			<value value="1" name="UNK1"/>
			<value value="2" name="UNK2"/>
			<value value="4" name="VRAM"/>
			<value value="5" name="SYSRAM"/>
			<value value="6" name="SYSRAM_NO_SNOOP"/>
		</bitfield>
		<bitfield low="4" high="5" name="UNK4"/>
		<bitfield low="8" high="9" name="UNK8"/>
		<bitfield low="12" high="15" name="UNK12"/>
	</reg32>
</group>

</database>
<commit_msg>fuc: Nailed down the watchdog stuff.<commit_after><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />

<bitset name="nv98_fuc_intr" inline="yes">
	<bitfield pos="1" name="WATCHDOG"/>
	<bitfield pos="2" name="FIFO_DATA"/>
	<bitfield pos="3" name="CHANNEL_SWITCH"/>
	<bitfield pos="4" name="EXIT"/>
	<bitfield pos="6" name="USER1"/> <!-- there are more... -->
</bitset>

<group name="nv98_fucbase">
	<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x004" name="INTR_ACK" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x008" name="INTR" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x010" name="INTR_EN_SET" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x014" name="INTR_EN_CLR" access="w" type="nv98_fuc_intr"/>
	<reg32 offset="0x018" name="INTR_EN" access="r" type="nv98_fuc_intr"/>
	<reg32 offset="0x01c" name="INTR_DISPATCH">
		<doc>
			Each interrupt has 2 bits in here, and its handling
			is determined by their combination:
			<ul>
			<li>M1 = 0, M2 = 0: fuc interrupt 0</li>
			<li>M1 = 0, M2 = 1: fuc interrupt 1</li>
			<li>M1 = 1, M2 = 0: host interrupt</li>
			<li>M1 = 1, M2 = 1: ignored</li>
			</ul>
		</doc>
		<bitfield low="0" high="15" name="M1" type="nv98_fuc_intr"/>
		<bitfield low="16" high="31" name="M2" type="nv98_fuc_intr"/>
	</reg32>

	<!-- the following two are conspiciously absent from PGRAPH. -->
	<reg32 offset="0x02c" name="TIME_LOW"/>
	<reg32 offset="0x030" name="TIME_HIGH"/>
	<reg32 offset="0x034" name="WATCHDOG_TIME"/>
	<reg32 offset="0x038" name="WATCHDOG_ENABLE"/>

	<reg32 offset="0x040" name="SCRATCH" length="2"/>

	<reg32 offset="0x048" name="ACCESS_EN">
		<bitfield pos="0" name="CHANNEL_SWITCH"/>
		<bitfield pos="1" name="FIFO"/>
	</reg32>
	<!-- 4c also related to FIFO/switching -->

	<!-- the following two are also conspiciously absent from PGRAPH. -->
	<reg32 offset="0x050" name="CHANNEL_CUR">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x054" name="CHANNEL_NEXT">
		<bitfield name="CHAN" high="29" low="0" type="nv50_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>

	<reg32 offset="0x064" name="FIFO_DATA"/>
	<reg32 offset="0x068" name="FIFO_CMD">
		<bitfield low="0" high="10" name="MTHD" shr="2"/>
		<bitfield low="11" high="13" name="SUBC"/> <!-- guess... -->
		<bitfield pos="14" name="NONINCR"/> <!-- even bigger guess... -->
	</reg32>
	<reg32 offset="0x070" name="FIFO_OCCUPIED"/>
	<reg32 offset="0x074" name="FIFO_HEAD_ADVANCE">
		<doc>Write 1 to go to next command.</doc>
	</reg32>
	<reg32 offset="0x078" name="FIFO_LIMIT">
		<doc>Up to 0x10</doc>
	</reg32>

	<reg32 offset="0x100" name="CTRL">
		<bitfield pos="1" name="START_TRIGGER"/>
	</reg32>

	<reg32 offset="0x104" name="ENTRY"/>

	<reg32 offset="0x108" name="CAPS">
		<bitfield low="0" high="8" name="CODE_SIZE" shr="8"/>
		<bitfield low="9" high="16" name="DATA_SIZE" shr="8"/>
	</reg32>

	<reg32 offset="0x110" name="XFER_EXT_BASE" shr="8"/>
	<reg32 offset="0x114" name="XFER_FUC_ADDR"/>
	<reg32 offset="0x118" name="XFER_CTRL">
		<bitfield pos="4" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/>
		</bitfield>
		<bitfield pos="5" name="DIR">
			<value value="0" name="LOAD"/>
			<value value="1" name="STORE"/>
		</bitfield>
		<bitfield low="8" high="10" name="SIZE">
			<value value="2" name="16"/>
			<value value="3" name="32"/>
			<value value="4" name="64"/>
			<value value="5" name="128"/>
			<value value="6" name="256"/>
		</bitfield>
		<bitfield low="12" high="14" name="TARGET"/>
	</reg32>
	<reg32 offset="0x11c" name="XFER_EXT_ADDR">
		<doc>Also virtual address for code.</doc>
	</reg32>

	<reg32 offset="0x180" name="CODE_INDEX" variants="NVA3-">
		<bitfield high="15" low="2" name="PHYS_ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
		<bitfield pos="28" name="UNK28"/>
	</reg32>
	<reg32 offset="0x184" name="CODE" variants="NVA3-"/>
	<reg32 offset="0x188" name="CODE_VIRT_ADDR" shr="8" variants="NVA3-"/>
	<reg32 offset="0x1c0" name="DATA_INDEX" variants="NVA3-">
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
	</reg32>
	<reg32 offset="0x1c4" name="DATA" variants="NVA3-"/>

	<reg32 offset="0xff0" name="PC"/>
	<reg32 offset="0xff4" name="UPLOAD"/>
	<reg32 offset="0xff8" name="UPLOAD_ADDR">
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="20" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/> <!-- pre-NVA3 only? -->
		</bitfield>
		<bitfield pos="21" name="READBACK"/>
		<bitfield pos="28" name="UNK28"/>
		<bitfield pos="29" name="CODE_BUSY"/>
	</reg32>
	<reg32 offset="0xffc" name="HOST_MMIO_INDEX"/>
</group>

<group name="nv98_fuc_targets">
	<reg32 offset="0x600" length="8" name="TARGET" variants="NV50:NVC0">
		<doc>Note that target 7 is hardwired to point to context DMAobj.</doc>
		<bitfield low="0" high="15" name="INST" shr="4"/>
		<bitfield low="24" high="26" name="TYPE">
			<value value="0" name="DMAOBJ"/>
			<value value="4" name="VRAM"/>
			<value value="5" name="SYSRAM"/>
			<value value="6" name="SYSRAM_NO_SNOOP"/>
		</bitfield>
		<bitfield pos="30" name="VALID"/>
		<bitfield pos="31" name="UNK31"/>
	</reg32>
	<reg32 offset="0x600" length="8" name="TARGET" variants="NVC0-">
		<bitfield low="0" high="2" name="TYPE">
			<value value="0" name="VM"/>
			<value value="1" name="UNK1"/>
			<value value="2" name="UNK2"/>
			<value value="4" name="VRAM"/>
			<value value="5" name="SYSRAM"/>
			<value value="6" name="SYSRAM_NO_SNOOP"/>
		</bitfield>
		<bitfield low="4" high="5" name="UNK4"/>
		<bitfield low="8" high="9" name="UNK8"/>
		<bitfield low="12" high="15" name="UNK12"/>
	</reg32>
</group>

</database>

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