<commit_before>#=========================================================================
# Tile_test.py
#=========================================================================
# ParcProc5stBypass assembly tests driver

from new_pymtl import *
from new_pmlib import mem_msgs
from new_pmlib import TestMemory
from new_pmlib import TestProcManager
from new_pmlib import SparseMemoryImage
from Tile      import Tile

#-----------------------------------------------------------------------
# TestHarness
#-----------------------------------------------------------------------
class TestHarness( Model ):

  #---------------------------------------------------------------------
  # __init__
  #---------------------------------------------------------------------
  def __init__( s, ModelType, memreq_params, memresp_params,
                mem_delay, sparse_mem_img, test_verilog ):

    data_nbits = memreq_params.data_nbits
    print data_nbits
    s.tile     = ModelType( reset_vector   = 0x00000400,
                            mem_data_nbits = data_nbits )
    s.mem      = TestMemory( memreq_params, memresp_params, 2,
                             mem_delay, mem_nbytes=2**24  )
    s.proc_mgr = TestProcManager( s.mem, sparse_mem_img )

    if test_verilog:
      s.tile = get_verilated( s.tile )

  def elaborate_logic( s ):

    # Connect Manager Signals

    s.connect( s.proc_mgr.proc_go,     s.tile.go         )
    s.connect( s.proc_mgr.proc_status, s.tile.status     )

    # Memory Request/Response Signals

    s.connect( s.tile.memreq [0], s.mem.reqs [0] )
    s.connect( s.tile.memresp[0], s.mem.resps[0] )
    s.connect( s.tile.memreq [1], s.mem.reqs [1] )
    s.connect( s.tile.memresp[1], s.mem.resps[1] )

  #---------------------------------------------------------------------
  # done
  #---------------------------------------------------------------------
  def done( s ):
    return s.proc_mgr.done

  #---------------------------------------------------------------------
  # line_trace
  #---------------------------------------------------------------------
  def line_trace( s ):
    return s.proc_mgr.line_trace() + \
           s.tile.line_trace() #+ \
           #s.mem.line_trace()

#-----------------------------------------------------------------------
# run_proc_test
#-----------------------------------------------------------------------
# function to drive the unit tests
def run_proc_test( ModelType, test_verilog, dump_vcd, vcd_file, input_list ):

  # Instantiate and elaborate the model

  #memreq_params  = mem_msgs.MemReqParams( 32, 128 )
  #memresp_params = mem_msgs.MemRespParams( 128 )
  memreq_params  = mem_msgs.MemReqParams( 32, 32 )
  memresp_params = mem_msgs.MemRespParams( 32 )

  # input_list parameters

  mem_delay       = input_list[0]
  sparse_mem_img  = input_list[1]
  expected_result = input_list[2]

  # Instantiate and elaborate test harness model

  model = TestHarness( ModelType, memreq_params, memresp_params,
                       mem_delay, sparse_mem_img, test_verilog )
  model.elaborate()

  # Create a simulator using the simulation tool

  sim = SimulationTool( model )
  if dump_vcd:
    sim.dump_vcd( vcd_file )

  # Run the simulation

  print ""

  sim.reset()
  while not model.done() and sim.ncycles < 4000:
    sim.print_line_trace()
    sim.cycle()

  assert model.done()
  assert model.tile.status == expected_result

  # Add a couple extra ticks so that the VCD dump is nicer

  sim.cycle()
  sim.cycle()
  sim.cycle()

#-----------------------------------------------------------------------
# run_bypass_proc_test
#-----------------------------------------------------------------------
def run_bypass_proc_test( dump_vcd, test_verilog, vcd_file_name, input_list ):
  run_proc_test( Tile, test_verilog,
                 dump_vcd, vcd_file_name, input_list )

#---------------------------------------------------------------------------
# X. mtc2 tests - matrix vector multiplier specific
#---------------------------------------------------------------------------

test_start = """
  .text;<commit_msg>[dotprod] hack: delete bytearray to reduce memory footprint (details)<commit_after>#=========================================================================
# Tile_test.py
#=========================================================================
# ParcProc5stBypass assembly tests driver

from new_pymtl import *
from new_pmlib import mem_msgs
from new_pmlib import TestMemory
from new_pmlib import TestProcManager
from new_pmlib import SparseMemoryImage
from Tile      import Tile

#-----------------------------------------------------------------------
# TestHarness
#-----------------------------------------------------------------------
class TestHarness( Model ):

  #---------------------------------------------------------------------
  # __init__
  #---------------------------------------------------------------------
  def __init__( s, ModelType, memreq_params, memresp_params,
                mem_delay, sparse_mem_img, test_verilog ):

    data_nbits = memreq_params.data_nbits
    s.tile     = ModelType( reset_vector   = 0x00000400,
                            mem_data_nbits = data_nbits )
    s.mem      = TestMemory( memreq_params, memresp_params, 2,
                             mem_delay, mem_nbytes=2**24  )
    s.proc_mgr = TestProcManager( s.mem, sparse_mem_img )

    if test_verilog:
      s.tile = get_verilated( s.tile )

  def elaborate_logic( s ):

    # Connect Manager Signals

    s.connect( s.proc_mgr.proc_go,     s.tile.go         )
    s.connect( s.proc_mgr.proc_status, s.tile.status     )

    # Memory Request/Response Signals

    s.connect( s.tile.memreq [0], s.mem.reqs [0] )
    s.connect( s.tile.memresp[0], s.mem.resps[0] )
    s.connect( s.tile.memreq [1], s.mem.reqs [1] )
    s.connect( s.tile.memresp[1], s.mem.resps[1] )

  def cleanup( s ):
    del s.mem.mem.mem[:]

  #---------------------------------------------------------------------
  # done
  #---------------------------------------------------------------------
  def done( s ):
    return s.proc_mgr.done

  #---------------------------------------------------------------------
  # line_trace
  #---------------------------------------------------------------------
  def line_trace( s ):
    return s.proc_mgr.line_trace() + \
           s.tile.line_trace() #+ \
           #s.mem.line_trace()

#-----------------------------------------------------------------------
# run_proc_test
#-----------------------------------------------------------------------
# function to drive the unit tests
def run_proc_test( ModelType, test_verilog, dump_vcd, vcd_file, input_list ):

  # Instantiate and elaborate the model

  #memreq_params  = mem_msgs.MemReqParams( 32, 128 )
  #memresp_params = mem_msgs.MemRespParams( 128 )
  memreq_params  = mem_msgs.MemReqParams( 32, 32 )
  memresp_params = mem_msgs.MemRespParams( 32 )

  # input_list parameters

  mem_delay       = input_list[0]
  sparse_mem_img  = input_list[1]
  expected_result = input_list[2]

  # Instantiate and elaborate test harness model

  model = TestHarness( ModelType, memreq_params, memresp_params,
                       mem_delay, sparse_mem_img, test_verilog )
  model.elaborate()

  # Create a simulator using the simulation tool

  sim = SimulationTool( model )
  if dump_vcd:
    sim.dump_vcd( vcd_file )

  # Run the simulation

  print ""

  sim.reset()
  while not model.done() and sim.ncycles < 4000:
    sim.print_line_trace()
    sim.cycle()

  assert model.done()
  assert model.tile.status == expected_result

  # Add a couple extra ticks so that the VCD dump is nicer

  sim.cycle()
  sim.cycle()
  sim.cycle()

  model.cleanup()

#-----------------------------------------------------------------------
# run_bypass_proc_test
#-----------------------------------------------------------------------
def run_bypass_proc_test( dump_vcd, test_verilog, vcd_file_name, input_list ):
  run_proc_test( Tile, test_verilog,
                 dump_vcd, vcd_file_name, input_list )

#---------------------------------------------------------------------------
# X. mtc2 tests - matrix vector multiplier specific
#---------------------------------------------------------------------------

test_start = """
  .text;
{'fraction_non_alphanumeric': 0.3442998312846469, 'fraction_numerical': 0.010604965051819716, 'mean_word_length': 1.353658536585366, 'pattern_counts': {'":': 0, '<': 5, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6578823', 'n_tokens_mistral': 2359, 'n_tokens_neox': 2210, 'n_words': 489}