<commit_before>#include "redirect_memory.h"
#include "simulator.h"
#include "core_manager.h"
#include "core.h"
#include "pin_memory_manager.h"
#include "performance_model.h"

// FIXME
// Only need this function because some memory accesses are made before cores have
// been initialized. Should not evnentually need this

VOID printInsInfo(CONTEXT* ctxt)
{
   __attribute(__unused__) ADDRINT reg_inst_ptr = PIN_GetContextReg(ctxt, REG_INST_PTR);
   __attribute(__unused__) ADDRINT reg_stack_ptr = PIN_GetContextReg(ctxt, REG_STACK_PTR);

   LOG_PRINT("eip = 0x%x, esp = 0x%x", reg_inst_ptr, reg_stack_ptr);
}

void memOp (Core::lock_signal_t lock_signal, Core::mem_op_t mem_op_type, IntPtr d_addr, char *data_buffer, UInt32 data_size)
{   
   assert (lock_signal == Core::NONE);

   Core *core = Sim()->getCoreManager()->getCurrentCore();
   LOG_ASSERT_ERROR(core, "Could not find Core object for current thread");
   core->accessMemory (lock_signal, mem_op_type, d_addr, data_buffer, data_size, true);
}

bool rewriteStringOp (INS ins)
{
   if (! (INS_RepPrefix(ins) || INS_RepnePrefix(ins)))
   {
      // No REP prefix
      return false;
   }

   if (INS_Opcode(ins) == XED_ICLASS_SCASB)
   {
      INS_InsertCall(ins, IPOINT_BEFORE,
            AFUNPTR (emuSCASBIns),
            IARG_CONTEXT,
            IARG_ADDRINT, INS_NextAddress(ins),
            IARG_BOOL, INS_RepPrefix(ins),
            IARG_END);

      INS_Delete(ins);

      return true;
   }

   else if (INS_Opcode(ins) == XED_ICLASS_CMPSB)
   {
      INS_InsertCall(ins, IPOINT_BEFORE,
            AFUNPTR (emuCMPSBIns),
            IARG_CONTEXT,
            IARG_ADDRINT, INS_NextAddress(ins),
            IARG_BOOL, INS_RepPrefix(ins),
            IARG_END);

      INS_Delete(ins);
      
      return true;
   }

   else
   {
      // Has a REP or REPNE prefix
      if (  (INS_Opcode(ins) == XED_ICLASS_MOVSB) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSW) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSD) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSD_XMM) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSB) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSW) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSD) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVDQU)
         )
      {
         return false;
      }

      LOG_ASSERT_ERROR(! (INS_IsMemoryRead(ins) || INS_IsMemoryWrite(ins)), "Ins: %s not currently supported", INS_Disassemble(ins).c_str());
      
      return false;
   }
}


void emuCMPSBIns(CONTEXT *ctxt, ADDRINT next_gip, bool has_rep_prefix)
{
   __attribute(__unused__) ADDRINT reg_gip = PIN_GetContextReg(ctxt, REG_INST_PTR);
   LOG_PRINT("REP CMPSB Instruction: EIP(0x%x)", reg_gip);

   assert(has_rep_prefix == true);
   
   ADDRINT reg_gcx = PIN_GetContextReg(ctxt, REG_GCX);<commit_msg>[64 bit] New instructions that arise in 64 bit handled<commit_after>#include "redirect_memory.h"
#include "simulator.h"
#include "core_manager.h"
#include "core.h"
#include "pin_memory_manager.h"
#include "performance_model.h"

// FIXME
// Only need this function because some memory accesses are made before cores have
// been initialized. Should not evnentually need this

VOID printInsInfo(CONTEXT* ctxt)
{
   __attribute(__unused__) ADDRINT reg_inst_ptr = PIN_GetContextReg(ctxt, REG_INST_PTR);
   __attribute(__unused__) ADDRINT reg_stack_ptr = PIN_GetContextReg(ctxt, REG_STACK_PTR);

   LOG_PRINT("eip = 0x%x, esp = 0x%x", reg_inst_ptr, reg_stack_ptr);
}

void memOp (Core::lock_signal_t lock_signal, Core::mem_op_t mem_op_type, IntPtr d_addr, char *data_buffer, UInt32 data_size)
{   
   assert (lock_signal == Core::NONE);

   Core *core = Sim()->getCoreManager()->getCurrentCore();
   LOG_ASSERT_ERROR(core, "Could not find Core object for current thread");
   core->accessMemory (lock_signal, mem_op_type, d_addr, data_buffer, data_size, true);
}

bool rewriteStringOp (INS ins)
{
   if (! (INS_RepPrefix(ins) || INS_RepnePrefix(ins)))
   {
      // No REP prefix
      return false;
   }

   if (INS_Opcode(ins) == XED_ICLASS_SCASB)
   {
      INS_InsertCall(ins, IPOINT_BEFORE,
            AFUNPTR (emuSCASBIns),
            IARG_CONTEXT,
            IARG_ADDRINT, INS_NextAddress(ins),
            IARG_BOOL, INS_RepPrefix(ins),
            IARG_END);

      INS_Delete(ins);

      return true;
   }

   else if (INS_Opcode(ins) == XED_ICLASS_CMPSB)
   {
      INS_InsertCall(ins, IPOINT_BEFORE,
            AFUNPTR (emuCMPSBIns),
            IARG_CONTEXT,
            IARG_ADDRINT, INS_NextAddress(ins),
            IARG_BOOL, INS_RepPrefix(ins),
            IARG_END);

      INS_Delete(ins);
      
      return true;
   }

   else
   {
      // Has a REP or REPNE prefix
      if (  (INS_Opcode(ins) == XED_ICLASS_MOVSB) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSW) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSS) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSD) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVSD_XMM) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSB) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSW) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSD) ||
            (INS_Opcode(ins) == XED_ICLASS_STOSQ) ||
            (INS_Opcode(ins) == XED_ICLASS_MOVDQU) ||
            (INS_Opcode(ins) == XED_ICLASS_RET_NEAR) ||
            (INS_Opcode(ins) == XED_ICLASS_CVTSI2SS) ||
            (INS_Opcode(ins) == XED_ICLASS_CVTSI2SD) ||
            (INS_Opcode(ins) == XED_ICLASS_SQRTSS) ||
            (INS_Opcode(ins) == XED_ICLASS_SQRTSD) ||
            (INS_Opcode(ins) == XED_ICLASS_MULSS) ||
            (INS_Opcode(ins) == XED_ICLASS_MULSD) ||
            (INS_Opcode(ins) == XED_ICLASS_DIVSS) ||
            (INS_Opcode(ins) == XED_ICLASS_DIVSD) ||
            (INS_Opcode(ins) == XED_ICLASS_ADDSS) ||
            (INS_Opcode(ins) == XED_ICLASS_ADDSD) ||
            (INS_Opcode(ins) == XED_ICLASS_SUBSS) ||
            (INS_Opcode(ins) == XED_ICLASS_SUBSD)
         )
      {
         return false;
      }

      LOG_ASSERT_ERROR(! (INS_IsMemoryRead(ins) || INS_IsMemoryWrite(ins)), "Ins: %s (0x%x) not currently supported", INS_Disassemble(ins).c_str(), INS_Address (ins));
      
      return false;
   }
}


void emuCMPSBIns(CONTEXT *ctxt, ADDRINT next_gip, bool has_rep_prefix)
{
   __attribute(__unused__) ADDRINT reg_gip = PIN_GetContextReg(ctxt, REG_INST_PTR);
   LOG_PRINT("REP CMPSB Instruction: EIP(0x%x)", reg_gip);

   assert(has_rep_prefix == true);
   
   ADDRINT reg_gcx = PIN_GetContextReg(ctxt, REG_GCX);
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