<commit_before>/*
 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief       ia32 architecture variants
 * @author      <NAME>, <NAME>
 * @version     $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
 */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "lc_opts.h"
#include "lc_opts_enum.h"

#include "irtools.h"

#include "bearch_ia32_t.h"
#include "ia32_architecture.h"

ia32_code_gen_config_t  ia32_cg_config;

/**
 * CPU features.
 */
enum cpu_arch_features {
	arch_feature_intel    = 0x80000000,                      /**< Intel CPU */
	arch_feature_amd      = 0x40000000,                      /**< AMD CPU */
	arch_feature_p6       = 0x20000000,                      /**< P6 instructions */
	arch_feature_mmx      = 0x10000000,                      /**< MMX instructions */
	arch_feature_sse1     = 0x08000000 | arch_feature_mmx,   /**< SSE1 instructions, include MMX */
	arch_feature_sse2     = 0x04000000 | arch_feature_sse1,  /**< SSE2 instructions, include SSE1 */
	arch_feature_sse3     = 0x02000000 | arch_feature_sse2,  /**< SSE3 instructions, include SSE2 */
	arch_feature_ssse3    = 0x01000000 | arch_feature_sse3,  /**< SSSE3 instructions, include SSE3 */
	arch_feature_3DNow    = 0x00800000,                      /**< 3DNow! instructions */
	arch_feature_3DNowE   = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
	arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
	arch_feature_64bit    = 0x00100000 | arch_feature_sse2,  /**< x86_64 support, include SSE2 */
};

/**
 * Architectures.
 */
enum cpu_support {
	/* intel CPU's */
	arch_generic     =  0,

	arch_i386        =  1,
	arch_i486        =  2,
	arch_pentium     =  3 | arch_feature_intel,
	arch_pentium_mmx =  4 | arch_feature_intel | arch_feature_mmx,
	arch_pentium_pro =  5 | arch_feature_intel | arch_feature_p6,
	arch_pentium_2   =  6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
	arch_pentium_3   =  7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
	arch_pentium_4   =  8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
	arch_pentium_m   =  9 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
	arch_core        = 10 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
	arch_prescott    = 11 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
	arch_core2       = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,

	/* AMD CPU's */
	arch_k6          = 13 | arch_feature_amd | arch_feature_mmx,
	arch_k6_2        = 14 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
	arch_k6_3        = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
	arch_athlon      = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
	arch_athlon_xp   = 17 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
	arch_opteron     = 18 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,

	/* other */
	arch_winchip_c6  = 19 | arch_feature_mmx,
	arch_winchip2    = 20 | arch_feature_mmx | arch_feature_3DNow,
	arch_c3          = 21 | arch_feature_mmx | arch_feature_3DNow,
	arch_c3_2        = 22 | arch_feature_sse1,  /* really no 3DNow! */
};

/** checks for l <= x <= h */
#define _IN_RANGE(x, l, h)  ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))

/** returns true if it's Intel architecture */
#define ARCH_INTEL(x)       (((x) & arch_feature_intel) != 0)

/** returns true if it's AMD architecture */
#define ARCH_AMD(x)         (((x) & arch_feature_amd) != 0)

/** return true if it's a Athlon/Opteron */
#define ARCH_ATHLON(x)      _IN_RANGE((x), arch_athlon, arch_opteron)

/** return true if the CPU has MMX support */
#define ARCH_MMX(x)         (((x) & arch_feature_mmx) != 0)

/** return true if the CPU has 3DNow! support */
#define ARCH_3DNow(x)       (((x) & arch_feature_3DNow) != 0)

/** return true if the CPU has P6 features (CMOV) */
#define IS_P6_ARCH(x)       (((x) & arch_feature_p6) != 0)

static cpu_support arch                 = arch_generic;
static cpu_support opt_arch             = arch_pentium_4;
static int         use_sse2             = 0;
static int         opt_cc               = 1;
static int         opt_unsafe_floatconv = 0;

/* instruction set architectures. */
static const lc_opt_enum_int_items_t arch_items[] = {
	{ "i386",       arch_i386, },
	{ "i486",       arch_i486, },
	{ "pentium",    arch_pentium, },
	{ "i586",       arch_pentium, },
	{ "pentiumpro", arch_pentium_pro, },
	{ "i686",       arch_pentium_pro, },
	{ "pentiummmx", arch_pentium_mmx, },
	{ "pentium2",   arch_pentium_2, },
	{ "p2",         arch_pentium_2, },
	{ "pentium3",   arch_pentium_3, },
	{ "p3",         arch_pentium_3, },
	{ "pentium4",   arch_pentium_4, },
	{ "p4",         arch_pentium_4, },
	{ "prescott",   arch_pentium_4, },
	{ "pentiumm",   arch_pentium_m, },
	{ "pm",         arch_pentium_m, },
	{ "core",       arch_core, },
	{ "yonah",      arch_core, },
	{ "merom",      arch_core2, },
	{ "nocona",     arch_core2, },
	{ "core2",      arch_core2, },
	{ "k6",         arch_k6, },
	{ "k6-2",       arch_k6_2, },
	{ "k6-3",       arch_k6_2, },
	{ "athlon",     arch_athlon, },
	{ "athlon-xp",  arch_athlon_xp, },
	{ "athlon-mp",  arch_athlon_xp, },
	{ "athlon-4",   arch_athlon_xp, },
	{ "athlon64",   arch_opteron, },
	{ "k8",         arch_opteron, },
	{ "opteron",    arch_opteron, },
	{ "generic",    arch_generic, },
	{ NULL,         0 }
};
<commit_msg>nocona is a Pentium 4 variant<commit_after>/*
 * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
 *
 * This file is part of libFirm.
 *
 * This file may be distributed and/or modified under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation and appearing in the file LICENSE.GPL included in the
 * packaging of this file.
 *
 * Licensees holding valid libFirm Professional Edition licenses may use
 * this file in accordance with the libFirm Commercial License.
 * Agreement provided with the Software.
 *
 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE.
 */

/**
 * @file
 * @brief       ia32 architecture variants
 * @author      <NAME>, <NAME>
 * @version     $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
 */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "lc_opts.h"
#include "lc_opts_enum.h"

#include "irtools.h"

#include "bearch_ia32_t.h"
#include "ia32_architecture.h"

ia32_code_gen_config_t  ia32_cg_config;

/**
 * CPU features.
 */
enum cpu_arch_features {
	arch_feature_intel    = 0x80000000,                      /**< Intel CPU */
	arch_feature_amd      = 0x40000000,                      /**< AMD CPU */
	arch_feature_p6       = 0x20000000,                      /**< P6 instructions */
	arch_feature_mmx      = 0x10000000,                      /**< MMX instructions */
	arch_feature_sse1     = 0x08000000 | arch_feature_mmx,   /**< SSE1 instructions, include MMX */
	arch_feature_sse2     = 0x04000000 | arch_feature_sse1,  /**< SSE2 instructions, include SSE1 */
	arch_feature_sse3     = 0x02000000 | arch_feature_sse2,  /**< SSE3 instructions, include SSE2 */
	arch_feature_ssse3    = 0x01000000 | arch_feature_sse3,  /**< SSSE3 instructions, include SSE3 */
	arch_feature_3DNow    = 0x00800000,                      /**< 3DNow! instructions */
	arch_feature_3DNowE   = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
	arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
	arch_feature_64bit    = 0x00100000 | arch_feature_sse2,  /**< x86_64 support, include SSE2 */
};

/**
 * Architectures.
 */
enum cpu_support {
	/* intel CPU's */
	arch_generic     =  0,

	arch_i386        =  1,
	arch_i486        =  2,
	arch_pentium     =  3 | arch_feature_intel,
	arch_pentium_mmx =  4 | arch_feature_intel | arch_feature_mmx,
	arch_pentium_pro =  5 | arch_feature_intel | arch_feature_p6,
	arch_pentium_2   =  6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
	arch_pentium_3   =  7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
	arch_pentium_4   =  8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
	arch_pentium_m   =  9 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
	arch_core        = 10 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
	arch_prescott    = 11 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
	arch_core2       = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,

	/* AMD CPU's */
	arch_k6          = 13 | arch_feature_amd | arch_feature_mmx,
	arch_k6_2        = 14 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
	arch_k6_3        = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
	arch_athlon      = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
	arch_athlon_xp   = 17 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
	arch_opteron     = 18 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,

	/* other */
	arch_winchip_c6  = 19 | arch_feature_mmx,
	arch_winchip2    = 20 | arch_feature_mmx | arch_feature_3DNow,
	arch_c3          = 21 | arch_feature_mmx | arch_feature_3DNow,
	arch_c3_2        = 22 | arch_feature_sse1,  /* really no 3DNow! */
};

/** checks for l <= x <= h */
#define _IN_RANGE(x, l, h)  ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))

/** returns true if it's Intel architecture */
#define ARCH_INTEL(x)       (((x) & arch_feature_intel) != 0)

/** returns true if it's AMD architecture */
#define ARCH_AMD(x)         (((x) & arch_feature_amd) != 0)

/** return true if it's a Athlon/Opteron */
#define ARCH_ATHLON(x)      _IN_RANGE((x), arch_athlon, arch_opteron)

/** return true if the CPU has MMX support */
#define ARCH_MMX(x)         (((x) & arch_feature_mmx) != 0)

/** return true if the CPU has 3DNow! support */
#define ARCH_3DNow(x)       (((x) & arch_feature_3DNow) != 0)

/** return true if the CPU has P6 features (CMOV) */
#define IS_P6_ARCH(x)       (((x) & arch_feature_p6) != 0)

static cpu_support arch                 = arch_generic;
static cpu_support opt_arch             = arch_pentium_4;
static int         use_sse2             = 0;
static int         opt_cc               = 1;
static int         opt_unsafe_floatconv = 0;

/* instruction set architectures. */
static const lc_opt_enum_int_items_t arch_items[] = {
	{ "i386",       arch_i386, },
	{ "i486",       arch_i486, },
	{ "pentium",    arch_pentium, },
	{ "i586",       arch_pentium, },
	{ "pentiumpro", arch_pentium_pro, },
	{ "i686",       arch_pentium_pro, },
	{ "pentiummmx", arch_pentium_mmx, },
	{ "pentium2",   arch_pentium_2, },
	{ "p2",         arch_pentium_2, },
	{ "pentium3",   arch_pentium_3, },
	{ "p3",         arch_pentium_3, },
	{ "pentium4",   arch_pentium_4, },
	{ "p4",         arch_pentium_4, },
	{ "prescott",   arch_pentium_4, },
	{ "nocona",     arch_pentium_4, },
	{ "pentiumm",   arch_pentium_m, },
	{ "pm",         arch_pentium_m, },
	/*
	 * core CPUs: Yonah
	 */
	{ "core",       arch_core, },
	{ "yonah",      arch_core, },
	/*
	 * core2 CPUs: Conroe (XE, L), Allendale, Merom (XE),
	 * Kentsfield (XE), Yorkfield XE, Penryn, Wolfdale, Yorkfield
	 */
	{ "merom",      arch_core2, },
	{ "core2",      arch_core2, },
	{ "k6",         arch_k6, },
	{ "k6-2",       arch_k6_2, },
	{ "k6-3",       arch_k6_2, },
	{ "athlon",     arch_athlon, },
	{ "athlon-xp",  arch_athlon_xp, },
	{ "athlon-mp",  arch_athlon_xp, },
	{ "athlon-4",   arch_athlon_xp, },
	{ "athlon64",   arch_opteron, },
	{ "k8",         arch_opteron, },
	{ "opteron",    arch_opteron, },
	{ "generic",    arch_generic, },
	{ NULL,         0 }
};

{'fraction_non_alphanumeric': 0.11887889163149933, 'fraction_numerical': 0.05271120312126762, 'mean_word_length': 3.1086032057572783, 'pattern_counts': {'":': 0, '<': 37, '<?xml version=': 0, '>': 7, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 8, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2243914', 'n_tokens_mistral': 5029, 'n_tokens_neox': 4636, 'n_words': 1007}