<commit_before>/*-----------------------------------------------------------------------*/
/* MMCv3/SDv1/SDv2 (in native mode via MCI) control module (C)ChaN, 2010 */
/*-----------------------------------------------------------------------*/
/* This program is opened under license policy of following trems.
/
/  Copyright (C) 2010, ChaN, all right reserved.
/
/ * This program is a free software and there is NO WARRANTY.
/ * No restriction on use. You can use, modify and redistribute it for
/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
/ * Redistributions of source code must retain the above copyright notice.
/
/---------------------------------------------------------------------------*/

#include <string.h>
#include "lpc23xx.h"
#include "VIC.h"
#include "xtimer.h"
#include "diskio.h"

#define ENABLE_DEBUG    (0)
#include "debug.h"

/* --- MCI configurations --- */
#define N_BUF       4           /* Block transfer FIFO depth (>= 2) */
#define USE_4BIT    1           /* Use wide bus mode if SDC is detected */
#define PCLK        36000000UL  /* PCLK supplied to MCI module */
#define MCLK_ID     400000UL    /* MCICLK for ID state (100k-400k) */
#define MCLK_RW     18000000UL  /* MCICLK for data transfer (PCLK divided by even number) */

/* This MCI driver assumes that MCLK_RW is CCLK/4 or slower. If block buffer underrun/overrun
/  occured due to any interrupt by higher priority process or slow external memory, increasing
/  N_BUF or decreasing MCLK_RW will solve it. */


/* ----- Port definitions ----- */
#define SOCKINS     !(FIO0PIN2 & 0x20)  /* Card detect switch */
#define SOCKWP      (FIO0PIN2 & 0x04)   /* Write protect switch */


/* ----- MMC/SDC command ----- */
#define CMD0    (0)             /* GO_IDLE_STATE */
#define CMD1    (1)             /* SEND_OP_COND (MMC) */
#define CMD2    (2)             /* ALL_SEND_CID */
#define CMD3    (3)             /* SEND_RELATIVE_ADDR */
#define ACMD6   (6|0x80)        /* SET_BUS_WIDTH (SDC) */
#define CMD7    (7)             /* SELECT_CARD */
#define CMD8    (8)             /* SEND_IF_COND */
#define CMD9    (9)             /* SEND_CSD */
#define CMD10   (10)            /* SEND_CID */
#define CMD12   (12)            /* STOP_TRANSMISSION */
#define CMD13   (13)            /* SEND_STATUS */
#define ACMD13  (13|0x80)       /* SD_STATUS (SDC) */
#define CMD16   (16)            /* SET_BLOCKLEN */
#define CMD17   (17)            /* READ_SINGLE_BLOCK */
#define CMD18   (18)            /* READ_MULTIPLE_BLOCK */
#define CMD23   (23)            /* SET_BLK_COUNT (MMC) */
#define ACMD23  (23|0x80)       /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24   (24)            /* WRITE_BLOCK */
#define CMD25   (25)            /* WRITE_MULTIPLE_BLOCK */
#define CMD32   (32)            /* ERASE_ER_BLK_START */
#define CMD33   (33)            /* ERASE_ER_BLK_END */
#define CMD38   (38)            /* ERASE */
#define ACMD41  (41|0x80)       /* SEND_OP_COND (SDC) */
#define CMD55   (55)            /* APP_CMD */

/* Card type flags (CardType) */
#define CT_MMC      0x01        /* MMC ver 3 */
#define CT_SD1      0x02        /* SD ver 1 */
#define CT_SD2      0x04        /* SD ver 2 */
#define CT_SDC      (CT_SD1|CT_SD2) /* SD */
#define CT_BLOCK    0x08        /* Block addressing */


/*--------------------------------------------------------------------------

   Module Private Functions

---------------------------------------------------------------------------*/

static volatile diskio_sta_t Stat = DISKIO_STA_NOINIT;  /* Disk status */

static unsigned short CardRCA;          /* Assigned RCA */
static unsigned char CardType,          /* Card type flag */
       CardInfo[16 + 16 + 4];   /* CSD(16), CID(16), OCR(4) */

static volatile unsigned char XferStat,             /* b3:MCI error, b2:Overrun, b1:Write, b0:Read */
       XferWc,          /* Write block counter */
       XferWp, XferRp;  /* R/W index of block FIFO */

static unsigned long DmaBuff[N_BUF][128]  __attribute__((section(".usbdata")));  /* Block transfer FIFO */
static unsigned long LinkList [N_BUF][4]  __attribute__((section(".usbdata")));  /* DMA link list */

void Isr_MCI(void) __attribute__((interrupt("IRQ")));
void Isr_GPDMA(void) __attribute__((interrupt("IRQ")));

/*-----------------------------------------------------------------------*/
/* Interrupt service routine for data transfer                           */
/*-----------------------------------------------------------------------*/

void Isr_MCI(void)
{
    unsigned long ms;
    unsigned char xs;

    ms = MCI_STATUS & 0x073A;   /* Clear MCI interrupt status */
    MCI_CLEAR = ms;

    xs = XferStat;

    if (ms & 0x400) {           /* A block transfer completed (DataBlockEnd) */
        if (xs & 1) {               /* In card read operation */
            if (ms & 0x100) {           /* When last block is received (DataEnd), */
                GPDMA_SOFT_BREQ = 0x10;    /* Pop off remaining data in the MCIFIFO */
            }

            unsigned char n = (XferWp + 1) % N_BUF;   /* Next write buffer */
            XferWp = n;

            if (n == XferRp) {
                xs |= 4;    /* Check block overrun */
            }
        }
        else {                      /* In card write operation */
            unsigned char n = (XferRp + 1) % N_BUF;   /* Next read buffer */
            XferRp = n;

            if (n == XferWp) {
                xs |= 4;    /* Check block underrun */
            }
        }
    }
    else {                  /* An MCI error occured (not DataBlockEnd) */
        xs |= 8;
    }

    XferStat = xs;

    VICVectAddr = 0;
}

void Isr_GPDMA(void)
{
    if (GPDMA_INT_TCSTAT & BIT0) {
        GPDMA_INT_TCCLR = 0x01;             /* Clear GPDMA interrupt flag */

        if (XferStat & 2) {
            /* In write operation */
            if (--XferWc == N_BUF) { /* Terminate LLI */
                LinkList[XferRp % N_BUF][2] = 0;
            }
        }
    }
    else {
        GPDMA_INT_TCCLR = 0x3;
    }

    VICVectAddr = 0;
}


/*-----------------------------------------------------------------------*/
/* Ready for data reception                                              */
/*-----------------------------------------------------------------------*/

/**
 * @param blks          Number of blocks to receive (1..127)
 * @param bs            Block size (64 or 512)
 * */
static void ready_reception(unsigned int blks, unsigned int bs)
{
    unsigned int n;
    unsigned long dma_ctrl;

    /* ------ Setting up GPDMA Ch-0 ------ */
    GPDMA_CH0_CFG &= 0xFFF80420;        /* Disable ch-0 */
    GPDMA_INT_TCCLR = 0x01;             /* Clear interrupt flag */
    dma_ctrl = 0x88492000 | (bs / 4);   /* 1_000_1_0_00_010_010_010_010_************ */

    /* Create link list */
    for (n = 0; n < N_BUF; n++) {
        LinkList[n][0] = (unsigned long)&MCI_FIFO;
        LinkList[n][1] = (unsigned long)DmaBuff[n];
        LinkList[n][2] = (unsigned long)LinkList[(n + 1) % N_BUF];
        LinkList[n][3] = dma_ctrl;
    }

    /* Load first LLI */
    GPDMA_CH0_SRC = LinkList[0][0];
    GPDMA_CH0_DEST = LinkList[0][1];
    GPDMA_CH0_LLI = LinkList[0][2];
    GPDMA_CH0_CTRL = LinkList[0][3];

    /* Enable ch-0 */
    GPDMA_CH0_CFG |= 0x19009;           /* *************_0_0_1_1_0_010_*_0000_*_0100_1 */

    /* --------- Setting up MCI ---------- */

    XferRp = 0;
    XferWp = 0;                 /* Block FIFO R/W index */
    XferStat = 1;                           /* Transfer status: MCI --> Memory */

    MCI_DATA_LEN = bs * blks;               /* Set total data length */
    MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.2);  /* Data timer: 0.2sec */
    MCI_CLEAR = 0x72A;                      /* Clear status flags */
    MCI_MASK0 = 0x72A;                      /* DataBlockEnd StartBitErr DataEnd RxOverrun DataTimeOut DataCrcFail */

    for (n = 0; bs > 1; bs >>= 1, n += 0x10);

    MCI_DATA_CTRL  = n | 0xB;               /* Start to receive data blocks */
}


/*-----------------------------------------------------------------------*/
/* Start to transmit a data block                                        */
/*-----------------------------------------------------------------------*/

#if _READONLY == 0
/*
 * @param blks   Number of blocks to be transmitted (1..127)
 * */
static void start_transmission(unsigned char blks)
{
    unsigned int n;
    unsigned long dma_ctrl;


    /* ------ Setting up GPDMA Ch-0 ------ */

    GPDMA_CH0_CFG &= 0xFFF80420;        /* Disable ch-0 */
    GPDMA_INT_TCCLR = 0x01;             /* Clear interrupt flag */
    dma_ctrl = 0x84492080;              /* 1_000_0_1_00_010_010_010_010_000010000000 */

    /* Create link list */
    for (n = 0; n < N_BUF; n++) {
        LinkList[n][0] = (unsigned long)DmaBuff[n];
        LinkList[n][1] = (unsigned long)&MCI_FIFO;
        LinkList[n][2] = (n == (unsigned int) (blks - 1)) ? 0 : (unsigned long)LinkList[(n + 1) % N_BUF];
        LinkList[n][3] = dma_ctrl;
    }

    /* Load first LLI */
    GPDMA_CH0_SRC = LinkList[0][0];
    GPDMA_CH0_DEST = LinkList[0][1];
    GPDMA_CH0_LLI = LinkList[0][2];
    GPDMA_CH0_CTRL = LinkList[0][3];

    /* Enable ch-0 */
    GPDMA_CH0_CFG |= 0x18901;           /* *************_0_0_1_1_0_001_*_0100_*_0000_1 */

    /* --------- Setting up MCI ---------- */

    XferRp = 0;                             /* Block FIFO read index */
    XferWc = blks;
    XferStat = 2;                           /* Transfer status: Memroy --> MCI */

    MCI_DATA_LEN = 512 * (blks + 1);        /* Set total data length */
    MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.5);  /* Data timer: 0.5sec */
    MCI_CLEAR = 0x51A;                      /* Clear status flags */
    MCI_MASK0 = 0x51A;                      /* DataBlockEnd DataEnd TxUnderrun DataTimeOut DataCrcFail */
    MCI_DATA_CTRL  = (9 << 4) | 0x9;        /* Start to transmit data blocks */
}
#endif  /* _READONLY */




/*-----------------------------------------------------------------------*/
/* Stop data transfer                                                    */
/*-----------------------------------------------------------------------*/

static void stop_transfer(void)
{
    MCI_MASK0 = 0;          /* Disable MCI interrupt */
    MCI_DATA_CTRL = 0;      /* Stop MCI data transfer */

    GPDMA_CH0_CFG &= 0xFFF80420;    /* Disable DMA ch-0 */
}




/*-----------------------------------------------------------------------*/
/* Power Control (Device dependent)                                      */
/*-----------------------------------------------------------------------*/

static int power_status(void)
{
    return (MCI_POWER & 3) ? 1 : 0;
}


static void power_on(void)
{
    /* Enable MCI and GPDMA clock */
    PCONP |= (3 << 28);

    /* Enable GPDMA controller with little-endian */
    GPDMA_CH0_CFG &= 0xFFF80000;    /* Disable DMA ch-0 */
    GPDMA_CONFIG = 0x01;

    /* Select PCLK for MCI, CCLK/2 = 36MHz */
    PCLKSEL1 = (PCLKSEL1 & 0xFCFFFFFF) | 0x02000000;

    //0.19 0.20 0.21 0.22
    PINMODE1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13));
    PINMODE1 |= (BIT7) | (BIT9) | (BIT11) | (BIT13);    // no resistors
    //2.11 2.12 2.13
    PINMODE4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27));
    PINMODE4 |= (BIT23) | (BIT25) | (BIT27);            // no resistors
    /* Attach MCI unit to I/O pad */
    PINSEL1 = (PINSEL1 & 0xFFFFC03F) | 0x00002A80;  /* MCICLK, MCICMD, MCIDATA0, MCIPWR */
#if USE_4BIT
    PINSEL4 = (PINSEL4 & 0xF03FFFFF) | 0x0A800000;  /* MCIDATA1-3 */
#endif
    MCI_MASK0 = 0;
    MCI_COMMAND = 0;
    MCI_DATA_CTRL = 0;

    // pin 0.21 high active
    SCS |= 0x08;

    /* Register interrupt handlers for MCI,DMA event */
    //RegisterIrq(MCI_INT, Isr_MCI, PRI_LOWEST-1);
    install_irq(MCI_INT, Isr_MCI, 5);

    //RegisterIrq(GPDMA_INT, Isr_GPDMA, PRI_LOWEST-1);
    install_irq(GPDMA_INT, Isr_GPDMA, 5);


    /* Power-on (VCC is always tied to the socket on this board) */
    MCI_POWER = 0x01;                   /* Power on */

    //for (Timer[0] = 10; Timer[0]; ) ; /* 10ms */
    xtimer_usleep(1000);

    MCI_POWER = 0x03;                   /* Enable signals */
}


static void power_off(void)
{
    MCI_MASK0 = 0;
    MCI_COMMAND = 0;
    MCI_DATA_CTRL = 0;

    MCI_POWER = 0;          /* Power-off */
    MCI_CLOCK = 0;

    // pin 0.21 low inactive
    SCS &= ~0x08;

    //0.21 MCI led Pin (turns sd card off, too)
    //0.19 0.20 0.21 0.22 with pull-down
    PINMODE1 |= (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13);
    PINSEL1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13));
    //  Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them)

    //2.11 2.12 2.13 with pull-down
    PINMODE4 |= (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27);
    PINSEL4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27));
    //  Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them)

    Stat |= DISKIO_STA_NOINIT;
}


/*-----------------------------------------------------------------------*/
/* Send a command packet to the card and receive a response              */
/*-----------------------------------------------------------------------*/

/*
 * @param idx       Command index (bit[5..0]), ACMD flag (bit7)
 * @param arg       Command argument
 * @param rt        Expected response type. None(0), Short(1) or Long(2)
 * @param *buff     Response return buffer
 * @return 1 when function succeeded otherwise returns 0
 * */
static int send_cmd(unsigned int idx, unsigned long arg, unsigned int rt, unsigned long *buff)
{
    unsigned int s, mc;

    if (idx & 0x80) {               /* Send a CMD55 prior to the specified command if it is ACMD class */
        if (!send_cmd(CMD55, (unsigned long)CardRCA << 16, 1, buff) /* When CMD55 is faild, */
           || !(buff[0] & 0x00000020)) {
            return 0;    /* exit with error */
        }<commit_msg>cpu/lpc2387: Add missing assert(buff != NULL)<commit_after>/*-----------------------------------------------------------------------*/
/* MMCv3/SDv1/SDv2 (in native mode via MCI) control module (C)ChaN, 2010 */
/*-----------------------------------------------------------------------*/
/* This program is opened under license policy of following trems.
/
/  Copyright (C) 2010, ChaN, all right reserved.
/
/ * This program is a free software and there is NO WARRANTY.
/ * No restriction on use. You can use, modify and redistribute it for
/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
/ * Redistributions of source code must retain the above copyright notice.
/
/---------------------------------------------------------------------------*/

#include <string.h>
#include "lpc23xx.h"
#include "VIC.h"
#include "xtimer.h"
#include "diskio.h"

#define ENABLE_DEBUG    (0)
#include "debug.h"

/* --- MCI configurations --- */
#define N_BUF       4           /* Block transfer FIFO depth (>= 2) */
#define USE_4BIT    1           /* Use wide bus mode if SDC is detected */
#define PCLK        36000000UL  /* PCLK supplied to MCI module */
#define MCLK_ID     400000UL    /* MCICLK for ID state (100k-400k) */
#define MCLK_RW     18000000UL  /* MCICLK for data transfer (PCLK divided by even number) */

/* This MCI driver assumes that MCLK_RW is CCLK/4 or slower. If block buffer underrun/overrun
/  occured due to any interrupt by higher priority process or slow external memory, increasing
/  N_BUF or decreasing MCLK_RW will solve it. */


/* ----- Port definitions ----- */
#define SOCKINS     !(FIO0PIN2 & 0x20)  /* Card detect switch */
#define SOCKWP      (FIO0PIN2 & 0x04)   /* Write protect switch */


/* ----- MMC/SDC command ----- */
#define CMD0    (0)             /* GO_IDLE_STATE */
#define CMD1    (1)             /* SEND_OP_COND (MMC) */
#define CMD2    (2)             /* ALL_SEND_CID */
#define CMD3    (3)             /* SEND_RELATIVE_ADDR */
#define ACMD6   (6|0x80)        /* SET_BUS_WIDTH (SDC) */
#define CMD7    (7)             /* SELECT_CARD */
#define CMD8    (8)             /* SEND_IF_COND */
#define CMD9    (9)             /* SEND_CSD */
#define CMD10   (10)            /* SEND_CID */
#define CMD12   (12)            /* STOP_TRANSMISSION */
#define CMD13   (13)            /* SEND_STATUS */
#define ACMD13  (13|0x80)       /* SD_STATUS (SDC) */
#define CMD16   (16)            /* SET_BLOCKLEN */
#define CMD17   (17)            /* READ_SINGLE_BLOCK */
#define CMD18   (18)            /* READ_MULTIPLE_BLOCK */
#define CMD23   (23)            /* SET_BLK_COUNT (MMC) */
#define ACMD23  (23|0x80)       /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24   (24)            /* WRITE_BLOCK */
#define CMD25   (25)            /* WRITE_MULTIPLE_BLOCK */
#define CMD32   (32)            /* ERASE_ER_BLK_START */
#define CMD33   (33)            /* ERASE_ER_BLK_END */
#define CMD38   (38)            /* ERASE */
#define ACMD41  (41|0x80)       /* SEND_OP_COND (SDC) */
#define CMD55   (55)            /* APP_CMD */

/* Card type flags (CardType) */
#define CT_MMC      0x01        /* MMC ver 3 */
#define CT_SD1      0x02        /* SD ver 1 */
#define CT_SD2      0x04        /* SD ver 2 */
#define CT_SDC      (CT_SD1|CT_SD2) /* SD */
#define CT_BLOCK    0x08        /* Block addressing */


/*--------------------------------------------------------------------------

   Module Private Functions

---------------------------------------------------------------------------*/

static volatile diskio_sta_t Stat = DISKIO_STA_NOINIT;  /* Disk status */

static unsigned short CardRCA;          /* Assigned RCA */
static unsigned char CardType,          /* Card type flag */
       CardInfo[16 + 16 + 4];   /* CSD(16), CID(16), OCR(4) */

static volatile unsigned char XferStat,             /* b3:MCI error, b2:Overrun, b1:Write, b0:Read */
       XferWc,          /* Write block counter */
       XferWp, XferRp;  /* R/W index of block FIFO */

static unsigned long DmaBuff[N_BUF][128]  __attribute__((section(".usbdata")));  /* Block transfer FIFO */
static unsigned long LinkList [N_BUF][4]  __attribute__((section(".usbdata")));  /* DMA link list */

void Isr_MCI(void) __attribute__((interrupt("IRQ")));
void Isr_GPDMA(void) __attribute__((interrupt("IRQ")));

/*-----------------------------------------------------------------------*/
/* Interrupt service routine for data transfer                           */
/*-----------------------------------------------------------------------*/

void Isr_MCI(void)
{
    unsigned long ms;
    unsigned char xs;

    ms = MCI_STATUS & 0x073A;   /* Clear MCI interrupt status */
    MCI_CLEAR = ms;

    xs = XferStat;

    if (ms & 0x400) {           /* A block transfer completed (DataBlockEnd) */
        if (xs & 1) {               /* In card read operation */
            if (ms & 0x100) {           /* When last block is received (DataEnd), */
                GPDMA_SOFT_BREQ = 0x10;    /* Pop off remaining data in the MCIFIFO */
            }

            unsigned char n = (XferWp + 1) % N_BUF;   /* Next write buffer */
            XferWp = n;

            if (n == XferRp) {
                xs |= 4;    /* Check block overrun */
            }
        }
        else {                      /* In card write operation */
            unsigned char n = (XferRp + 1) % N_BUF;   /* Next read buffer */
            XferRp = n;

            if (n == XferWp) {
                xs |= 4;    /* Check block underrun */
            }
        }
    }
    else {                  /* An MCI error occured (not DataBlockEnd) */
        xs |= 8;
    }

    XferStat = xs;

    VICVectAddr = 0;
}

void Isr_GPDMA(void)
{
    if (GPDMA_INT_TCSTAT & BIT0) {
        GPDMA_INT_TCCLR = 0x01;             /* Clear GPDMA interrupt flag */

        if (XferStat & 2) {
            /* In write operation */
            if (--XferWc == N_BUF) { /* Terminate LLI */
                LinkList[XferRp % N_BUF][2] = 0;
            }
        }
    }
    else {
        GPDMA_INT_TCCLR = 0x3;
    }

    VICVectAddr = 0;
}


/*-----------------------------------------------------------------------*/
/* Ready for data reception                                              */
/*-----------------------------------------------------------------------*/

/**
 * @param blks          Number of blocks to receive (1..127)
 * @param bs            Block size (64 or 512)
 * */
static void ready_reception(unsigned int blks, unsigned int bs)
{
    unsigned int n;
    unsigned long dma_ctrl;

    /* ------ Setting up GPDMA Ch-0 ------ */
    GPDMA_CH0_CFG &= 0xFFF80420;        /* Disable ch-0 */
    GPDMA_INT_TCCLR = 0x01;             /* Clear interrupt flag */
    dma_ctrl = 0x88492000 | (bs / 4);   /* 1_000_1_0_00_010_010_010_010_************ */

    /* Create link list */
    for (n = 0; n < N_BUF; n++) {
        LinkList[n][0] = (unsigned long)&MCI_FIFO;
        LinkList[n][1] = (unsigned long)DmaBuff[n];
        LinkList[n][2] = (unsigned long)LinkList[(n + 1) % N_BUF];
        LinkList[n][3] = dma_ctrl;
    }

    /* Load first LLI */
    GPDMA_CH0_SRC = LinkList[0][0];
    GPDMA_CH0_DEST = LinkList[0][1];
    GPDMA_CH0_LLI = LinkList[0][2];
    GPDMA_CH0_CTRL = LinkList[0][3];

    /* Enable ch-0 */
    GPDMA_CH0_CFG |= 0x19009;           /* *************_0_0_1_1_0_010_*_0000_*_0100_1 */

    /* --------- Setting up MCI ---------- */

    XferRp = 0;
    XferWp = 0;                 /* Block FIFO R/W index */
    XferStat = 1;                           /* Transfer status: MCI --> Memory */

    MCI_DATA_LEN = bs * blks;               /* Set total data length */
    MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.2);  /* Data timer: 0.2sec */
    MCI_CLEAR = 0x72A;                      /* Clear status flags */
    MCI_MASK0 = 0x72A;                      /* DataBlockEnd StartBitErr DataEnd RxOverrun DataTimeOut DataCrcFail */

    for (n = 0; bs > 1; bs >>= 1, n += 0x10);

    MCI_DATA_CTRL  = n | 0xB;               /* Start to receive data blocks */
}


/*-----------------------------------------------------------------------*/
/* Start to transmit a data block                                        */
/*-----------------------------------------------------------------------*/

#if _READONLY == 0
/*
 * @param blks   Number of blocks to be transmitted (1..127)
 * */
static void start_transmission(unsigned char blks)
{
    unsigned int n;
    unsigned long dma_ctrl;


    /* ------ Setting up GPDMA Ch-0 ------ */

    GPDMA_CH0_CFG &= 0xFFF80420;        /* Disable ch-0 */
    GPDMA_INT_TCCLR = 0x01;             /* Clear interrupt flag */
    dma_ctrl = 0x84492080;              /* 1_000_0_1_00_010_010_010_010_000010000000 */

    /* Create link list */
    for (n = 0; n < N_BUF; n++) {
        LinkList[n][0] = (unsigned long)DmaBuff[n];
        LinkList[n][1] = (unsigned long)&MCI_FIFO;
        LinkList[n][2] = (n == (unsigned int) (blks - 1)) ? 0 : (unsigned long)LinkList[(n + 1) % N_BUF];
        LinkList[n][3] = dma_ctrl;
    }

    /* Load first LLI */
    GPDMA_CH0_SRC = LinkList[0][0];
    GPDMA_CH0_DEST = LinkList[0][1];
    GPDMA_CH0_LLI = LinkList[0][2];
    GPDMA_CH0_CTRL = LinkList[0][3];

    /* Enable ch-0 */
    GPDMA_CH0_CFG |= 0x18901;           /* *************_0_0_1_1_0_001_*_0100_*_0000_1 */

    /* --------- Setting up MCI ---------- */

    XferRp = 0;                             /* Block FIFO read index */
    XferWc = blks;
    XferStat = 2;                           /* Transfer status: Memroy --> MCI */

    MCI_DATA_LEN = 512 * (blks + 1);        /* Set total data length */
    MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.5);  /* Data timer: 0.5sec */
    MCI_CLEAR = 0x51A;                      /* Clear status flags */
    MCI_MASK0 = 0x51A;                      /* DataBlockEnd DataEnd TxUnderrun DataTimeOut DataCrcFail */
    MCI_DATA_CTRL  = (9 << 4) | 0x9;        /* Start to transmit data blocks */
}
#endif  /* _READONLY */




/*-----------------------------------------------------------------------*/
/* Stop data transfer                                                    */
/*-----------------------------------------------------------------------*/

static void stop_transfer(void)
{
    MCI_MASK0 = 0;          /* Disable MCI interrupt */
    MCI_DATA_CTRL = 0;      /* Stop MCI data transfer */

    GPDMA_CH0_CFG &= 0xFFF80420;    /* Disable DMA ch-0 */
}




/*-----------------------------------------------------------------------*/
/* Power Control (Device dependent)                                      */
/*-----------------------------------------------------------------------*/

static int power_status(void)
{
    return (MCI_POWER & 3) ? 1 : 0;
}


static void power_on(void)
{
    /* Enable MCI and GPDMA clock */
    PCONP |= (3 << 28);

    /* Enable GPDMA controller with little-endian */
    GPDMA_CH0_CFG &= 0xFFF80000;    /* Disable DMA ch-0 */
    GPDMA_CONFIG = 0x01;

    /* Select PCLK for MCI, CCLK/2 = 36MHz */
    PCLKSEL1 = (PCLKSEL1 & 0xFCFFFFFF) | 0x02000000;

    //0.19 0.20 0.21 0.22
    PINMODE1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13));
    PINMODE1 |= (BIT7) | (BIT9) | (BIT11) | (BIT13);    // no resistors
    //2.11 2.12 2.13
    PINMODE4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27));
    PINMODE4 |= (BIT23) | (BIT25) | (BIT27);            // no resistors
    /* Attach MCI unit to I/O pad */
    PINSEL1 = (PINSEL1 & 0xFFFFC03F) | 0x00002A80;  /* MCICLK, MCICMD, MCIDATA0, MCIPWR */
#if USE_4BIT
    PINSEL4 = (PINSEL4 & 0xF03FFFFF) | 0x0A800000;  /* MCIDATA1-3 */
#endif
    MCI_MASK0 = 0;
    MCI_COMMAND = 0;
    MCI_DATA_CTRL = 0;

    // pin 0.21 high active
    SCS |= 0x08;

    /* Register interrupt handlers for MCI,DMA event */
    //RegisterIrq(MCI_INT, Isr_MCI, PRI_LOWEST-1);
    install_irq(MCI_INT, Isr_MCI, 5);

    //RegisterIrq(GPDMA_INT, Isr_GPDMA, PRI_LOWEST-1);
    install_irq(GPDMA_INT, Isr_GPDMA, 5);


    /* Power-on (VCC is always tied to the socket on this board) */
    MCI_POWER = 0x01;                   /* Power on */

    //for (Timer[0] = 10; Timer[0]; ) ; /* 10ms */
    xtimer_usleep(1000);

    MCI_POWER = 0x03;                   /* Enable signals */
}


static void power_off(void)
{
    MCI_MASK0 = 0;
    MCI_COMMAND = 0;
    MCI_DATA_CTRL = 0;

    MCI_POWER = 0;          /* Power-off */
    MCI_CLOCK = 0;

    // pin 0.21 low inactive
    SCS &= ~0x08;

    //0.21 MCI led Pin (turns sd card off, too)
    //0.19 0.20 0.21 0.22 with pull-down
    PINMODE1 |= (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13);
    PINSEL1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13));
    //  Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them)

    //2.11 2.12 2.13 with pull-down
    PINMODE4 |= (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27);
    PINSEL4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27));
    //  Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them)

    Stat |= DISKIO_STA_NOINIT;
}


/*-----------------------------------------------------------------------*/
/* Send a command packet to the card and receive a response              */
/*-----------------------------------------------------------------------*/

/*
 * @param idx       Command index (bit[5..0]), ACMD flag (bit7)
 * @param arg       Command argument
 * @param rt        Expected response type. None(0), Short(1) or Long(2)
 * @param *buff     Response return buffer
 * @return 1 when function succeeded otherwise returns 0
 * */
static int send_cmd(unsigned int idx, unsigned long arg, unsigned int rt, unsigned long *buff)
{
    unsigned int s, mc;

    assert(buff != NULL);

    if (idx & 0x80) {               /* Send a CMD55 prior to the specified command if it is ACMD class */
        if (!send_cmd(CMD55, (unsigned long)CardRCA << 16, 1, buff) /* When CMD55 is faild, */
           || !(buff[0] & 0x00000020)) {
            return 0;    /* exit with error */
        }
{'fraction_non_alphanumeric': 0.21427809577985565, 'fraction_numerical': 0.05276069257297259, 'mean_word_length': 1.4628316259521934, 'pattern_counts': {'":': 0, '<': 21, '<?xml version=': 0, '>': 17, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 2, 'word_list_counts': {'cursed_substrings.json': 16, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3370311', 'n_tokens_mistral': 10036, 'n_tokens_neox': 8980, 'n_words': 2428}