<commit_before>This application note explains how to achieve actual 9 bit data communication and mark/space parity bit emulation.

##9-bit data width communication

In serial port communication, the uart frame consist of a start bit, data bits and stop bits. Typically the length of data bits varies from 5 to 8 bits with most of the application using 8-N-1 configuration. Some custom protocols and multidrop bus (MDB) uses and additional bit to carry extra information. This additional bit appears after last data bit but before stop bit in given uart frame.

The MDB uses this additional bit to differentiate between address and data byte. Custom protocols uses this bit to indicate that the given data byte is actual data or control information. Some rare custom protocols defines that this bit must always be 0 or 1 in uart frame, some define a particular sequence for example; in the transmitted packet, 3rd uart frame must have this bit set to 1 with all other frames having this bit set to 0.

There are three ways in which this additional bit can be added in transmitted uart frame:

- *Use uart hardware* that supports 9-bit data width configuration for example; OX16C950 for host computer and ATmega328, MAX3109, dsPIC33E families microcontroller from microchip for embedded system etc. Most of the host computer hardware, driver and operating system does not support 9-bit mode and therefore custom drivers and libraries have to be developed and used. UART hardware itself may be little more expensive also.

  This method has some variance and implementation specific complexity. Some hardware provide 9 bit wide FIFO for ex; dsPIC30F3012, while some uses a bit in another register as 9th data bit for ex; ATmega328. This increases the need to complete things in a timely manner and a more complicated driver etc. Most hardware does not support 9 bit data with parity bit also available.

- *Emulate 9th bit* while using the standard supported uart configuration on available hardware and software resources. This involves enabling the parity bit in uart frame and explicitly dynamically setting this bit. If the 9th bit is to be set to 0, count the number of 1's from 0th to 8th data bit. If this number is even then configure the uart controller for 8-E-1 communication otherwise 8-O-1 (8 data bits, odd parity and 1 stop bit). This has to be done for every uart frame to be transmitted.
  
  Similarly, If the 9th bit is to be set to 1, count the number of 1's from 0th to 8th data bit. If this number is even then configure the uart controller for 8-O-1 communication otherwise 8-E-1. An important point to note is that the parity setting is common for both tx and rx part of uart hardware and therefore we can not simultaneously transmit and receive data. For a master/slave configuration, however this is not an issue.
  
  Special attention must be paid to the timing as if a byte is transmitted or received while the parity setting is changed, inconsistent result may be observed. Further this trick may not be applied if parity bit is also used in addition to 9 bit data.
  
- *Bit bang the GPIO* if available. This is mainly applicable to embedded system microcontroller where firmware manually constructs uart frame and send it over the same GPIO pin physically.


##Emulating Mark and Space parity bit

In serial port communication, the uart frame may use an additional bit known as parity bit to detect corrupted data byte. This bit is placed between last data bit and stop bit. There are 5 types of parity namely; even, odd, mark, space and no parity. Mark and space parity is supported by most available hardware however some tweaks may be needed in case the underlying operating system, driver or system library does not provide enough support for mark and space parities.

If no parity is used, uart frame contains only data bits, start and stop bit(s). If even parity is used, the parity bit is set to 0 if there is an even number of 1's in in data bits. If odd parity is used, the parity bit is set to 0 if there is an odd number of 1's in the data bits. If mark parity is used, the parity bit is always 1 irrespective of the data bits contents. If space parity is used, the parity bit is always 0 irrespective of the data bits contents.

The emulation trick described above can also be used to emulate mark and space parity if the underlying driver or software does not provide explicit support for it.
<commit_msg>add timing caveats in 9 bit emulation mode app note<commit_after>This application note explains how to achieve actual 9 bit data communication and mark/space parity bit emulation.

##9-bit data width communication

In serial port communication, the uart frame consist of a start bit, data bits and stop bits. Typically the length of data bits varies from 5 to 8 bits with most of the application using 8-N-1 configuration. Some custom protocols and multidrop bus (MDB) uses and additional bit to carry extra information. This additional bit appears after last data bit but before stop bit in given uart frame.

The MDB uses this additional bit to differentiate between address and data byte. Custom protocols uses this bit to indicate that the given data byte is actual data or control information. Some rare custom protocols defines that this bit must always be 0 or 1 in uart frame, some define a particular sequence for example; in the transmitted packet, 3rd uart frame must have this bit set to 1 with all other frames having this bit set to 0. Another such sequence can be 9th bit is 1 in 1st frame to represent address, than all other frmaes will have this bit as 0 and then the last frame will have this bit again as 1 to indicate end of message.

There are three ways in which this additional bit can be added in transmitted uart frame:

- *Use uart hardware* that supports 9-bit data width configuration for example; OX16C950 for host computer and ATmega328, MAX3109, dsPIC33E families microcontroller from microchip for embedded system etc. Most of the host computer hardware, driver and operating system does not support 9-bit mode and therefore custom drivers and libraries have to be developed and used. UART hardware itself may be little more expensive also.

  This method has some variance and implementation specific complexity. Some hardware provide 9 bit wide FIFO for ex; dsPIC30F3012, while some uses a bit in another register as 9th data bit for ex; ATmega328. This increases the need to complete things in a timely manner and a more complicated driver etc. Most hardware does not support 9 bit data with parity bit also available.

- *Emulate 9th bit* while using the standard supported uart configuration on available hardware and software resources. This involves enabling the parity bit in uart frame and explicitly dynamically setting this bit. If the 9th bit is to be set to 0, count the number of 1's from 0th to 8th data bit. If this number is even then configure the uart controller for 8-E-1 communication otherwise 8-O-1 (8 data bits, odd parity and 1 stop bit). This has to be done for every uart frame to be transmitted.
  
  Similarly, If the 9th bit is to be set to 1, count the number of 1's from 0th to 8th data bit. If this number is even then configure the uart controller for 8-O-1 communication otherwise 8-E-1. An important point to note is that the parity setting is common for both tx and rx part of uart hardware and therefore we can not simultaneously transmit and receive data. For a master/slave configuration, however this is not an issue.
  
  Special attention must be paid to the timing as if a byte is transmitted or received while the parity setting is changed, inconsistent result may be observed. The tx buffer must be emptied physically  by uart hardware for each byte to make sure that desired parity settings come in effect as set for each byte i.e. setting parity, uart frame construction and physically transmitting the frame must be an atomic operation. The protocol itself may have defined a time window and we need to make sure that it is met. Further this trick may not be applied if parity bit is also used in addition to 9 bit data.
  
- *Bit bang the GPIO* if available. This is mainly applicable to embedded system microcontroller where firmware manually constructs uart frame and send it over the same GPIO pin physically.


##Emulating Mark and Space parity bit

In serial port communication, the uart frame may use an additional bit known as parity bit to detect corrupted data byte. This bit is placed between last data bit and stop bit. There are 5 types of parity namely; even, odd, mark, space and no parity. Mark and space parity is supported by most available hardware however some tweaks may be needed in case the underlying operating system, driver or system library does not provide enough support for mark and space parities.

If no parity is used, uart frame contains only data bits, start and stop bit(s). If even parity is used, the parity bit is set to 0 if there is an even number of 1's in in data bits. If odd parity is used, the parity bit is set to 0 if there is an odd number of 1's in the data bits. If mark parity is used, the parity bit is always 1 irrespective of the data bits contents. If space parity is used, the parity bit is always 0 irrespective of the data bits contents.

The emulation trick described above can also be used to emulate mark and space parity if the underlying driver or software does not provide explicit support for it.

{'fraction_non_alphanumeric': 0.02391487568478719, 'fraction_numerical': 0.014959966287399916, 'mean_word_length': 4.207350521119035, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4907373', 'n_tokens_mistral': 2318, 'n_tokens_neox': 2102, 'n_words': 1644}