<commit_before>========================================================================================================================
XC2C32A (JED file bit ordering)
========================================================================================================================

CONVENTIONS
-------------------------
Leftmost bit in a row is MSB (N), rightmost is LSB (0)

ZIA
-------------------------
320 bits starting at fuse # 0 (FB0), 6128 (FB1)
40 rows, 8 bits per row
Each row is an 65:1 mux corresponding to one output from the global routing matrix.
The mux is a two level tree.
The first level consists of six 11:1 mask-programmed muxes (with a different coding for each row), reducing the 65
signals on the metal 4 bus down to six. The second level is an 8:1 one-hot bitstream-programmed mux, which selects the
final routing output as either a constant value or one of the six mask mux outputs.

Mask ROM mux inputs:
	Bit 5:
		FB1 macrocell 15 (row 7, 12, 30, 37)
		FB1 macrocell 14 (row 10, 18, 25, 38)
		FB1 macrocell 13 (row 6, 13, 26)
		FB1 macrocell 12 (row 1, 14, 28, 33)
		FB1 macrocell 11 (row 2, 16, 22, 34)
		FB1 macrocell 10 (row 4, 11, 32)
		FB1 macrocell 9 (row 0, 20, 29, 39)
		FB1 macrocell 8 (row 8, 17, 27)
		FB1 macrocell 7 (row 5, 15, 31, 36)
		FB1 macrocell 6 (row 3, 19, 24)
		FB1 macrocell 5 (row 9, 21, 23, 35)
	Bit 4:
		FB1 macrocell 4 (row 2, 18, 23)
		FB1 macrocell 3 (row 6, 21, 29, 36)
		FB1 macrocell 2 (row 9, 17, 24, 37)
		FB1 macrocell 1 (row 5, 12, 25, 39)
		FB1 macrocell 0 (row 10, 13, 27, 33)
		FB0 macrocell 15 (row 1, 15, 22)
		FB0 macrocell 14 (row 3, 11, 31)
		FB0 macrocell 13 (row 0, 19, 28, 38)
		FB0 macrocell 12 (row 7, 16, 26)
		FB0 macrocell 11 (row 4, 14, 30, 35)
		FB0 macrocell 10 (row 8, 20, 32, 34)
	Bit 3:
	Bit 2:
	Bit 1:

Bitstream mux inputs:
Inputs are active-low except for bit 7, which is active high.
This is done so that the all-ones reset state is a constant, low-power value.
	7    	Constant 1 (active HIGH)
	6    	Constant 0
	5:0		Mask-programmed mux outputs

PLA AND
-------------------------
4480 bits starting at fuse # 320 (FB0), 6448 (FB1)
56 rows, 80 bits per row
Each row configures inputs to an 80-input AND gate. 0 selects the signal, 1 selects a constant one.
Each column corresponds to one ZIA output.
First row is product term #0, second row product term #1, etc

Bit ordering for each row:
	0		ZIA row #0 non-inverted output
	1		ZIA row #0 inverted output
	2		ZIA row #1 non-inverted output
	3		ZIA row #1 inverted output
	...

PLA OR
-------------------------
896 bits starting at fuse # 4800 (FB0), 10928 (FB1)
56 rows, 16 bits per row
Each column configures inputs to a 16-input OR gate. 0 selects the signal, 1 selects a constant zero.
Each row corresponds to one product term.

Bit ordering for columns:
	0		Macrocell 15
	1		Macrocell 14
	...
	14		Macrocell 1
	15		Macrocell 0

Bit ordering for rows
	0		Product term 0
	1		Product term 1
	...
	54		Product term 54
	55		Product term 55

Macrocells
-------------------------
432 bits starting at fuse # 5696 (FB0), 11824 (FB2)
16 rows, 27 bits per row
	26		Selects input to the "11" clock source mux
				0 = Product Term Clock
				1 = Control Term Clock
	25		1 if FF is falling edge triggered, 0 if rising
	24:23	Clock source for the FF
				00 = GCK0
				01 = GCK1
				10 = GCK2
				11 = Product Term C or Control Term Clock
	22		1 if FF is DDR clocked, 0 if SDR
	21:20	Reset source for the FF
				00 = Product Term A
				01 = Global Set/Reset
				10 = Control Term Reset
				11 = disabled
	19:18	Set source for the FF
				00 = Product Term A
				01 = Global Set/Reset
				10 = Control Term Set
				11 = disabled
	17:16	Flipflop mode
				00 = D flipflop
				01 = latch
				10 = T flipflop
				11 = D flipflop with clock enable
	15:14	Input mux of some sort
				00 = IBUF driving ZIA
				11 = unused pin
				Other values unknown
	13:12	"FB val" - specifies output from macrocell to the ZIA (conjecture)
				Most likely one-hot to select either FF or XOR output
	11		Selects input to the flipflop<commit_msg>Added more coding to fbval and ZIA routing<commit_after>========================================================================================================================
XC2C32A (JED file bit ordering)
========================================================================================================================

CONVENTIONS
-------------------------
Leftmost bit in a row is MSB (N), rightmost is LSB (0)

ZIA
-------------------------
320 bits starting at fuse # 0 (FB0), 6128 (FB1)
40 rows, 8 bits per row
Each row is an 65:1 mux corresponding to one output from the global routing matrix.
The mux is a two level tree.
The first level consists of six 11:1 mask-programmed muxes (with a different coding for each row), reducing the 65
signals on the metal 4 bus down to six. The second level is an 8:1 one-hot bitstream-programmed mux, which selects the
final routing output as either a constant value or one of the six mask mux outputs.

Mask ROM mux inputs:
	Bit 5 (leftmost group on M4 bus):
		FB1 macrocell 15 (row 7, 12, 30, 37)
		FB1 macrocell 14 (row 10, 18, 25, 38)
		FB1 macrocell 13 (row 6, 13, 26)
		FB1 macrocell 12 (row 1, 14, 28, 33)
		FB1 macrocell 11 (row 2, 16, 22, 34)
		FB1 macrocell 10 (row 4, 11, 32)
		FB1 macrocell 9 (row 0, 20, 29, 39)
		FB1 macrocell 8 (row 8, 17, 27)
		FB1 macrocell 7 (row 5, 15, 31, 36)
		FB1 macrocell 6 (row 3, 19, 24)
		FB1 macrocell 5 (row 9, 21, 23, 35)
	Bit 4:
		FB1 macrocell 4 (row 2, 18, 23)
		FB1 macrocell 3 (row 6, 21, 29, 36)
		FB1 macrocell 2 (row 9, 17, 24, 37)
		FB1 macrocell 1 (row 5, 12, 25, 39)
		FB1 macrocell 0 (row 10, 13, 27, 33)
		FB0 macrocell 15 (row 1, 15, 22)
		FB0 macrocell 14 (row 3, 11, 31)
		FB0 macrocell 13 (row 0, 19, 28, 38)
		FB0 macrocell 12 (row 7, 16, 26)
		FB0 macrocell 11 (row 4, 14, 30, 35)
		FB0 macrocell 10 (row 8, 20, 32, 34)
	Bit 3:
		FB0 macrocell 9 (row 3, 13, 29, 34)
		FB0 macrocell 8 (row 1, 17, 32)
		FB0 macrocell 7 (row 5, 20, 28, 35)
		FB0 macrocell 6 (row 8, 16, 23, 36)
		FB0 macrocell 5 (row 4, 21, 24, 38)
		FB0 macrocell 4 (row 9, 12, 26, 33)
		FB0 macrocell 3 (row 10, 14, 22)
		FB0 macrocell 2 (row 2, 11, 30, 39)
		FB0 macrocell 1 (row 0, 18, 27, 37)
		FB0 macrocell 0 (row 6, 15, 25)
		FB1 pad 15 (row 7, 19, 31)
	Bit 2:
		FB1 pad 14 (row )
		FB1 pad 13 (row )
		FB1 pad 12 (row )
		FB1 pad 11 (row )
		FB1 pad 10 (row )
		FB1 pad 9 (row )
		FB1 pad 8 (row )
		FB1 pad 7 (row )
		FB1 pad 6 (row )
		FB1 pad 5 (row )
		FB1 pad 4 (row )
	Bit 1:
		FB1 pad 3 (row )
		FB1 pad 2 (row )
		FB1 pad 1 (row )
		FB1 pad 0 (row )
		Dedicated input (row )
		FB0 pad 15 (row )
		FB0 pad 14 (row )
		FB0 pad 13 (row )
		FB0 pad 12 (row )
		FB0 pad 11 (row )
		FB0 pad 10 (row )
	Bit 0 (rightmost group on M4 bus, only 10 signals vs 11):
		FB0 pad 9 (row )
		FB0 pad 8 (row )
		FB0 pad 7 (row )
		FB0 pad 6 (row )
		FB0 pad 5 (row )
		FB0 pad 4 (row )
		FB0 pad 3 (row )
		FB0 pad 2 (row )
		FB0 pad 1 (row )
		FB0 pad 0 (row )

Bitstream mux inputs:
Inputs are active-low except for bit 7, which is active high.
This is done so that the all-ones reset state is a constant, low-power value.
	7    	Constant 1 (active HIGH)
	6    	Constant 0
	5:0		Mask-programmed mux outputs

PLA AND
-------------------------
4480 bits starting at fuse # 320 (FB0), 6448 (FB1)
56 rows, 80 bits per row
Each row configures inputs to an 80-input AND gate. 0 selects the signal, 1 selects a constant one.
Each column corresponds to one ZIA output.
First row is product term #0, second row product term #1, etc

Bit ordering for each row:
	0		ZIA row #0 non-inverted output
	1		ZIA row #0 inverted output
	2		ZIA row #1 non-inverted output
	3		ZIA row #1 inverted output
	...

PLA OR
-------------------------
896 bits starting at fuse # 4800 (FB0), 10928 (FB1)
56 rows, 16 bits per row
Each column configures inputs to a 16-input OR gate. 0 selects the signal, 1 selects a constant zero.
Each row corresponds to one product term.

Bit ordering for columns:
	0		Macrocell 15
	1		Macrocell 14
	...
	14		Macrocell 1
	15		Macrocell 0

Bit ordering for rows
	0		Product term 0
	1		Product term 1
	...
	54		Product term 54
	55		Product term 55

Macrocells
-------------------------
432 bits starting at fuse # 5696 (FB0), 11824 (FB2)
16 rows, 27 bits per row
	26		Selects input to the "11" clock source mux
				0 = Product Term Clock
				1 = Control Term Clock
	25		1 if FF is falling edge triggered, 0 if rising
	24:23	Clock source for the FF
				00 = GCK0
				01 = GCK1
				10 = GCK2
				11 = Product Term C or Control Term Clock
	22		1 if FF is DDR clocked, 0 if SDR
	21:20	Reset source for the FF
				00 = Product Term A
				01 = Global Set/Reset
				10 = Control Term Reset
				11 = disabled
	19:18	Set source for the FF
				00 = Product Term A
				01 = Global Set/Reset
				10 = Control Term Set
				11 = disabled
	17:16	Flipflop mode
				00 = D flipflop
				01 = latch
				10 = T flipflop
				11 = D flipflop with clock enable
	15:14	Input mux of some sort
				00 = IBUF driving ZIA
				11 = unused pin
				Other values unknown
	13:12	"FB val" - specifies output from macrocell to the ZIA
				00 = unknown (not observed)
				01 = unknown (not observed)
				10 = flipflop feeding into ZIA
				11 = ZIA output not used
	11		Selects input to the flipflop
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