<commit_before>"""HDL HDLRegister descriptors and actions."""


class HDLRegisterField(object):
    """Bitfield inside a register."""

    def __init__(self, name, reg_slice, permissions, properties=None):
        """Initialize."""
        self.name = name

        _slice = self._validate_slice(reg_slice)

        self.reg_slice = _slice
        self.permissions = permissions
        if properties is not None:
            self.properties = dict(properties)
        else:
            self.properties = {}

    def _validate_slice(self, reg_slice):
        if isinstance(reg_slice, (tuple, list)):
            if len(reg_slice) > 2:
                raise ValueError('invalid range')
            return reg_slice
        elif isinstance(reg_slice, int):
            return [reg_slice]
        else:
            raise TypeError('invalid type '
                            'for slice: "{}"'.format(type(reg_slice)))

    def add_properties(self, **kwargs):
        """Add a property."""
        self.properties.update(kwargs)

    def get_range(self):
        """Get which bits are claimed by this field."""
        if len(self.reg_slice) > 1:
            return range(self.reg_slice[1], self.reg_slice[0]+1)
        else:
            return self.reg_slice

    @staticmethod
    def dumps_slice(reg_slice):
        """Print formatted slice."""
        if len(reg_slice) == 2:
            return '[{}..{}]'.format(*reg_slice)
        else:
            return '[{}]'.format(reg_slice[0])


class HDLRegister(object):
    """Register."""

    def __init__(self, name, size, addr):
        """Initialize."""
        self.name = name
        self.size = size
        self.addr = addr
        self.fields = []
        self.properties = {}

    def get_used_bits(self):
        """Get which bits are already claimed by fields."""
        bits = []
        for field in self.fields:
            bits.extend(field.get_range())

        return bits

    def add_properies(self, **properties):
        """Add a property."""
        self.properties.update(properties)

    def check_bit_clash(self, bit_list):
        """Check if bits in list clash with pre-existing fields."""
        clashes = []
        for bit in bit_list:
            if bit in self.get_used_bits():
                clashes.append(bit)

        if len(clashes) == 0:
            return None

        return clashes

    def add_fields(self, *args):
        """Add fields."""
        for arg in args:
            if not isinstance(arg, HDLRegisterField):
                raise TypeError('only HDLRegisterField type allowed')

            # check clashes
            clashes = self.check_bit_clash(arg.get_range())
            if clashes is not None:
                raise ValueError('Cannot insert field,'
                                 ' bits "{}" already reserved'.format(clashes))

            # else, insert
            self.fields.append(arg)

    def get_write_mask(self):
        """Get register write access mask."""
        wr_mask = 0
        for field in self.fields:
            if field.permissions == 'R':
                continue

            for bit in field.get_range():
                wr_mask |= (1 << bit)

        return wr_mask
<commit_msg>make dumps_slice function a method<commit_after>"""HDL HDLRegister descriptors and actions."""


class HDLRegisterField(object):
    """Bitfield inside a register."""

    def __init__(self, name, reg_slice, permissions, properties=None):
        """Initialize."""
        self.name = name

        _slice = self._validate_slice(reg_slice)

        self.reg_slice = _slice
        self.permissions = permissions
        if properties is not None:
            self.properties = dict(properties)
        else:
            self.properties = {}

    def _validate_slice(self, reg_slice):
        if isinstance(reg_slice, (tuple, list)):
            if len(reg_slice) > 2:
                raise ValueError('invalid range')
            return reg_slice
        elif isinstance(reg_slice, int):
            return [reg_slice]
        else:
            raise TypeError('invalid type '
                            'for slice: "{}"'.format(type(reg_slice)))

    def add_properties(self, **kwargs):
        """Add a property."""
        self.properties.update(kwargs)

    def get_range(self):
        """Get which bits are claimed by this field."""
        if len(self.reg_slice) > 1:
            return range(self.reg_slice[1], self.reg_slice[0]+1)
        else:
            return self.reg_slice

    def dumps_slice(self):
        """Print formatted slice."""
        if len(self.reg_slice) == 2:
            return '[{}..{}]'.format(*self.reg_slice)
        else:
            return '[{}]'.format(self.reg_slice[0])


class HDLRegister(object):
    """Register."""

    def __init__(self, name, size, addr):
        """Initialize."""
        self.name = name
        self.size = size
        self.addr = addr
        self.fields = []
        self.properties = {}

    def get_used_bits(self):
        """Get which bits are already claimed by fields."""
        bits = []
        for field in self.fields:
            bits.extend(field.get_range())

        return bits

    def add_properies(self, **properties):
        """Add a property."""
        self.properties.update(properties)

    def check_bit_clash(self, bit_list):
        """Check if bits in list clash with pre-existing fields."""
        clashes = []
        for bit in bit_list:
            if bit in self.get_used_bits():
                clashes.append(bit)

        if len(clashes) == 0:
            return None

        return clashes

    def add_fields(self, *args):
        """Add fields."""
        for arg in args:
            if not isinstance(arg, HDLRegisterField):
                raise TypeError('only HDLRegisterField type allowed')

            # check clashes
            clashes = self.check_bit_clash(arg.get_range())
            if clashes is not None:
                raise ValueError('Cannot insert field,'
                                 ' bits "{}" already reserved'.format(clashes))

            # else, insert
            self.fields.append(arg)

    def get_write_mask(self):
        """Get register write access mask."""
        wr_mask = 0
        for field in self.fields:
            if field.permissions == 'R':
                continue

            for bit in field.get_range():
                wr_mask |= (1 << bit)

        return wr_mask

{'fraction_non_alphanumeric': 0.1133302368787738, 'fraction_numerical': 0.003096454559529339, 'mean_word_length': 1.8395604395604395, 'pattern_counts': {'":': 0, '<': 7, '<?xml version=': 0, '>': 7, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 4, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2186308', 'n_tokens_mistral': 1783, 'n_tokens_neox': 1694, 'n_words': 475}