<commit_before>/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* GPIO module for Chrome EC */

#include "board.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "registers.h"
#include "task.h"
#include "util.h"

/* Console output macros */
#define CPUTS(outstr) cputs(CC_GPIO, outstr)
#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)

/* For each EXTI bit, record which GPIO entry is using it */
static const struct gpio_info *exti_events[16];

struct port_config {
	uint32_t addr;
	uint32_t mode;
	uint32_t cnf;
};

/* helper function for generating bitmasks for STM32 GPIO config registers */
static void gpio_config_info(const struct gpio_info *g, uint32_t *addr,
		uint32_t *mode, uint32_t *cnf) {
	/*
	 * 2-bit config followed by 2-bit mode for each pin, each
	 * successive pin raises the exponent for the lowest bit
	 * set by an order of 4, e.g. 2^0, 2^4, 2^8, etc.
	 */
	if (g->mask & 0xff) {
		*addr = g->port;	/* GPIOx_CRL */
		*mode = g->mask;
	} else {
		*addr = g->port + 0x04;	/* GPIOx_CRH */
		*mode = g->mask >> 8;
	}
	*mode = *mode * *mode * *mode * *mode;
	*mode |= *mode << 1;
	*cnf = *mode << 2;
}

int gpio_pre_init(void)
{
	const struct gpio_info *g = gpio_list;
	int is_warm = 0;
	int i;
	uint32_t addr, cnf, mode, mask;

	if ((STM32_RCC_APB2ENR & 0x1fd) == 0x1fd) {
		/* This is a warm reboot */
		is_warm = 1;
	} else {
		/* Enable all GPIOs clocks
		 * TODO: more fine-grained enabling for power saving
		 */
		STM32_RCC_APB2ENR |= 0x1fd;<commit_msg>stm32: fix sysjump on stm32f100<commit_after>/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* GPIO module for Chrome EC */

#include "board.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "registers.h"
#include "task.h"
#include "util.h"

/* Console output macros */
#define CPUTS(outstr) cputs(CC_GPIO, outstr)
#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)

/* For each EXTI bit, record which GPIO entry is using it */
static const struct gpio_info *exti_events[16];

struct port_config {
	uint32_t addr;
	uint32_t mode;
	uint32_t cnf;
};

/* helper function for generating bitmasks for STM32 GPIO config registers */
static void gpio_config_info(const struct gpio_info *g, uint32_t *addr,
		uint32_t *mode, uint32_t *cnf) {
	/*
	 * 2-bit config followed by 2-bit mode for each pin, each
	 * successive pin raises the exponent for the lowest bit
	 * set by an order of 4, e.g. 2^0, 2^4, 2^8, etc.
	 */
	if (g->mask & 0xff) {
		*addr = g->port;	/* GPIOx_CRL */
		*mode = g->mask;
	} else {
		*addr = g->port + 0x04;	/* GPIOx_CRH */
		*mode = g->mask >> 8;
	}
	*mode = *mode * *mode * *mode * *mode;
	*mode |= *mode << 1;
	*cnf = *mode << 2;
}

int gpio_pre_init(void)
{
	const struct gpio_info *g = gpio_list;
	int is_warm = 0;
	int i;
	uint32_t addr, cnf, mode, mask;

	if (STM32_RCC_APB1ENR & 1) {
		/* This is a warm reboot : TIM2 is already active */
		is_warm = 1;
	} else {
		/* Enable all GPIOs clocks
		 * TODO: more fine-grained enabling for power saving
		 */
		STM32_RCC_APB2ENR |= 0x1fd;
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