<commit_before>/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* Clocks and power management settings */

#include <stdint.h>

#include "atomic.h"
#include "board.h"
#include "clock.h"
#include "common.h"
#include "console.h"
#include "cpu.h"
#include "hwtimer.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"

/* Allow serial console to wake up the EC from STOP mode */
/* #define CONFIG_FORCE_CONSOLE_RESUME */

/**
 * minimum delay to enter stop mode
 * STOP mode wakeup time with regulator in low power mode is 5 us.
 * PLL locking time is 200us.
 */
#define STOP_MODE_LATENCY 300 /* us */

/**
 * RTC clock frequency (connected to LSI clock)
 *
 * TODO: crosbug.com/p/12281 calibrate LSI frequency
 */
#define RTC_FREQ 40000 /* Hz */
#define US_PER_RTC_TICK (1000000 / RTC_FREQ)

/* On-going actions preventing to go into deep-sleep mode */
uint32_t sleep_mask = SLEEP_MASK_FORCE;

void enable_sleep(uint32_t mask)
{
	atomic_clear(&sleep_mask, mask);
}

void disable_sleep(uint32_t mask)
{
	atomic_or(&sleep_mask, mask);
}

static void wait_rtc_ready(void)
{
	/* wait for Registers Synchronized Flag */
	while (!(STM32_RTC_CRL & (1 << 3)))
		;<commit_msg>stm32: activate stop mode<commit_after>/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* Clocks and power management settings */

#include <stdint.h>

#include "atomic.h"
#include "board.h"
#include "clock.h"
#include "common.h"
#include "console.h"
#include "cpu.h"
#include "hwtimer.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"

/* Allow serial console to wake up the EC from STOP mode */
/* #define CONFIG_FORCE_CONSOLE_RESUME */

/**
 * minimum delay to enter stop mode
 * STOP mode wakeup time with regulator in low power mode is 5 us.
 * PLL locking time is 200us.
 */
#define STOP_MODE_LATENCY 300 /* us */

/**
 * RTC clock frequency (connected to LSI clock)
 *
 * TODO: crosbug.com/p/12281 calibrate LSI frequency
 */
#define RTC_FREQ 40000 /* Hz */
#define US_PER_RTC_TICK (1000000 / RTC_FREQ)

/* On-going actions preventing to go into deep-sleep mode */
uint32_t sleep_mask;

void enable_sleep(uint32_t mask)
{
	atomic_clear(&sleep_mask, mask);
}

void disable_sleep(uint32_t mask)
{
	atomic_or(&sleep_mask, mask);
}

static void wait_rtc_ready(void)
{
	/* wait for Registers Synchronized Flag */
	while (!(STM32_RTC_CRL & (1 << 3)))
		;
{'fraction_non_alphanumeric': 0.12103100485618229, 'fraction_numerical': 0.029137093761673515, 'mean_word_length': 4.071969696969697, 'pattern_counts': {'":': 0, '<': 9, '<?xml version=': 0, '>': 5, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1977772', 'n_tokens_mistral': 1015, 'n_tokens_neox': 929, 'n_words': 312}