<commit_before>TOC

0. Introduction
1. MMIO ranges and registers
2. DEBUG registers
3. Interrupts
3.1. User interrupts


= Introduction =

PBUS is present on all nvidia cards. In theory, it deals with "bus control".
In practice, it accumulates all sort of junk nobody bothered to create
a speecial area for. It is unaffected by any PMC.ENABLE bits.


= MMIO ranges and registers =

The MMIO ranges owned by PBUS are:

001000:002000 PBUS - main area
010000:020000 ??? - has something to do with PCI config space of other devices? [NV41-] [XXX]
060000:061000 PEEPHOLE - indirect memory access [NV84-] [peephole.txt]
080000:080200 PBUS_HWSQ_NEW_CODE - code RAM for hwsq [NV92:NVC0] [hwsq.txt]

The registers in the PBUS area are:

001000:001100 misc registers [see below] [XXX]
001100:001200 interrupts [NV03-] [see below]
001200:001208 ROM control [NV04:NV50] [prom.txt]
001300:001380 HWSQ - hardware sequencer [NV17:NV20, NV25:NVC0] [hwsq.txt]
001380:001400 VGA_STACK [NV41:NV50] [vga-stack.txt]
001400:001500 HWSQ - hardware sequencer [NV17:NV20, NV25:NVC0] [hwsq.txt]
001500:001540 misc registers [see below] [XXX]
001540:001550 HWUNITS - enabling/disabling optional hardware subunits [NV40:NV50] [see below]
00155c:001578 PEEPHOLE - indirect memory access [NV30:NV84] [peephole.txt]
001578:001580 HWSQ - hardware sequencer [NV41:NVC0] [hwsq.txt]
001580:0015a0 CLOCK_GATE - clock gating registers [NV17:NV20 NV25:NVC0] [see below]
001700:001800 HOST_MEM - host memory access setup [NV44:NV50] [nv40-host-mem.txt] [XXX: variants are wrong]
001700:001800 HOST_MEM - host memory access setup [NV50:NVC0] [nv50-host-mem.txt]
001700:001800 HOST_MEM - host memory access setup [NVC0-] [nvc0-host-mem.txt]
001800:001a00 PCI - PCI configuration space [NV01:NV50] [pci.txt]
001900:001980 REMAP - BAR1 remapping circuitry [NV50:NVC0] [nv50-remap.txt]
001980:001a00 P2P - NV50 P2P slave [NV50:NVC0] [nv50-p2p.txt]
[XXX: loads and loads of unknown registers not shown]


= DEBUG registers =

DEBUG registers store misc hardware control bits. They're mostly unknown, and
usually group together unrelated bits. The known bits include:

MMIO 0x001098: DEBUG_6 [NV17:NV20, NV25-]
  bit 3: HWSQ_ENABLE - enables HWSQ effects [hwsq.txt]
  bit 4: HWSQ_OVERRIDE_MODE - selects read value for HWSQ-overriden registers
         [hwsq.txt]
[XXX: document other known stuff]


= Interrupts =

The following registers deal with PBUS interrupts:

001100 INTR - interrupt status [NV03-]<commit_msg>pbus: Add the PWM and THERM ranges.<commit_after>TOC

0. Introduction
1. MMIO ranges and registers
2. DEBUG registers
3. Interrupts
3.1. User interrupts


= Introduction =

PBUS is present on all nvidia cards. In theory, it deals with "bus control".
In practice, it accumulates all sort of junk nobody bothered to create
a speecial area for. It is unaffected by any PMC.ENABLE bits.


= MMIO ranges and registers =

The MMIO ranges owned by PBUS are:

001000:002000 PBUS - main area
010000:020000 ??? - has something to do with PCI config space of other devices? [NV41-] [XXX]
060000:061000 PEEPHOLE - indirect memory access [NV84-] [peephole.txt]
080000:080200 PBUS_HWSQ_NEW_CODE - code RAM for hwsq [NV92:NVC0] [hwsq.txt]

The registers in the PBUS area are:

001000:0010f0 DEBUG registers [see below]
0010f0:0010f4 PWM - PWM generators [NV11:NV50] [nv10-gpio.txt]
001100:001200 interrupts [NV03-] [see below]
001200:001208 ROM control [NV04:NV50] [prom.txt]
001300:001380 HWSQ - hardware sequencer [NV17:NV20, NV25:NVC0] [hwsq.txt]
001380:001400 VGA_STACK [NV41:NV50] [vga-stack.txt]
001400:001500 HWSQ - hardware sequencer [NV17:NV20, NV25:NVC0] [hwsq.txt]
001500:001540 DEBUG registers [see below]
001540:001550 HWUNITS - enabling/disabling optional hardware subunits [NV40:NV50] [see below]
00155c:001578 PEEPHOLE - indirect memory access [NV30:NV84] [peephole.txt]
001578:001580 HWSQ - hardware sequencer [NV41:NVC0] [hwsq.txt]
001580:0015a0 CLOCK_GATE - clock gating registers [NV17:NV20 NV25:NVC0] [see below]
0015b0:0015c0 THERM - thermal sensor [NV43:NV50] [nv43-therm.txt]
0015f4:001604 PWM - PWM generators [NV41:NV50] [nv10-gpio.txt]
001700:001800 HOST_MEM - host memory access setup [NV44:NV50] [nv40-host-mem.txt] [XXX: variants are wrong]
001700:001800 HOST_MEM - host memory access setup [NV50:NVC0] [nv50-host-mem.txt]
001700:001800 HOST_MEM - host memory access setup [NVC0-] [nvc0-host-mem.txt]
001800:001a00 PCI - PCI configuration space [NV01:NV50] [pci.txt]
001900:001980 REMAP - BAR1 remapping circuitry [NV50:NVC0] [nv50-remap.txt]
001980:001a00 P2P - NV50 P2P slave [NV50:NVC0] [nv50-p2p.txt]
[XXX: loads and loads of unknown registers not shown]


= DEBUG registers =

DEBUG registers store misc hardware control bits. They're mostly unknown, and
usually group together unrelated bits. The known bits include:

MMIO 0x001098: DEBUG_6 [NV17:NV20, NV25-]
  bit 3: HWSQ_ENABLE - enables HWSQ effects [hwsq.txt]
  bit 4: HWSQ_OVERRIDE_MODE - selects read value for HWSQ-overriden registers
         [hwsq.txt]
[XXX: document other known stuff]


= Interrupts =

The following registers deal with PBUS interrupts:

001100 INTR - interrupt status [NV03-]
{'fraction_non_alphanumeric': 0.09498834498834499, 'fraction_numerical': 0.14918414918414918, 'mean_word_length': 4.891304347826087, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '713911', 'n_tokens_mistral': 2366, 'n_tokens_neox': 1870, 'n_words': 613}