<commit_before>---
layout: page
title: FIR Filter Chip Design - VLSI 
description: Spring 2015 VLSI course project (HMC)
img: /assets/img/proj_vlsi.png
timeline: 2015
date: 2018-08-22 13:32:20 +0300
---

One of my most interesting classes I took at HMC is VLSI. For the final project, my team created an FIR filter chip 
from scratch. 

More details are in the final report via image link:<commit_msg>adding vlsi project<commit_after>---
layout: page
title: FIR Filter Chip Design - VLSI 
description: Spring 2015 VLSI course project (HMC)
img: /assets/img/proj_vlsi.png
timeline: 2015
date: 2018-08-22 13:32:20 +0300
---

One of my most interesting classes I took at HMC is VLSI. For the final project, my team created an FIR filter chip 
from scratch. 

- - -
### Takeaways:
  1. Pulling a **all-nighter** to draw an 8-bit multiplier is not so fun.
  2. Learned how to verilog, correspond schematics to layouts.
  3. Designing chips are hard and the process is intricate.

- - -

More details are in the final report via image link:
{'fraction_non_alphanumeric': 0.08220502901353965, 'fraction_numerical': 0.05415860735009671, 'mean_word_length': 3.6, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3488422', 'n_tokens_mistral': 381, 'n_tokens_neox': 321, 'n_words': 152}