<commit_before>-- intel10g.lua -- Intel 82599 10GbE ethernet device driver

--- This module defines a device driver for one specific PCI device.
--- The load-time `...` argument must be bound to two values:
---     * The unique name for this module instance.
---     * The PCI address for the device this instance manages.

local moduleinstance,pciaddress = ...

if pciaddress == nil then
   print("WARNING: intel10g loaded as normal module; should be device-specific.")
end

module(moduleinstance,package.seeall)

local ffi = require "ffi"
local C = ffi.C
local lib = require("lib")
local pci = require("pci")
local register = require("register")
local memory = require("memory")
local test = require("test")
require("intel_h")
local bits, bitset = lib.bits, lib.bitset

-- DMA memory.
local num_descriptors = 32 * 1024
local buffer_count = 2 * 1024 * 1024
local rxdesc, rxdesc_phy
local txdesc, txdesc_phy
local buffers, buffers_phy

-- Configuration registers table.
r = {}
-- Statistics registers table.
s = {}

function open ()
   pci.set_bus_master(pciaddress, true)
   base = ffi.cast("uint32_t*", pci.map_pci_memory(pciaddress, 0))
   register.define(config_registers_desc, r, base)
   register.define(statistics_registers_desc, s, base)
   init_device()
end

function init_device ()
   init_dma_memory()
   disable_interrupts()
   global_reset()
   wait_eeprom_autoread()
   wait_dma()
--   setup_link()
   init_statistics()
   init_receive()
   init_transmit()
end

function disable_interrupts () end

function global_reset ()
   local reset = bits{LinkReset=3, DeviceReset=26}
   r.CTRL(reset)
   register.dump(r)
   C.usleep(1000)
   register.dump(r)
   r.CTRL:wait(reset, 0)
end

function wait_eeprom_autoread () r.EEC:wait(bits{AutoreadDone=9}) end
function wait_dma ()             r.RDRXCTL:wait(bits{DMAInitDone=3})  end

function init_statistics ()
   for _,reg in pairs(s) do reg:reset() end
end

function linkup () return bitset(r.LINKS(), 30) end

function get_configuration_state ()
   return { AUTOC = r.AUTOC(), HLREG0 = r.HLREG0() }
end

function restore_configuration_state (saved_state)
   r.AUTOC(saved_state.AUTOC)
   r.HLREG0(saved_state.HLREG0)
end

function enable_mac_loopback ()
   r.AUTOC:set(bits({ForceLinkUp=0, LMS10G=13}))
   r.HLREG0:set(bits({Loop=15}))
end

function init_receive ()
   set_promiscuous_mode() -- accept all, no need to configure MAC address filter
   r.RDRXCTL:set(bits{CRCStrip=0})
   r.HLREG0:clr(bits({RXLNGTHERREN=27, UndocumentedRXCRCSTRP=1}))
   r.RDBAL(rxdesc_phy % 2^32)
   r.RDBAH(rxdesc_phy / 2^32)
   r.RDLEN(num_descriptors * ffi.sizeof("union rx"))
   r.RXDCTL(bits{Enable=25})
   r.RXCTRL:set(bits{RXEN=0})
end

function init_transmit ()
   r.HLREG0:set(bits{TXCRCEN=0})
   r.TDBAL(txdesc_phy % 2^32)
   r.TDBAH(txdesc_phy / 2^32)
   r.TDLEN(num_descriptors * ffi.sizeof("union tx"))
   r.TDH(0)
   r.TDT(0)
   r.DMATXCTL(bits{TE=0})
   r.TXDCTL:wait(bits{Enable=25})
end

tdh, tdt = 0, 0 -- Cached values of TDT and TDH
txfree = 0
txdesc_flags = bits{eop=24,ifcs=25}
function transmit (address, size)
--   print("TX DUMP ("..size.."): " .. bit.tohex(ffi.cast("uint32_t*", address)[1]))
   txdesc[tdt].data.address = address
   txdesc[tdt].data.options = bit.bor(size, txdesc_flags)
   tdt = (tdt + 1) % num_descriptors
end

function can_reclaim_buffer ()
   return txfree ~= tdh
end

function reclaim_buffer ()
   if txfree ~= tdh then
      local address = txdesc[txfree].data.address
      txfree = (txfree + 1) % num_descriptors
      return ffi.cast("uint8_t*", address)
   end
end

function sync_transmit ()
   C.full_memory_barrier()
   tdh = r.TDH()
   r.TDT(tdt)
end<commit_msg>intel10g: Removed reclaim_buffer logic.<commit_after>-- intel10g.lua -- Intel 82599 10GbE ethernet device driver

--- This module defines a device driver for one specific PCI device.
--- The load-time `...` argument must be bound to two values:
---     * The unique name for this module instance.
---     * The PCI address for the device this instance manages.

local moduleinstance,pciaddress = ...

if pciaddress == nil then
   print("WARNING: intel10g loaded as normal module; should be device-specific.")
end

module(moduleinstance,package.seeall)

local ffi = require "ffi"
local C = ffi.C
local lib = require("lib")
local pci = require("pci")
local register = require("register")
local memory = require("memory")
local test = require("test")
require("intel_h")
local bits, bitset = lib.bits, lib.bitset

-- DMA memory.
local num_descriptors = 32 * 1024
local buffer_count = 2 * 1024 * 1024
local rxdesc, rxdesc_phy
local txdesc, txdesc_phy
local buffers, buffers_phy

-- Configuration registers table.
r = {}
-- Statistics registers table.
s = {}

function open ()
   pci.set_bus_master(pciaddress, true)
   base = ffi.cast("uint32_t*", pci.map_pci_memory(pciaddress, 0))
   register.define(config_registers_desc, r, base)
   register.define(statistics_registers_desc, s, base)
   init_device()
end

function init_device ()
   init_dma_memory()
   disable_interrupts()
   global_reset()
   wait_eeprom_autoread()
   wait_dma()
--   setup_link()
   init_statistics()
   init_receive()
   init_transmit()
end

function disable_interrupts () end

function global_reset ()
   local reset = bits{LinkReset=3, DeviceReset=26}
   r.CTRL(reset)
   register.dump(r)
   C.usleep(1000)
   register.dump(r)
   r.CTRL:wait(reset, 0)
end

function wait_eeprom_autoread () r.EEC:wait(bits{AutoreadDone=9}) end
function wait_dma ()             r.RDRXCTL:wait(bits{DMAInitDone=3})  end

function init_statistics ()
   for _,reg in pairs(s) do reg:reset() end
end

function linkup () return bitset(r.LINKS(), 30) end

function get_configuration_state ()
   return { AUTOC = r.AUTOC(), HLREG0 = r.HLREG0() }
end

function restore_configuration_state (saved_state)
   r.AUTOC(saved_state.AUTOC)
   r.HLREG0(saved_state.HLREG0)
end

function enable_mac_loopback ()
   r.AUTOC:set(bits({ForceLinkUp=0, LMS10G=13}))
   r.HLREG0:set(bits({Loop=15}))
end

function init_receive ()
   set_promiscuous_mode() -- accept all, no need to configure MAC address filter
   r.RDRXCTL:set(bits{CRCStrip=0})
   r.HLREG0:clr(bits({RXLNGTHERREN=27, UndocumentedRXCRCSTRP=1}))
   r.RDBAL(rxdesc_phy % 2^32)
   r.RDBAH(rxdesc_phy / 2^32)
   r.RDLEN(num_descriptors * ffi.sizeof("union rx"))
   r.RXDCTL(bits{Enable=25})
   r.RXCTRL:set(bits{RXEN=0})
end

function init_transmit ()
   r.HLREG0:set(bits{TXCRCEN=0})
   r.TDBAL(txdesc_phy % 2^32)
   r.TDBAH(txdesc_phy / 2^32)
   r.TDLEN(num_descriptors * ffi.sizeof("union tx"))
   r.TDH(0)
   r.TDT(0)
   r.DMATXCTL(bits{TE=0})
   r.TXDCTL:wait(bits{Enable=25})
end

tdh, tdt = 0, 0 -- Cached values of TDT and TDH
txfree = 0
txdesc_flags = bits{eop=24,ifcs=25}
function transmit (address, size)
--   print("TX DUMP ("..size.."): " .. bit.tohex(ffi.cast("uint32_t*", address)[1]))
   txdesc[tdt].data.address = address
   txdesc[tdt].data.options = bit.bor(size, txdesc_flags)
   tdt = (tdt + 1) % num_descriptors
end

function sync_transmit ()
   C.full_memory_barrier()
   tdh = r.TDH()
   r.TDT(tdt)
end
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