<commit_before>#=========================================================================
# machine.py
#=========================================================================

from pydgin.storage import RegisterFile
from pydgin.utils import specialize
from utils import trim_64

#-------------------------------------------------------------------------
# State
#-------------------------------------------------------------------------
class State( object ):
  # TODO: add virtualizables
  _virtualizable_ = ['pc', 'num_insts']

  def __init__( self, memory, debug, reset_addr=0x400 ):
    self.pc       = reset_addr

    self.xlen     = 64   # defines the bitwidth of int registers
    self.flen     = 64   # defines the bitwidth of fp  registers

    self.rf       = RiscVRegisterFile()
    self.fp       = RiscVFPRegisterFile()
    self.csr      = 0    # Bits( XLEN )
    self.fsr      = 0    # Bits( 32 )
    self.mem      = memory

    self    .debug = debug
    self.rf .debug = debug
    self.fp .debug = debug
    self.mem.debug = debug<commit_msg>[riscv] fix typo in name of fcsr register<commit_after>#=========================================================================
# machine.py
#=========================================================================

from pydgin.storage import RegisterFile
from pydgin.utils import specialize
from utils import trim_64

#-------------------------------------------------------------------------
# State
#-------------------------------------------------------------------------
class State( object ):
  # TODO: add virtualizables
  _virtualizable_ = ['pc', 'num_insts']

  def __init__( self, memory, debug, reset_addr=0x400 ):
    self.pc       = reset_addr

    self.xlen     = 64   # defines the bitwidth of int registers
    self.flen     = 64   # defines the bitwidth of fp  registers

    self.rf       = RiscVRegisterFile()
    self.fp       = RiscVFPRegisterFile()
    self.csr      = 0    # Bits( XLEN )
    self.fcsr     = 0    # Bits( 32 )
    self.mem      = memory

    self    .debug = debug
    self.rf .debug = debug
    self.fp .debug = debug
    self.mem.debug = debug
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