<commit_before>/**
 * \file
 *
 * \brief Header file for ATSAME70Q21
 *
 * Copyright (c) 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
 *
 * \license_start
 *
 * \page License
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * \license_stop
 *
 */

#ifndef _SAME70Q21_H_
#define _SAME70Q21_H_

/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions
  This file defines all structures and symbols for SAME70Q21:
    - registers and bitfields
    - peripheral base address
    - peripheral ID
    - PIO definitions
 *  @{
 */

#ifdef __cplusplus
 extern "C" {
#endif

#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
/* IO definitions (access restrictions to peripheral registers) */
/** \defgroup Atmel_glob_defs Atmel Global Defines

    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.

    \remark
    CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint<size>_t' respective types.
    Default the header files will follow the CMSIS core syntax.
 *  @{
 */

#ifndef __cplusplus
typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
#else
typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
#endif
typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */

#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */

/** @}  end of Atmel Global Defines */

/** \addtogroup SAME70Q21_cmsis CMSIS Definitions
 *  @{
 */
/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR SAME70Q21 */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** Interrupt Number Definition */
typedef enum IRQn
{
/******  CORTEX-M7 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn       = -14, /**< 2   Non Maskable Interrupt               */
  HardFault_IRQn            = -13, /**< 3   HardFault Interrupt                  */
  MemoryManagement_IRQn     = -12, /**< 4   Cortex-M7 Memory Management Interrupt  */
  BusFault_IRQn             = -11, /**< 5   Cortex-M7 Bus Fault Interrupt        */
  UsageFault_IRQn           = -10, /**< 6   Cortex-M7 Usage Fault Interrupt      */
  SVCall_IRQn               = -5 , /**< 11  Cortex-M7 SV Call Interrupt          */
  DebugMonitor_IRQn         = -4 , /**< 12  Cortex-M7 Debug Monitor Interrupt    */
  PendSV_IRQn               = -2 , /**< 14  Cortex-M7 Pend SV Interrupt          */
  SysTick_IRQn              = -1 , /**< 15  Cortex-M7 System Tick Interrupt      */
/******  SAME70Q21 specific Interrupt Numbers ***********************************/
  SUPC_IRQn                 = 0  , /**< 0   SAME70Q21 Supply Controller (SUPC)  */
  RSTC_IRQn                 = 1  , /**< 1   SAME70Q21 Reset Controller (RSTC)   */
  RTC_IRQn                  = 2  , /**< 2   SAME70Q21 Real-time Clock (RTC)     */
  RTT_IRQn                  = 3  , /**< 3   SAME70Q21 Real-time Timer (RTT)     */
  WDT_IRQn                  = 4  , /**< 4   SAME70Q21 Watchdog Timer (WDT)      */
  PMC_IRQn                  = 5  , /**< 5   SAME70Q21 Power Management Controller (PMC) */
  EFC_IRQn                  = 6  , /**< 6   SAME70Q21 Embedded Flash Controller (EFC) */
  UART0_IRQn                = 7  , /**< 7   SAME70Q21 Universal Asynchronous Receiver Transmitter (UART0) */
  UART1_IRQn                = 8  , /**< 8   SAME70Q21 Universal Asynchronous Receiver Transmitter (UART1) */
  PIOA_IRQn                 = 10 , /**< 10  SAME70Q21 Parallel Input/Output Controller (PIOA) */
  PIOB_IRQn                 = 11 , /**< 11  SAME70Q21 Parallel Input/Output Controller (PIOB) */
  PIOC_IRQn                 = 12 , /**< 12  SAME70Q21 Parallel Input/Output Controller (PIOC) */
  USART0_IRQn               = 13 , /**< 13  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
  USART1_IRQn               = 14 , /**< 14  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
  USART2_IRQn               = 15 , /**< 15  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */
  PIOD_IRQn                 = 16 , /**< 16  SAME70Q21 Parallel Input/Output Controller (PIOD) */
  PIOE_IRQn                 = 17 , /**< 17  SAME70Q21 Parallel Input/Output Controller (PIOE) */
  HSMCI_IRQn                = 18 , /**< 18  SAME70Q21 High Speed MultiMedia Card Interface (HSMCI) */
  TWIHS0_IRQn               = 19 , /**< 19  SAME70Q21 Two-wire Interface High Speed (TWIHS0) */
  TWIHS1_IRQn               = 20 , /**< 20  SAME70Q21 Two-wire Interface High Speed (TWIHS1) */
  SPI0_IRQn                 = 21 , /**< 21  SAME70Q21 Serial Peripheral Interface (SPI0) */
  SSC_IRQn                  = 22 , /**< 22  SAME70Q21 Synchronous Serial Controller (SSC) */
  TC0_IRQn                  = 23 , /**< 23  SAME70Q21 Timer Counter (TC0)       */
  TC1_IRQn                  = 24 , /**< 24  SAME70Q21 Timer Counter (TC0)       */
  TC2_IRQn                  = 25 , /**< 25  SAME70Q21 Timer Counter (TC0)       */
  TC3_IRQn                  = 26 , /**< 26  SAME70Q21 Timer Counter (TC1)       */
  TC4_IRQn                  = 27 , /**< 27  SAME70Q21 Timer Counter (TC1)       */
  TC5_IRQn                  = 28 , /**< 28  SAME70Q21 Timer Counter (TC1)       */
  AFEC0_IRQn                = 29 , /**< 29  SAME70Q21 Analog Front-End Controller (AFEC0) */
  DACC_IRQn                 = 30 , /**< 30  SAME70Q21 Digital-to-Analog Converter Controller (DACC) */
  PWM0_IRQn                 = 31 , /**< 31  SAME70Q21 Pulse Width Modulation Controller (PWM0) */
  ICM_IRQn                  = 32 , /**< 32  SAME70Q21 Integrity Check Monitor (ICM) */
  ACC_IRQn                  = 33 , /**< 33  SAME70Q21 Analog Comparator Controller (ACC) */
  USBHS_IRQn                = 34 , /**< 34  SAME70Q21 USB High-Speed Interface (USBHS) */
  MCAN0_IRQn                = 35 , /**< 35  SAME70Q21 Controller Area Network (MCAN0) */
  MCAN1_IRQn                = 37 , /**< 37  SAME70Q21 Controller Area Network (MCAN1) */
  GMAC_IRQn                 = 39 , /**< 39  SAME70Q21 Gigabit Ethernet MAC (GMAC) */
  AFEC1_IRQn                = 40 , /**< 40  SAME70Q21 Analog Front-End Controller (AFEC1) */
  TWIHS2_IRQn               = 41 , /**< 41  SAME70Q21 Two-wire Interface High Speed (TWIHS2) */
  SPI1_IRQn                 = 42 , /**< 42  SAME70Q21 Serial Peripheral Interface (SPI1) */
  QSPI_IRQn                 = 43 , /**< 43  SAME70Q21 Quad Serial Peripheral Interface (QSPI) */
  UART2_IRQn                = 44 , /**< 44  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART2) */
  UART3_IRQn                = 45 , /**< 45  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART3) */
  UART4_IRQn                = 46 , /**< 46  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART4) */
  TC6_IRQn                  = 47 , /**< 47  SAME70Q21 Timer Counter (TC2)       */
  TC7_IRQn                  = 48 , /**< 48  SAME70Q21 Timer Counter (TC2)       */
  TC8_IRQn                  = 49 , /**< 49  SAME70Q21 Timer Counter (TC2)       */
  TC9_IRQn                  = 50 , /**< 50  SAME70Q21 Timer Counter (TC3)       */
  TC10_IRQn                 = 51 , /**< 51  SAME70Q21 Timer Counter (TC3)       */
  TC11_IRQn                 = 52 , /**< 52  SAME70Q21 Timer Counter (TC3)       */
  AES_IRQn                  = 56 , /**< 56  SAME70Q21 Advanced Encryption Standard (AES) */
  TRNG_IRQn                 = 57 , /**< 57  SAME70Q21 True Random Number Generator (TRNG) */
  XDMAC_IRQn                = 58 , /**< 58  SAME70Q21 Extensible DMA Controller (XDMAC) */
  ISI_IRQn                  = 59 , /**< 59  SAME70Q21 Image Sensor Interface (ISI) */
  PWM1_IRQn                 = 60 , /**< 60  SAME70Q21 Pulse Width Modulation Controller (PWM1) */
  RSWDT_IRQn                = 63 , /**< 63  SAME70Q21 Reinforced Safety Watchdog Timer (RSWDT) */
  SDRAMC_IRQn               = 62 , /**< 62  SAME70Q21 SDRAM Controller (SDRAMC) */

  PERIPH_COUNT_IRQn        = 64  /**< Number of peripheral IDs */
} IRQn_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct _DeviceVectors
{
  /* Stack pointer */
  void* pvStack;
  /* Cortex-M handlers */
  void* pfnReset_Handler;                        /* 0   Reset handler                        */
  void* pfnNMI_Handler;                          /* 2   Non Maskable Interrupt               */
  void* pfnHardFault_Handler;                    /* 3   HardFault Interrupt                  */
  void* pfnMemManage_Handler;                    /* 4   Cortex-M7 Memory Management Interrupt  */
  void* pfnBusFault_Handler;                     /* 5   Cortex-M7 Bus Fault Interrupt        */<commit_msg>ext: Atmel ASF: Add missing interrupt number definitions<commit_after>/**
 * \file
 *
 * \brief Header file for ATSAME70Q21
 *
 * Copyright (c) 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
 *
 * \license_start
 *
 * \page License
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * \license_stop
 *
 */

#ifndef _SAME70Q21_H_
#define _SAME70Q21_H_

/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions
  This file defines all structures and symbols for SAME70Q21:
    - registers and bitfields
    - peripheral base address
    - peripheral ID
    - PIO definitions
 *  @{
 */

#ifdef __cplusplus
 extern "C" {
#endif

#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
/* IO definitions (access restrictions to peripheral registers) */
/** \defgroup Atmel_glob_defs Atmel Global Defines

    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.

    \remark
    CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint<size>_t' respective types.
    Default the header files will follow the CMSIS core syntax.
 *  @{
 */

#ifndef __cplusplus
typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
#else
typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
#endif
typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile       uint32_t WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */

#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */

/** @}  end of Atmel Global Defines */

/** \addtogroup SAME70Q21_cmsis CMSIS Definitions
 *  @{
 */
/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR SAME70Q21 */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** Interrupt Number Definition */
typedef enum IRQn
{
/******  CORTEX-M7 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn       = -14, /**< 2   Non Maskable Interrupt               */
  HardFault_IRQn            = -13, /**< 3   HardFault Interrupt                  */
  MemoryManagement_IRQn     = -12, /**< 4   Cortex-M7 Memory Management Interrupt  */
  BusFault_IRQn             = -11, /**< 5   Cortex-M7 Bus Fault Interrupt        */
  UsageFault_IRQn           = -10, /**< 6   Cortex-M7 Usage Fault Interrupt      */
  SVCall_IRQn               = -5 , /**< 11  Cortex-M7 SV Call Interrupt          */
  DebugMonitor_IRQn         = -4 , /**< 12  Cortex-M7 Debug Monitor Interrupt    */
  PendSV_IRQn               = -2 , /**< 14  Cortex-M7 Pend SV Interrupt          */
  SysTick_IRQn              = -1 , /**< 15  Cortex-M7 System Tick Interrupt      */
/******  SAME70Q21 specific Interrupt Numbers ***********************************/
  SUPC_IRQn                 = 0  , /**< 0   SAME70Q21 Supply Controller (SUPC)  */
  RSTC_IRQn                 = 1  , /**< 1   SAME70Q21 Reset Controller (RSTC)   */
  RTC_IRQn                  = 2  , /**< 2   SAME70Q21 Real-time Clock (RTC)     */
  RTT_IRQn                  = 3  , /**< 3   SAME70Q21 Real-time Timer (RTT)     */
  WDT_IRQn                  = 4  , /**< 4   SAME70Q21 Watchdog Timer (WDT)      */
  PMC_IRQn                  = 5  , /**< 5   SAME70Q21 Power Management Controller (PMC) */
  EFC_IRQn                  = 6  , /**< 6   SAME70Q21 Embedded Flash Controller (EFC) */
  UART0_IRQn                = 7  , /**< 7   SAME70Q21 Universal Asynchronous Receiver Transmitter (UART0) */
  UART1_IRQn                = 8  , /**< 8   SAME70Q21 Universal Asynchronous Receiver Transmitter (UART1) */
  PIOA_IRQn                 = 10 , /**< 10  SAME70Q21 Parallel Input/Output Controller (PIOA) */
  PIOB_IRQn                 = 11 , /**< 11  SAME70Q21 Parallel Input/Output Controller (PIOB) */
  PIOC_IRQn                 = 12 , /**< 12  SAME70Q21 Parallel Input/Output Controller (PIOC) */
  USART0_IRQn               = 13 , /**< 13  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
  USART1_IRQn               = 14 , /**< 14  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
  USART2_IRQn               = 15 , /**< 15  SAME70Q21 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */
  PIOD_IRQn                 = 16 , /**< 16  SAME70Q21 Parallel Input/Output Controller (PIOD) */
  PIOE_IRQn                 = 17 , /**< 17  SAME70Q21 Parallel Input/Output Controller (PIOE) */
  HSMCI_IRQn                = 18 , /**< 18  SAME70Q21 High Speed MultiMedia Card Interface (HSMCI) */
  TWIHS0_IRQn               = 19 , /**< 19  SAME70Q21 Two-wire Interface High Speed (TWIHS0) */
  TWIHS1_IRQn               = 20 , /**< 20  SAME70Q21 Two-wire Interface High Speed (TWIHS1) */
  SPI0_IRQn                 = 21 , /**< 21  SAME70Q21 Serial Peripheral Interface (SPI0) */
  SSC_IRQn                  = 22 , /**< 22  SAME70Q21 Synchronous Serial Controller (SSC) */
  TC0_IRQn                  = 23 , /**< 23  SAME70Q21 Timer Counter (TC0)       */
  TC1_IRQn                  = 24 , /**< 24  SAME70Q21 Timer Counter (TC0)       */
  TC2_IRQn                  = 25 , /**< 25  SAME70Q21 Timer Counter (TC0)       */
  TC3_IRQn                  = 26 , /**< 26  SAME70Q21 Timer Counter (TC1)       */
  TC4_IRQn                  = 27 , /**< 27  SAME70Q21 Timer Counter (TC1)       */
  TC5_IRQn                  = 28 , /**< 28  SAME70Q21 Timer Counter (TC1)       */
  AFEC0_IRQn                = 29 , /**< 29  SAME70Q21 Analog Front-End Controller (AFEC0) */
  DACC_IRQn                 = 30 , /**< 30  SAME70Q21 Digital-to-Analog Converter Controller (DACC) */
  PWM0_IRQn                 = 31 , /**< 31  SAME70Q21 Pulse Width Modulation Controller (PWM0) */
  ICM_IRQn                  = 32 , /**< 32  SAME70Q21 Integrity Check Monitor (ICM) */
  ACC_IRQn                  = 33 , /**< 33  SAME70Q21 Analog Comparator Controller (ACC) */
  USBHS_IRQn                = 34 , /**< 34  SAME70Q21 USB High-Speed Interface (USBHS) */
  MCAN0_IRQn                = 35 , /**< 35  SAME70Q21 Controller Area Network (MCAN0) */
  MCAN1_IRQn                = 37 , /**< 37  SAME70Q21 Controller Area Network (MCAN1) */
  GMAC_IRQn                 = 39 , /**< 39  SAME70Q21 Gigabit Ethernet MAC (GMAC) */
  AFEC1_IRQn                = 40 , /**< 40  SAME70Q21 Analog Front-End Controller (AFEC1) */
  TWIHS2_IRQn               = 41 , /**< 41  SAME70Q21 Two-wire Interface High Speed (TWIHS2) */
  SPI1_IRQn                 = 42 , /**< 42  SAME70Q21 Serial Peripheral Interface (SPI1) */
  QSPI_IRQn                 = 43 , /**< 43  SAME70Q21 Quad Serial Peripheral Interface (QSPI) */
  UART2_IRQn                = 44 , /**< 44  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART2) */
  UART3_IRQn                = 45 , /**< 45  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART3) */
  UART4_IRQn                = 46 , /**< 46  SAME70Q21 Universal Asynchronous Receiver Transmitter (UART4) */
  TC6_IRQn                  = 47 , /**< 47  SAME70Q21 Timer Counter (TC2)       */
  TC7_IRQn                  = 48 , /**< 48  SAME70Q21 Timer Counter (TC2)       */
  TC8_IRQn                  = 49 , /**< 49  SAME70Q21 Timer Counter (TC2)       */
  TC9_IRQn                  = 50 , /**< 50  SAME70Q21 Timer Counter (TC3)       */
  TC10_IRQn                 = 51 , /**< 51  SAME70Q21 Timer Counter (TC3)       */
  TC11_IRQn                 = 52 , /**< 52  SAME70Q21 Timer Counter (TC3)       */
  AES_IRQn                  = 56 , /**< 56  SAME70Q21 Advanced Encryption Standard (AES) */
  TRNG_IRQn                 = 57 , /**< 57  SAME70Q21 True Random Number Generator (TRNG) */
  XDMAC_IRQn                = 58 , /**< 58  SAME70Q21 Extensible DMA Controller (XDMAC) */
  ISI_IRQn                  = 59 , /**< 59  SAME70Q21 Image Sensor Interface (ISI) */
  PWM1_IRQn                 = 60 , /**< 60  SAME70Q21 Pulse Width Modulation Controller (PWM1) */
  RSWDT_IRQn                = 63 , /**< 63  SAME70Q21 Reinforced Safety Watchdog Timer (RSWDT) */
  SDRAMC_IRQn               = 62 , /**< 62  SAME70Q21 SDRAM Controller (SDRAMC) */

  GMACQ1_IRQn               = 66 , /**< 66  SAME70Q21 Priority Queue 1 (GMAC) */
  GMACQ2_IRQn               = 67 , /**< 67  SAME70Q21 Priority Queue 2 (GMAC) */

  PERIPH_COUNT_IRQn                /**< Number of peripheral IDs */
} IRQn_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */


#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct _DeviceVectors
{
  /* Stack pointer */
  void* pvStack;
  /* Cortex-M handlers */
  void* pfnReset_Handler;                        /* 0   Reset handler                        */
  void* pfnNMI_Handler;                          /* 2   Non Maskable Interrupt               */
  void* pfnHardFault_Handler;                    /* 3   HardFault Interrupt                  */
  void* pfnMemManage_Handler;                    /* 4   Cortex-M7 Memory Management Interrupt  */
  void* pfnBusFault_Handler;                     /* 5   Cortex-M7 Bus Fault Interrupt        */
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