<commit_before>/* SPDX-License-Identifier: BSD-3-Clause
 *
 *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
 *   Copyright 2017 NXP
 *
 */
#ifndef __DPAA_ETHDEV_H__
#define __DPAA_ETHDEV_H__

/* System headers */
#include <stdbool.h>
#include <rte_ethdev_driver.h>
#include <rte_event_eth_rx_adapter.h>

#include <fsl_usd.h>
#include <fsl_qman.h>
#include <fsl_bman.h>
#include <dpaa_of.h>
#include <netcfg.h>

#define MAX_DPAA_CORES			4
#define DPAA_MBUF_HW_ANNOTATION		64
#define DPAA_FD_PTA_SIZE		64

/* mbuf->seqn will be used to store event entry index for
 * driver specific usage. For parallel mode queues, invalid
 * index will be set and for atomic mode queues, valid value
 * ranging from 1 to 16.
 */
#define DPAA_INVALID_MBUF_SEQN  0

/* we will re-use the HEADROOM for annotation in RX */
#define DPAA_HW_BUF_RESERVE	0
#define DPAA_PACKET_LAYOUT_ALIGN	64

/* Alignment to use for cpu-local structs to avoid coherency problems. */
#define MAX_CACHELINE			64

#define DPAA_MAX_RX_PKT_LEN  10240

#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */

/* RX queue tail drop threshold (CGR Based) in frame count */
#define CGR_RX_PERFQ_THRESH 256

/*max mac filter for memac(8) including primary mac addr*/
#define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)

/*Maximum number of slots available in TX ring*/
#define DPAA_TX_BURST_SIZE	7

/* Optimal burst size for RX and TX as default */
#define DPAA_DEF_RX_BURST_SIZE 7
#define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE

#ifndef VLAN_TAG_SIZE
#define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
#endif

/* PCD frame queues */
#define DPAA_PCD_FQID_START		0x400
#define DPAA_PCD_FQID_MULTIPLIER	0x100
#define DPAA_DEFAULT_NUM_PCD_QUEUES	1
#define DPAA_MAX_NUM_PCD_QUEUES		4

#define DPAA_IF_TX_PRIORITY		3
#define DPAA_IF_RX_PRIORITY		0
#define DPAA_IF_DEBUG_PRIORITY		7

#define DPAA_IF_RX_ANNOTATION_STASH	1
#define DPAA_IF_RX_DATA_STASH		1
#define DPAA_IF_RX_CONTEXT_STASH		0

/* Each "debug" FQ is represented by one of these */
#define DPAA_DEBUG_FQ_RX_ERROR   0
#define DPAA_DEBUG_FQ_TX_ERROR   1

#define DPAA_RSS_OFFLOAD_ALL ( \
	ETH_RSS_FRAG_IPV4 | \
	ETH_RSS_NONFRAG_IPV4_TCP | \
	ETH_RSS_NONFRAG_IPV4_UDP | \
	ETH_RSS_NONFRAG_IPV4_SCTP | \
	ETH_RSS_FRAG_IPV6 | \
	ETH_RSS_NONFRAG_IPV6_TCP | \
	ETH_RSS_NONFRAG_IPV6_UDP | \
	ETH_RSS_NONFRAG_IPV6_SCTP)<commit_msg>net/dpaa: fix supported RSS types<commit_after>/* SPDX-License-Identifier: BSD-3-Clause
 *
 *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
 *   Copyright 2017 NXP
 *
 */
#ifndef __DPAA_ETHDEV_H__
#define __DPAA_ETHDEV_H__

/* System headers */
#include <stdbool.h>
#include <rte_ethdev_driver.h>
#include <rte_event_eth_rx_adapter.h>

#include <fsl_usd.h>
#include <fsl_qman.h>
#include <fsl_bman.h>
#include <dpaa_of.h>
#include <netcfg.h>

#define MAX_DPAA_CORES			4
#define DPAA_MBUF_HW_ANNOTATION		64
#define DPAA_FD_PTA_SIZE		64

/* mbuf->seqn will be used to store event entry index for
 * driver specific usage. For parallel mode queues, invalid
 * index will be set and for atomic mode queues, valid value
 * ranging from 1 to 16.
 */
#define DPAA_INVALID_MBUF_SEQN  0

/* we will re-use the HEADROOM for annotation in RX */
#define DPAA_HW_BUF_RESERVE	0
#define DPAA_PACKET_LAYOUT_ALIGN	64

/* Alignment to use for cpu-local structs to avoid coherency problems. */
#define MAX_CACHELINE			64

#define DPAA_MAX_RX_PKT_LEN  10240

#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */

/* RX queue tail drop threshold (CGR Based) in frame count */
#define CGR_RX_PERFQ_THRESH 256

/*max mac filter for memac(8) including primary mac addr*/
#define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)

/*Maximum number of slots available in TX ring*/
#define DPAA_TX_BURST_SIZE	7

/* Optimal burst size for RX and TX as default */
#define DPAA_DEF_RX_BURST_SIZE 7
#define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE

#ifndef VLAN_TAG_SIZE
#define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
#endif

/* PCD frame queues */
#define DPAA_PCD_FQID_START		0x400
#define DPAA_PCD_FQID_MULTIPLIER	0x100
#define DPAA_DEFAULT_NUM_PCD_QUEUES	1
#define DPAA_MAX_NUM_PCD_QUEUES		4

#define DPAA_IF_TX_PRIORITY		3
#define DPAA_IF_RX_PRIORITY		0
#define DPAA_IF_DEBUG_PRIORITY		7

#define DPAA_IF_RX_ANNOTATION_STASH	1
#define DPAA_IF_RX_DATA_STASH		1
#define DPAA_IF_RX_CONTEXT_STASH		0

/* Each "debug" FQ is represented by one of these */
#define DPAA_DEBUG_FQ_RX_ERROR   0
#define DPAA_DEBUG_FQ_TX_ERROR   1

#define DPAA_RSS_OFFLOAD_ALL ( \
	ETH_RSS_L2_PAYLOAD | \
	ETH_RSS_IP | \
	ETH_RSS_UDP | \
	ETH_RSS_TCP | \
	ETH_RSS_SCTP)
{'fraction_non_alphanumeric': 0.07375643224699828, 'fraction_numerical': 0.027658662092624357, 'mean_word_length': 4.8531994981179425, 'pattern_counts': {'":': 0, '<': 21, '<?xml version=': 0, '>': 21, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4913783', 'n_tokens_mistral': 2073, 'n_tokens_neox': 1920, 'n_words': 486}