<commit_before>/* 
* File:    p4_native.c
* CVS:     $Id$
* Author:  <NAME>
*          <EMAIL>
* Mods:    <your name here>
*          <your email address>
*/

#ifdef _WIN32
  /* Define SUBSTRATE to map to linux-perfctr.h
   * since we haven't figured out how to assign a value 
   * to a label at make inside the Windows IDE */
#define SUBSTRATE "linux-perfctr.h"
#endif

#include "papi.h"
#include SUBSTRATE
#include "papi_preset.h"
#include "papi_internal.h"
#include "papi_protos.h"


#ifdef __i386__
/*
    Native event index structure:

   +----------+--------+----------------+
   |0100000000| event  |      mask      |
   +----------+--------+----------------+
    31   -  24 23 -- 16 15    ----      0
*/


/*  Definitions of the virtual indexes of all P4 native events used in the preset tables.
    To create a new native event index, make up an appropriate name (used only internally);
    the definition for the name consists of:
    - the NATIVE_MASK bit;
    - one of the event group names from the enum table in p4_events.h, shifted to the 3rd byte;
    - any required mask bits from that event group, shifted into position;
      valid mask bits for each group are defined in p4_events.h

   Definitive descriptions of the event groups can be found in:
    IA32 Intel Arch. SW. Dev. Man. V3: Appendix A, Table A-1
    Order Number 245472-012, 2003.
*/

#define PNE_branch_retired_all (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMNM) + (1<<MMTP) + (1<<MMTM))
#define PNE_branch_retired_not_taken (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMNM))
#define PNE_branch_retired_taken (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTP) + (1<<MMTM))
#define PNE_branch_retired_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMTP))
#define PNE_branch_retired_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNM) + (1<<MMTM))
#define PNE_branch_retired_not_taken_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP))
#define PNE_branch_retired_taken_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTP))
#define PNE_branch_retired_taken_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTM))
#define PNE_branch_retired_not_taken_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNM))
#define PNE_cycles (NATIVE_MASK + (P4_custom_event<<16) + 0)    // this is the first custom entry
#define PNE_page_walk_type_data_miss (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<DTMISS))
#define PNE_page_walk_type_instr_miss (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<ITMISS))
#define PNE_page_walk_type_all (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<DTMISS) + (1<<ITMISS))
#define PNE_x87_FP_uop_tag0 (NATIVE_MASK + (P4_x87_FP_uop<<16) + (1<<TAG0) + (1<<ALL))
#define PNE_execution_event_nbogus0 (NATIVE_MASK + (P4_execution_event<<16) + (1<<NBOGUS0))
#define PNE_replay_event (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS))
#define PNE_replay_event_L1_load_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT)  + (1<<PEBS_L1_MISS_BIT))
#define PNE_replay_event_L1_data_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT) + (1<<PEBS_L1_MISS_BIT))
#define PNE_replay_event_L1_data_access (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT))
#define PNE_replay_event_L2_load_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT)  + (1<<PEBS_L2_MISS_BIT))
#define PNE_replay_event_L2_data_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT) + (1<<PEBS_L2_MISS_BIT))
#define PNE_instr_retired_non_bogus (NATIVE_MASK + (P4_instr_retired<<16) + (1<<NBOGUSNTAG) + (1<<NBOGUSTAG))
#define PNE_instr_retired_all (NATIVE_MASK + (P4_instr_retired<<16) + (1<<NBOGUSNTAG) + (1<<NBOGUSTAG) + (1<<BOGUSNTAG) + (1<<BOGUSTAG))

/*
   PAPI preset events are defined in the tables below.
   Each entry consists of a PAPI name, derived info, and up to eight native event indexes
   as defined above.
   Events that require tagging should be ordered such that the
   first event is the one that is read. See PAPI_FP_INS for an example.
*/

const hwi_search_t _papi_hwd_pentium4_mlt2_preset_map[] = {
/* preset, derived, native index array */
   {PAPI_RES_STL, {0, {PNE_replay_event, PAPI_NULL,}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_branch_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_branch_retired_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_NTK, {0, {PNE_branch_retired_not_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_branch_retired_mispredicted, PAPI_NULL,}, {0,}}},
   {PAPI_BR_PRC, {0, {PNE_branch_retired_predicted, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_page_walk_type_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_page_walk_type_instr_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_TL, {0, {PNE_page_walk_type_all, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_instr_retired_non_bogus, PAPI_NULL,}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   /* Initial definition of FP_OPS identical to FP_INS. Could this be tweaked for SSE? */
   {PAPI_FP_OPS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_cycles, PAPI_NULL,}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_replay_event_L1_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L1_STM,  {0, { PNE_replay_event_L1_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L1_DCM, {0, {PNE_replay_event_L1_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_L2_LDM, {0, {PNE_replay_event_L2_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L2_STM,  {0, { PNE_replay_event_L2_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L2_DCM, {0, {PNE_replay_event_L2_data_miss, PAPI_NULL,}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

const hwi_search_t _papi_hwd_pentium4_mge2_preset_map[] = {
/* preset, derived, native index array */
   {PAPI_RES_STL, {0, {PNE_replay_event, PAPI_NULL,}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_branch_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_branch_retired_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_NTK, {0, {PNE_branch_retired_not_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_branch_retired_mispredicted, PAPI_NULL,}, {0,}}},
   {PAPI_BR_PRC, {0, {PNE_branch_retired_predicted, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_page_walk_type_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_page_walk_type_instr_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_TL, {0, {PNE_page_walk_type_all, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_instr_retired_non_bogus, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_instr_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   /* Initial definition of FP_OPS identical to FP_INS. Could this be tweaked for SSE? */
   {PAPI_FP_OPS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_cycles, PAPI_NULL,}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_replay_event_L1_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L1_STM,  {0, { PNE_replay_event_L1_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L1_DCM, {0, {PNE_replay_event_L1_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_replay_event_L1_data_access, PAPI_NULL,}, {0,}}},
   {PAPI_L2_LDM, {0, {PNE_replay_event_L2_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L2_STM,  {0, { PNE_replay_event_L2_store_miss, PAPI_NULL,},{0,}}},<commit_msg>Added a definition for PAPI_VEC_INS. Now we need a program to test it...<commit_after>/* 
* File:    p4_native.c
* CVS:     $Id$
* Author:  <NAME>
*          <EMAIL>
* Mods:    <your name here>
*          <your email address>
*/

#ifdef _WIN32
  /* Define SUBSTRATE to map to linux-perfctr.h
   * since we haven't figured out how to assign a value 
   * to a label at make inside the Windows IDE */
#define SUBSTRATE "linux-perfctr.h"
#endif

#include "papi.h"
#include SUBSTRATE
#include "papi_preset.h"
#include "papi_internal.h"
#include "papi_protos.h"


#ifdef __i386__
/*
    Native event index structure:

   +----------+--------+----------------+
   |0100000000| event  |      mask      |
   +----------+--------+----------------+
    31   -  24 23 -- 16 15    ----      0
*/


/*  Definitions of the virtual indexes of all P4 native events used in the preset tables.
    To create a new native event index, make up an appropriate name (used only internally);
    the definition for the name consists of:
    - the NATIVE_MASK bit;
    - one of the event group names from the enum table in p4_events.h, shifted to the 3rd byte;
    - any required mask bits from that event group, shifted into position;
      valid mask bits for each group are defined in p4_events.h

   Definitive descriptions of the event groups can be found in:
    IA32 Intel Arch. SW. Dev. Man. V3: Appendix A, Table A-1
    Order Number 245472-012, 2003.
*/

#define PNE_branch_retired_all (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMNM) + (1<<MMTP) + (1<<MMTM))
#define PNE_branch_retired_not_taken (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMNM))
#define PNE_branch_retired_taken (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTP) + (1<<MMTM))
#define PNE_branch_retired_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP) + (1<<MMTP))
#define PNE_branch_retired_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNM) + (1<<MMTM))
#define PNE_branch_retired_not_taken_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNP))
#define PNE_branch_retired_taken_predicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTP))
#define PNE_branch_retired_taken_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMTM))
#define PNE_branch_retired_not_taken_mispredicted (NATIVE_MASK + (P4_branch_retired<<16) + (1<<MMNM))
#define PNE_cycles (NATIVE_MASK + (P4_custom_event<<16) + 0)    // this is the first custom entry
#define PNE_page_walk_type_data_miss (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<DTMISS))
#define PNE_page_walk_type_instr_miss (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<ITMISS))
#define PNE_page_walk_type_all (NATIVE_MASK + (P4_page_walk_type<<16) + (1<<DTMISS) + (1<<ITMISS))
#define PNE_x87_FP_uop_tag0 (NATIVE_MASK + (P4_x87_FP_uop<<16) + (1<<TAG0) + (1<<ALL))
#define PNE_64bit_MMX_uop_tag1 (NATIVE_MASK + (P4_64bit_MMX_uop<<16) + (1<<TAG1) + (1<<ALL))
#define PNE_128bit_MMX_uop_tag1 (NATIVE_MASK + (P4_128bit_MMX_uop<<16) + (1<<TAG1) + (1<<ALL))
#define PNE_execution_event_nbogus0 (NATIVE_MASK + (P4_execution_event<<16) + (1<<NBOGUS0))
#define PNE_execution_event_nbogus1 (NATIVE_MASK + (P4_execution_event<<16) + (1<<NBOGUS1))
#define PNE_execution_event_nbogus2 (NATIVE_MASK + (P4_execution_event<<16) + (1<<NBOGUS2))
#define PNE_execution_event_nbogus3 (NATIVE_MASK + (P4_execution_event<<16) + (1<<NBOGUS3))
#define PNE_replay_event (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS))
#define PNE_replay_event_L1_load_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT)  + (1<<PEBS_L1_MISS_BIT))
#define PNE_replay_event_L1_data_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT) + (1<<PEBS_L1_MISS_BIT))
#define PNE_replay_event_L1_data_access (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT))
#define PNE_replay_event_L2_load_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT)  + (1<<PEBS_L2_MISS_BIT))
#define PNE_replay_event_L2_data_miss (NATIVE_MASK + (P4_replay_event<<16) + (1<<NBOGUS) + (1<<PEBS_MV_LOAD_BIT) + (1<<PEBS_MV_STORE_BIT) + (1<<PEBS_L2_MISS_BIT))
#define PNE_instr_retired_non_bogus (NATIVE_MASK + (P4_instr_retired<<16) + (1<<NBOGUSNTAG) + (1<<NBOGUSTAG))
#define PNE_instr_retired_all (NATIVE_MASK + (P4_instr_retired<<16) + (1<<NBOGUSNTAG) + (1<<NBOGUSTAG) + (1<<BOGUSNTAG) + (1<<BOGUSTAG))

/*
   PAPI preset events are defined in the tables below.
   Each entry consists of a PAPI name, derived info, and up to eight native event indexes
   as defined above.
   Events that require tagging should be ordered such that the
   first event is the one that is read. See PAPI_FP_INS for an example.
*/

const hwi_search_t _papi_hwd_pentium4_mlt2_preset_map[] = {
/* preset, derived, native index array */
   {PAPI_RES_STL, {0, {PNE_replay_event, PAPI_NULL,}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_branch_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_branch_retired_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_NTK, {0, {PNE_branch_retired_not_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_branch_retired_mispredicted, PAPI_NULL,}, {0,}}},
   {PAPI_BR_PRC, {0, {PNE_branch_retired_predicted, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_page_walk_type_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_page_walk_type_instr_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_TL, {0, {PNE_page_walk_type_all, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_instr_retired_non_bogus, PAPI_NULL,}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   /* Initial definition of FP_OPS identical to FP_INS. Could this be tweaked for SSE? */
   {PAPI_FP_OPS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   {PAPI_VEC_INS, {0, {PNE_execution_event_nbogus1, PNE_64bit_MMX_uop_tag1, PNE_128bit_MMX_uop_tag1, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_cycles, PAPI_NULL,}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_replay_event_L1_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L1_STM,  {0, { PNE_replay_event_L1_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L1_DCM, {0, {PNE_replay_event_L1_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_L2_LDM, {0, {PNE_replay_event_L2_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L2_STM,  {0, { PNE_replay_event_L2_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L2_DCM, {0, {PNE_replay_event_L2_data_miss, PAPI_NULL,}, {0,}}},
   {0, {0, {0,}, {0,}}}
};

const hwi_search_t _papi_hwd_pentium4_mge2_preset_map[] = {
/* preset, derived, native index array */
   {PAPI_RES_STL, {0, {PNE_replay_event, PAPI_NULL,}, {0,}}},
   {PAPI_BR_INS, {0, {PNE_branch_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_BR_TKN, {0, {PNE_branch_retired_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_NTK, {0, {PNE_branch_retired_not_taken, PAPI_NULL,}, {0,}}},
   {PAPI_BR_MSP, {0, {PNE_branch_retired_mispredicted, PAPI_NULL,}, {0,}}},
   {PAPI_BR_PRC, {0, {PNE_branch_retired_predicted, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_DM, {0, {PNE_page_walk_type_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_IM, {0, {PNE_page_walk_type_instr_miss, PAPI_NULL,}, {0,}}},
   {PAPI_TLB_TL, {0, {PNE_page_walk_type_all, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_INS, {0, {PNE_instr_retired_non_bogus, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_IIS, {0, {PNE_instr_retired_all, PAPI_NULL,}, {0,}}},
   {PAPI_FP_INS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   /* Initial definition of FP_OPS identical to FP_INS. Could this be tweaked for SSE? */
   {PAPI_FP_OPS, {0, {PNE_execution_event_nbogus0, PNE_x87_FP_uop_tag0, PAPI_NULL,}, {0,}}},
   {PAPI_VEC_INS, {0, {PNE_execution_event_nbogus1, PNE_64bit_MMX_uop_tag1, PNE_128bit_MMX_uop_tag1, PAPI_NULL,}, {0,}}},
   {PAPI_TOT_CYC, {0, {PNE_cycles, PAPI_NULL,}, {0,}}},
   {PAPI_L1_LDM, {0, {PNE_replay_event_L1_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L1_STM,  {0, { PNE_replay_event_L1_store_miss, PAPI_NULL,},{0,}}},
   {PAPI_L1_DCM, {0, {PNE_replay_event_L1_data_miss, PAPI_NULL,}, {0,}}},
   {PAPI_L1_DCA, {0, {PNE_replay_event_L1_data_access, PAPI_NULL,}, {0,}}},
   {PAPI_L2_LDM, {0, {PNE_replay_event_L2_load_miss, PAPI_NULL,}, {0,}}},
//  {PAPI_L2_STM,  {0, { PNE_replay_event_L2_store_miss, PAPI_NULL,},{0,}}},
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