<commit_before>/*
 * Blackfin CPLB initialization
 *
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>

#define CPLB_MEM CONFIG_MAX_MEM_SIZE

/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* possibly 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)

/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)


u_long icplb_table[MAX_CPLBS + 1];
u_long dcplb_table[MAX_CPLBS + 1];

#ifdef CONFIG_CPLB_SWITCH_TAB_L1
# define PDT_ATTR __attribute__((l1_data))
#else
# define PDT_ATTR
#endif

u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;

#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
#endif

struct s_cplb {
	struct cplb_tab init_i;
	struct cplb_tab init_d;
	struct cplb_tab switch_i;
	struct cplb_tab switch_d;
};

#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
static struct cplb_desc cplb_data[] = {
	{
		.start = 0,
		.end = SIZE_1K,
		.psize = SIZE_1K,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_OOPS,
		.d_conf = SDRAM_OOPS,
#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "Zero Pointer Guard Page",
	},
	{
		.start = L1_CODE_START,
		.end = L1_CODE_START + L1_CODE_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | I_CPLB,
		.i_conf = L1_IMEMORY,
		.d_conf = 0,
		.valid = 1,
		.name = "L1 I-Memory",
	},
	{
		.start = L1_DATA_A_START,
		.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = 0,
		.d_conf = L1_DMEMORY,
#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "L1 D-Memory",
	},
	{
		.start = 0,
		.end = 0,  /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "Kernel Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "uClinux MTD Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0,   /* dynamic */
		.psize = SIZE_1M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "Uncached DMA Zone",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.i_conf = 0, /* dynamic */
		.d_conf = 0, /* dynamic */
		.valid = 1,
		.name = "Reserved Memory",
	},
	{
		.start = ASYNC_BANK0_BASE,
		.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.d_conf = SDRAM_EBIU,
		.valid = 1,
		.name = "Asynchronous Memory Banks",
	},
	{
		.start = L2_START,
		.end = L2_START + L2_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = L2_IMEMORY,
		.d_conf = L2_DMEMORY,
		.valid = (L2_LENGTH > 0),
		.name = "L2 Memory",
	},
	{
		.start = BOOT_ROM_START,
		.end = BOOT_ROM_START + BOOT_ROM_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "On-Chip BootROM",
	},
};

static u16 __init lock_kernel_check(u32 start, u32 end)
{
	if ((end   <= (u32) _end && end   >= (u32)_stext) ||
	    (start <= (u32) _end && start >= (u32)_stext))
		return IN_KERNEL;
	return 0;
}

static unsigned short __init
fill_cplbtab(struct cplb_tab *table,<commit_msg>Blackfin arch: fix bug - Fail to boot jffs2 kernel for BF561 with SMP patch<commit_after>/*
 * Blackfin CPLB initialization
 *
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>

#define CPLB_MEM CONFIG_MAX_MEM_SIZE

/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 16 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Data Memory
* possibly 1 for L2 Data Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)

/*
* Number of required instruction CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* approx 12 for smaller 1MB page size CPLBs for allignment purposes
* 1 for L1 Instruction Memory
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)


u_long icplb_table[MAX_CPLBS + 1];
u_long dcplb_table[MAX_CPLBS + 1];

#ifdef CONFIG_CPLB_SWITCH_TAB_L1
# define PDT_ATTR __attribute__((l1_data))
#else
# define PDT_ATTR
#endif

u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;

#ifdef CONFIG_CPLB_INFO
u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
#endif

struct s_cplb {
	struct cplb_tab init_i;
	struct cplb_tab init_d;
	struct cplb_tab switch_i;
	struct cplb_tab switch_d;
};

#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
static struct cplb_desc cplb_data[] = {
	{
		.start = 0,
		.end = SIZE_1K,
		.psize = SIZE_1K,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_OOPS,
		.d_conf = SDRAM_OOPS,
#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "Zero Pointer Guard Page",
	},
	{
		.start = L1_CODE_START,
		.end = L1_CODE_START + L1_CODE_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | I_CPLB,
		.i_conf = L1_IMEMORY,
		.d_conf = 0,
		.valid = 1,
		.name = "L1 I-Memory",
	},
	{
		.start = L1_DATA_A_START,
		.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
		.psize = SIZE_4M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = 0,
		.d_conf = L1_DMEMORY,
#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
		.valid = 1,
#else
		.valid = 0,
#endif
		.name = "L1 D-Memory",
	},
	{
		.start = 0,
		.end = 0,  /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "Kernel Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "uClinux MTD Memory",
	},
	{
		.start = 0, /* dynamic */
		.end = 0,   /* dynamic */
		.psize = SIZE_1M,
		.attr = INITIAL_T | SWITCH_T | D_CPLB,
		.d_conf = SDRAM_DNON_CHBL,
		.valid = 1,
		.name = "Uncached DMA Zone",
	},
	{
		.start = 0, /* dynamic */
		.end = 0, /* dynamic */
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.i_conf = 0, /* dynamic */
		.d_conf = 0, /* dynamic */
		.valid = 1,
		.name = "Reserved Memory",
	},
	{
		.start = ASYNC_BANK0_BASE,
		.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
		.psize = 0,
		.attr = SWITCH_T | D_CPLB,
		.d_conf = SDRAM_EBIU,
		.valid = 1,
		.name = "Asynchronous Memory Banks",
	},
	{
		.start = L2_START,
		.end = L2_START + L2_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = L2_IMEMORY,
		.d_conf = L2_DMEMORY,
		.valid = (L2_LENGTH > 0),
		.name = "L2 Memory",
	},
	{
		.start = BOOT_ROM_START,
		.end = BOOT_ROM_START + BOOT_ROM_LENGTH,
		.psize = SIZE_1M,
		.attr = SWITCH_T | I_CPLB | D_CPLB,
		.i_conf = SDRAM_IGENERIC,
		.d_conf = SDRAM_DGENERIC,
		.valid = 1,
		.name = "On-Chip BootROM",
	},
};

static u16 __init lock_kernel_check(u32 start, u32 end)
{
	if (start >= (u32)_end || end <= (u32)_stext)
		return 0;

	/* This cplb block overlapped with kernel area. */
	return IN_KERNEL;
}

static unsigned short __init
fill_cplbtab(struct cplb_tab *table,
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