<commit_before>#include "dcpu.hpp"
#include "dcpu_opcodes.hpp"

#include <algorithm>
#include <sstream>
#include <iomanip>

#include <assert.h>

namespace cpu {


/// Checks if a OpCode is a Branch instrucction
#define IS_CONDITIONAL(x) ((x) >= IFB && (x) <= IFU)

#define PUSH (--rsp)    /// Push the stack
#define POP (rsp++)     /// Pop the stack


DCPU::DCPU()
{
    ram = new uint16_t[RAM_SIZE];
    attached_hardware.reserve (100); // Reserve space for some logical small qty
    reset();
}

DCPU::~DCPU()
{
    delete[] ram;
}

void DCPU::reset()
{
    std::fill_n (ram, RAM_SIZE, 0);
    ra = rb = rc = rx = ry = rz = ri = rj = rex = rsp = ria = rpc = 0;
    
    int_queueing = skipping_flag = on_fire = false;
    wait_cycles = tot_cycles = 0;
    
}

void DCPU::loadProgram (const uint16_t* prog, int size, int offset)
{
    assert (prog != NULL);
    assert (size > 0);
    assert (offset >= 0);
    assert (offset + size < 	UINT16_MAX);
    
    std::copy_n (prog, size, ram + offset);
    
}

bool DCPU::tick()
{

    tot_cycles++;
    if (wait_cycles <= 0) {
        wait_cycles = realStep();
        tickHardware();
        return true;
    }
    
    wait_cycles--;
    
    tickHardware();
    return false;
}

int DCPU::step() {
    int i, cycles = realStep();
    i = cycles;
    while (i-- > 0)
        tickHardware();

    tot_cycles += cycles;
    return cycles;
}

/**
 * @brief Executes a DCPU instrucction (real function)
 * @return Number of cycles that the DCPU need to do it
 */
int DCPU::realStep()
{
    int cycles = 0;
    
    uint16_t *a = NULL, *b = NULL;
    int16_t sa, sb;   	// Signed versions
    uint_fast32_t tmp_result;
    uint16_t tmp_a;			// Used by Literal values
    uint_fast16_t old_sp = rsp;
    
    opword* op = (opword*) (ram + (rpc++) );
    
    // TODO Move skiing here and use a table to precalculate instrucction 
    //      long for skining
    
    switch (op->basic.a) {
        // registers, direct:
    case REG_A:
        a = &ra;
        break;
        
    case REG_B:
        a = &rb;
        break;
        
    case REG_C:
        a = &rc;
        break;
        
    case REG_X:
        a = &rx;<commit_msg>Set to register some variable trying to improve performance<commit_after>#include "dcpu.hpp"
#include "dcpu_opcodes.hpp"

#include <algorithm>
#include <sstream>
#include <iomanip>

#include <assert.h>

namespace cpu {


/// Checks if a OpCode is a Branch instrucction
#define IS_CONDITIONAL(x) ((x) >= IFB && (x) <= IFU)

#define PUSH (--rsp)    /// Push the stack
#define POP (rsp++)     /// Pop the stack


DCPU::DCPU()
{
    ram = new uint16_t[RAM_SIZE];
    attached_hardware.reserve (100); // Reserve space for some logical small qty
    reset();
}

DCPU::~DCPU()
{
    delete[] ram;
}

void DCPU::reset()
{
    std::fill_n (ram, RAM_SIZE, 0);
    ra = rb = rc = rx = ry = rz = ri = rj = rex = rsp = ria = rpc = 0;
    
    int_queueing = skipping_flag = on_fire = false;
    wait_cycles = tot_cycles = 0;
    
}

void DCPU::loadProgram (const uint16_t* prog, int size, int offset)
{
    assert (prog != NULL);
    assert (size > 0);
    assert (offset >= 0);
    assert (offset + size < 	UINT16_MAX);
    
    std::copy_n (prog, size, ram + offset);
    
}

bool DCPU::tick()
{

    tot_cycles++;
    if (wait_cycles <= 0) {
        wait_cycles = realStep();
        tickHardware();
        return true;
    }
    
    wait_cycles--;
    
    tickHardware();
    return false;
}

int DCPU::step() {
    int i, cycles = realStep();
    i = cycles;
    while (i-- > 0)
        tickHardware();

    tot_cycles += cycles;
    return cycles;
}

/**
 * @brief Executes a DCPU instrucction (real function)
 * @return Number of cycles that the DCPU need to do it
 */
int DCPU::realStep()
{
    int cycles = 0;
    
    register uint16_t *a = NULL, *b = NULL;
    register int16_t sa, sb;   	// Signed versions
    register uint_fast32_t tmp_result;
    register uint16_t tmp_a;			// Used by Literal values
    uint_fast16_t old_sp = rsp;
    
    opword* op = (opword*) (ram + (rpc++) );
    
    // TODO Move skiing here and use a table to precalculate instrucction 
    //      long for skining
    
    switch (op->basic.a) {
        // registers, direct:
    case REG_A:
        a = &ra;
        break;
        
    case REG_B:
        a = &rb;
        break;
        
    case REG_C:
        a = &rc;
        break;
        
    case REG_X:
        a = &rx;
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