<commit_before>module X86.Regs (
	-- squeese functions for the graph allocator
	virtualRegSqueeze,
	realRegSqueeze,

	-- immediates
	Imm(..),
	strImmLit,
	litToImm,

	-- addressing modes
	AddrMode(..),
	addrOffset,

	-- registers
	spRel,
	argRegs,
	allArgRegs,
	callClobberedRegs,
	allMachRegNos,
	classOfRealReg,
	showReg,	

	-- machine specific
	EABase(..), EAIndex(..), addrModeRegs,

	eax, ebx, ecx, edx, esi, edi, ebp, esp,
	fake0, fake1, fake2, fake3, fake4, fake5, firstfake,

	rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
	r8,  r9,  r10, r11, r12, r13, r14, r15,
  	xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
  	xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
	xmm,

	ripRel,
	allFPArgRegs,

	-- horror show
	freeReg,
	globalRegMaybe,
	
	allocatableRegs
)

where

#include "nativeGen/NCG.h"
#include "HsVersions.h"

#include "../includes/stg/MachRegs.h"

import Reg
import RegClass

import BlockId
import Cmm
import CLabel           ( CLabel )
import Pretty
import Outputable	( panic )
import FastTypes
import FastBool


#if  defined(i386_TARGET_ARCH) || defined(x86_64_TARGET_ARCH)
import Constants
#endif


-- | regSqueeze_class reg
--	Calculuate the maximum number of register colors that could be
--	denied to a node of this class due to having this reg 
--	as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt

virtualRegSqueeze cls vr
 = case cls of
 	RcInteger
	 -> case vr of
	 	VirtualRegI{}		-> _ILIT(1)
		VirtualRegHi{}		-> _ILIT(1)
                _other                  -> _ILIT(0)

	RcDouble
	 -> case vr of
		VirtualRegD{}		-> _ILIT(1)
		VirtualRegF{}		-> _ILIT(0)
                _other                  -> _ILIT(0)

	RcDoubleSSE
	 -> case vr of
		VirtualRegSSE{}		-> _ILIT(1)
                _other                  -> _ILIT(0)

        _other -> _ILIT(0)

{-# INLINE realRegSqueeze #-}
realRegSqueeze :: RegClass -> RealReg -> FastInt
realRegSqueeze cls rr
 = case cls of
 	RcInteger
	 -> case rr of
	 	RealRegSingle regNo
			| regNo	< firstfake -> _ILIT(1)
			| otherwise	-> _ILIT(0)
			
		RealRegPair{}		-> _ILIT(0)

	RcDouble
	 -> case rr of
	 	RealRegSingle regNo
			| regNo >= firstfake && regNo < lastfake -> _ILIT(1)
			| otherwise	-> _ILIT(0)
			
		RealRegPair{}		-> _ILIT(0)

        RcDoubleSSE
	 -> case rr of
	 	RealRegSingle regNo | regNo >= firstxmm -> _ILIT(1)<commit_msg>NCG: Fix off-by-one error in realRegSqueeze<commit_after>module X86.Regs (
	-- squeese functions for the graph allocator
	virtualRegSqueeze,
	realRegSqueeze,

	-- immediates
	Imm(..),
	strImmLit,
	litToImm,

	-- addressing modes
	AddrMode(..),
	addrOffset,

	-- registers
	spRel,
	argRegs,
	allArgRegs,
	callClobberedRegs,
	allMachRegNos,
	classOfRealReg,
	showReg,	

	-- machine specific
	EABase(..), EAIndex(..), addrModeRegs,

	eax, ebx, ecx, edx, esi, edi, ebp, esp,
	fake0, fake1, fake2, fake3, fake4, fake5, firstfake,

	rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
	r8,  r9,  r10, r11, r12, r13, r14, r15,
  	xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
  	xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
	xmm,

	ripRel,
	allFPArgRegs,

	-- horror show
	freeReg,
	globalRegMaybe,
	
	allocatableRegs
)

where

#include "nativeGen/NCG.h"
#include "HsVersions.h"

#include "../includes/stg/MachRegs.h"

import Reg
import RegClass

import BlockId
import Cmm
import CLabel           ( CLabel )
import Pretty
import Outputable	( panic )
import FastTypes
import FastBool


#if  defined(i386_TARGET_ARCH) || defined(x86_64_TARGET_ARCH)
import Constants
#endif


-- | regSqueeze_class reg
--	Calculuate the maximum number of register colors that could be
--	denied to a node of this class due to having this reg 
--	as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt

virtualRegSqueeze cls vr
 = case cls of
 	RcInteger
	 -> case vr of
	 	VirtualRegI{}		-> _ILIT(1)
		VirtualRegHi{}		-> _ILIT(1)
                _other                  -> _ILIT(0)

	RcDouble
	 -> case vr of
		VirtualRegD{}		-> _ILIT(1)
		VirtualRegF{}		-> _ILIT(0)
                _other                  -> _ILIT(0)

	RcDoubleSSE
	 -> case vr of
		VirtualRegSSE{}		-> _ILIT(1)
                _other                  -> _ILIT(0)

        _other -> _ILIT(0)

{-# INLINE realRegSqueeze #-}
realRegSqueeze :: RegClass -> RealReg -> FastInt
realRegSqueeze cls rr
 = case cls of
 	RcInteger
	 -> case rr of
	 	RealRegSingle regNo
			| regNo	< firstfake -> _ILIT(1)
			| otherwise	-> _ILIT(0)
			
		RealRegPair{}		-> _ILIT(0)

	RcDouble
	 -> case rr of
	 	RealRegSingle regNo
			| regNo >= firstfake && regNo <= lastfake -> _ILIT(1)
			| otherwise	-> _ILIT(0)
			
		RealRegPair{}		-> _ILIT(0)

        RcDoubleSSE
	 -> case rr of
	 	RealRegSingle regNo | regNo >= firstxmm -> _ILIT(1)
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