<commit_before>//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the MachineInstr class, which is the
// basic representation for all target dependent machine instructions used by
// the back end.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H

#include "Support/Annotation.h"
#include "Support/iterator"
#include <vector>

namespace llvm {

class Value;
class Function;
class MachineBasicBlock;
class TargetMachine;
class GlobalValue;

template <typename T> class ilist_traits;

typedef int MachineOpCode;

//===----------------------------------------------------------------------===//
/// MOTy - MachineOperandType - This namespace contains an enum that describes
/// how the machine operand is used by the instruction: is it read, defined, or
/// both?  Note that the MachineInstr/Operator class currently uses bool
/// arguments to represent this information instead of an enum.  Eventually this
/// should change over to use this _easier to read_ representation instead.
///
namespace MOTy {
  enum UseType {
    Use,             /// This machine operand is only read by the instruction
    Def,             /// This machine operand is only written by the instruction
    UseAndDef        /// This machine operand is read AND written
  };
}

//===----------------------------------------------------------------------===//
// class MachineOperand 
// 
// Purpose:
//   Representation of each machine instruction operand.
//   This class is designed so that you can allocate a vector of operands
//   first and initialize each one later.
//
//   E.g, for this VM instruction:
//		ptr = alloca type, numElements
//   we generate 2 machine instructions on the SPARC:
// 
//		mul Constant, Numelements -> Reg
//		add %sp, Reg -> Ptr
// 
//   Each instruction has 3 operands, listed above.  Of those:
//   -	Reg, NumElements, and Ptr are of operand type MO_Register.
//   -	Constant is of operand type MO_SignExtendedImmed on the SPARC.
//	
//   For the register operands, the virtual register type is as follows:
//	
//   -  Reg will be of virtual register type MO_MInstrVirtualReg.  The field
//	MachineInstr* minstr will point to the instruction that computes reg.
// 
//   -	%sp will be of virtual register type MO_MachineReg.
//	The field regNum identifies the machine register.
// 
//   -	NumElements will be of virtual register type MO_VirtualReg.
//	The field Value* value identifies the value.
// 
//   -	Ptr will also be of virtual register type MO_VirtualReg.
//	Again, the field Value* value identifies the value.
// 
//===----------------------------------------------------------------------===//

struct MachineOperand {
  enum MachineOperandType {
    MO_VirtualRegister,		// virtual register for *value
    MO_MachineRegister,		// pre-assigned machine register `regNum'
    MO_CCRegister,
    MO_SignExtendedImmed,
    MO_UnextendedImmed,
    MO_PCRelativeDisp,
    MO_MachineBasicBlock,       // MachineBasicBlock reference
    MO_FrameIndex,              // Abstract Stack Frame Index
    MO_ConstantPoolIndex,       // Address of indexed Constant in Constant Pool
    MO_ExternalSymbol,          // Name of external global symbol
    MO_GlobalAddress,           // Address of a global value
  };
  
private:
  // Bit fields of the flags variable used for different operand properties
  enum {
    DEFFLAG     = 0x01,       // this is a def of the operand
    USEFLAG     = 0x02,       // this is a use of the operand
    HIFLAG32    = 0x04,       // operand is %hi32(value_or_immedVal)
    LOFLAG32    = 0x08,       // operand is %lo32(value_or_immedVal)
    HIFLAG64    = 0x10,       // operand is %hi64(value_or_immedVal)
    LOFLAG64    = 0x20,       // operand is %lo64(value_or_immedVal)
    PCRELATIVE  = 0x40,       // Operand is relative to PC, not a global address
  };

private:
  union {
    Value*	value;		// BasicBlockVal for a label operand.
				// ConstantVal for a non-address immediate.
				// Virtual register for an SSA operand,
				//   including hidden operands required for
				//   the generated machine code.     
                                // LLVM global for MO_GlobalAddress.

    int64_t immedVal;		// Constant value for an explicit constant

    MachineBasicBlock *MBB;     // For MO_MachineBasicBlock type
    std::string *SymbolName;    // For MO_ExternalSymbol type
  };

  char flags;                   // see bit field definitions above
  MachineOperandType opType:8;  // Pack into 8 bits efficiently after flags.
  int regNum;	                // register number for an explicit register
                                // will be set for a value after reg allocation
private:
  MachineOperand()
    : immedVal(0),
      flags(0),
      opType(MO_VirtualRegister),
      regNum(-1) {}

  MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
    : immedVal(ImmVal),
      flags(0),
      opType(OpTy),
      regNum(-1) {}

  MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
    : immedVal(0),
      opType(OpTy),
      regNum(Reg) {
    switch (UseTy) {
    case MOTy::Use:       flags = USEFLAG; break;
    case MOTy::Def:       flags = DEFFLAG; break;
    case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
    default: assert(0 && "Invalid value for UseTy!");
    }
  }

  MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
		 bool isPCRelative = false)<commit_msg>Express one of MachineOperand's many constructors in terms of another, by means of default arguments.<commit_after>//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the MachineInstr class, which is the
// basic representation for all target dependent machine instructions used by
// the back end.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H

#include "Support/Annotation.h"
#include "Support/iterator"
#include <vector>

namespace llvm {

class Value;
class Function;
class MachineBasicBlock;
class TargetMachine;
class GlobalValue;

template <typename T> class ilist_traits;

typedef int MachineOpCode;

//===----------------------------------------------------------------------===//
/// MOTy - MachineOperandType - This namespace contains an enum that describes
/// how the machine operand is used by the instruction: is it read, defined, or
/// both?  Note that the MachineInstr/Operator class currently uses bool
/// arguments to represent this information instead of an enum.  Eventually this
/// should change over to use this _easier to read_ representation instead.
///
namespace MOTy {
  enum UseType {
    Use,             /// This machine operand is only read by the instruction
    Def,             /// This machine operand is only written by the instruction
    UseAndDef        /// This machine operand is read AND written
  };
}

//===----------------------------------------------------------------------===//
// class MachineOperand 
// 
// Purpose:
//   Representation of each machine instruction operand.
//   This class is designed so that you can allocate a vector of operands
//   first and initialize each one later.
//
//   E.g, for this VM instruction:
//		ptr = alloca type, numElements
//   we generate 2 machine instructions on the SPARC:
// 
//		mul Constant, Numelements -> Reg
//		add %sp, Reg -> Ptr
// 
//   Each instruction has 3 operands, listed above.  Of those:
//   -	Reg, NumElements, and Ptr are of operand type MO_Register.
//   -	Constant is of operand type MO_SignExtendedImmed on the SPARC.
//	
//   For the register operands, the virtual register type is as follows:
//	
//   -  Reg will be of virtual register type MO_MInstrVirtualReg.  The field
//	MachineInstr* minstr will point to the instruction that computes reg.
// 
//   -	%sp will be of virtual register type MO_MachineReg.
//	The field regNum identifies the machine register.
// 
//   -	NumElements will be of virtual register type MO_VirtualReg.
//	The field Value* value identifies the value.
// 
//   -	Ptr will also be of virtual register type MO_VirtualReg.
//	Again, the field Value* value identifies the value.
// 
//===----------------------------------------------------------------------===//

struct MachineOperand {
  enum MachineOperandType {
    MO_VirtualRegister,		// virtual register for *value
    MO_MachineRegister,		// pre-assigned machine register `regNum'
    MO_CCRegister,
    MO_SignExtendedImmed,
    MO_UnextendedImmed,
    MO_PCRelativeDisp,
    MO_MachineBasicBlock,       // MachineBasicBlock reference
    MO_FrameIndex,              // Abstract Stack Frame Index
    MO_ConstantPoolIndex,       // Address of indexed Constant in Constant Pool
    MO_ExternalSymbol,          // Name of external global symbol
    MO_GlobalAddress,           // Address of a global value
  };
  
private:
  // Bit fields of the flags variable used for different operand properties
  enum {
    DEFFLAG     = 0x01,       // this is a def of the operand
    USEFLAG     = 0x02,       // this is a use of the operand
    HIFLAG32    = 0x04,       // operand is %hi32(value_or_immedVal)
    LOFLAG32    = 0x08,       // operand is %lo32(value_or_immedVal)
    HIFLAG64    = 0x10,       // operand is %hi64(value_or_immedVal)
    LOFLAG64    = 0x20,       // operand is %lo64(value_or_immedVal)
    PCRELATIVE  = 0x40,       // Operand is relative to PC, not a global address
  };

private:
  union {
    Value*	value;		// BasicBlockVal for a label operand.
				// ConstantVal for a non-address immediate.
				// Virtual register for an SSA operand,
				//   including hidden operands required for
				//   the generated machine code.     
                                // LLVM global for MO_GlobalAddress.

    int64_t immedVal;		// Constant value for an explicit constant

    MachineBasicBlock *MBB;     // For MO_MachineBasicBlock type
    std::string *SymbolName;    // For MO_ExternalSymbol type
  };

  char flags;                   // see bit field definitions above
  MachineOperandType opType:8;  // Pack into 8 bits efficiently after flags.
  int regNum;	                // register number for an explicit register
                                // will be set for a value after reg allocation
private:
  MachineOperand(int64_t ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
    : immedVal(ImmVal),
      flags(0),
      opType(OpTy),
      regNum(-1) {}

  MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
    : immedVal(0),
      opType(OpTy),
      regNum(Reg) {
    switch (UseTy) {
    case MOTy::Use:       flags = USEFLAG; break;
    case MOTy::Def:       flags = DEFFLAG; break;
    case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
    default: assert(0 && "Invalid value for UseTy!");
    }
  }

  MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
		 bool isPCRelative = false)
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