<commit_before>/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(C) 2021 Marvell.
 */

#ifndef _CNXK_SE_H_
#define _CNXK_SE_H_
#include <stdbool.h>

#include "cnxk_cryptodev.h"
#include "cnxk_cryptodev_ops.h"

#define SRC_IOV_SIZE                                                           \
	(sizeof(struct roc_se_iov_ptr) +                                       \
	 (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))
#define DST_IOV_SIZE                                                           \
	(sizeof(struct roc_se_iov_ptr) +                                       \
	 (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))

struct cnxk_se_sess {
	uint16_t cpt_op : 4;
	uint16_t zsk_flag : 4;
	uint16_t aes_gcm : 1;
	uint16_t aes_ctr : 1;
	uint16_t chacha_poly : 1;
	uint16_t is_null : 1;
	uint16_t is_gmac : 1;
	uint16_t rsvd1 : 3;
	uint16_t aad_length;
	uint8_t mac_len;
	uint8_t iv_length;
	uint8_t auth_iv_length;
	uint16_t iv_offset;
	uint16_t auth_iv_offset;
	uint32_t salt;
	uint64_t cpt_inst_w7;
	struct roc_se_ctx roc_se_ctx;
} __rte_cache_aligned;

static __rte_always_inline int
cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)
{
	uint16_t mac_len = auth->digest_length;
	int ret;

	switch (auth->algo) {
	case RTE_CRYPTO_AUTH_MD5:
	case RTE_CRYPTO_AUTH_MD5_HMAC:
		ret = (mac_len == 16) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA1:
	case RTE_CRYPTO_AUTH_SHA1_HMAC:
		ret = (mac_len == 20) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA224:
	case RTE_CRYPTO_AUTH_SHA224_HMAC:
		ret = (mac_len == 28) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA256:
	case RTE_CRYPTO_AUTH_SHA256_HMAC:
		ret = (mac_len == 32) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA384:
	case RTE_CRYPTO_AUTH_SHA384_HMAC:
		ret = (mac_len == 48) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA512:
	case RTE_CRYPTO_AUTH_SHA512_HMAC:
		ret = (mac_len == 64) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_NULL:
		ret = 0;
		break;
	default:
		ret = -1;
	}

	return ret;
}

static __rte_always_inline void
cpt_fc_salt_update(struct roc_se_ctx *se_ctx, uint8_t *salt)
{
	struct roc_se_context *fctx = &se_ctx->se_ctx.fctx;
	memcpy(fctx->enc.encr_iv, salt, 4);
}

static __rte_always_inline uint32_t
fill_sg_comp(struct roc_se_sglist_comp *list, uint32_t i, phys_addr_t dma_addr,
	     uint32_t size)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];

	to->u.s.len[i % 4] = rte_cpu_to_be_16(size);
	to->ptr[i % 4] = rte_cpu_to_be_64(dma_addr);
	i++;
	return i;
}

static __rte_always_inline uint32_t
fill_sg_comp_from_buf(struct roc_se_sglist_comp *list, uint32_t i,
		      struct roc_se_buf_ptr *from)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];

	to->u.s.len[i % 4] = rte_cpu_to_be_16(from->size);
	to->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);
	i++;
	return i;
}

static __rte_always_inline uint32_t
fill_sg_comp_from_buf_min(struct roc_se_sglist_comp *list, uint32_t i,
			  struct roc_se_buf_ptr *from, uint32_t *psize)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];
	uint32_t size = *psize;
	uint32_t e_len;

	e_len = (size > from->size) ? from->size : size;
	to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
	to->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);
	*psize -= e_len;
	i++;
	return i;
}

/*
 * This fills the MC expected SGIO list
 * from IOV given by user.
 */
static __rte_always_inline uint32_t
fill_sg_comp_from_iov(struct roc_se_sglist_comp *list, uint32_t i,
		      struct roc_se_iov_ptr *from, uint32_t from_offset,
		      uint32_t *psize, struct roc_se_buf_ptr *extra_buf,
		      uint32_t extra_offset)
{
	int32_t j;
	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
	uint32_t size = *psize;
	struct roc_se_buf_ptr *bufs;

	bufs = from->bufs;
	for (j = 0; (j < from->buf_cnt) && size; j++) {
		uint64_t e_vaddr;
		uint32_t e_len;
		struct roc_se_sglist_comp *to = &list[i >> 2];

		if (unlikely(from_offset)) {
			if (from_offset >= bufs[j].size) {
				from_offset -= bufs[j].size;
				continue;
			}
			e_vaddr = (uint64_t)bufs[j].vaddr + from_offset;
			e_len = (size > (bufs[j].size - from_offset)) ?
					(bufs[j].size - from_offset) :
					size;
			from_offset = 0;
		} else {
			e_vaddr = (uint64_t)bufs[j].vaddr;
			e_len = (size > bufs[j].size) ? bufs[j].size : size;
		}

		to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
		to->ptr[i % 4] = rte_cpu_to_be_64(e_vaddr);

		if (extra_len && (e_len >= extra_offset)) {
			/* Break the data at given offset */
			uint32_t next_len = e_len - extra_offset;
			uint64_t next_vaddr = e_vaddr + extra_offset;

			if (!extra_offset) {
				i--;
			} else {
				e_len = extra_offset;
				size -= e_len;
				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
			}

			extra_len = RTE_MIN(extra_len, size);
			/* Insert extra data ptr */
			if (extra_len) {
				i++;
				to = &list[i >> 2];
				to->u.s.len[i % 4] =
					rte_cpu_to_be_16(extra_len);
				to->ptr[i % 4] = rte_cpu_to_be_64(
					(uint64_t)extra_buf->vaddr);
				size -= extra_len;
			}

			next_len = RTE_MIN(next_len, size);
			/* insert the rest of the data */
			if (next_len) {
				i++;
				to = &list[i >> 2];
				to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
				to->ptr[i % 4] = rte_cpu_to_be_64(next_vaddr);
				size -= next_len;
			}
			extra_len = 0;

		} else {
			size -= e_len;
		}
		if (extra_offset)
			extra_offset -= size;
		i++;
	}

	*psize = size;
	return (uint32_t)i;
}

static __rte_always_inline int
cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		  struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)
{
	uint32_t iv_offset = 0;
	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
	struct roc_se_ctx *se_ctx;
	uint32_t cipher_type, hash_type;
	uint32_t mac_len, size;
	uint8_t iv_len = 16;
	struct roc_se_buf_ptr *aad_buf = NULL;
	uint32_t encr_offset, auth_offset;
	uint32_t encr_data_len, auth_data_len, aad_len = 0;
	uint32_t passthrough_len = 0;
	union cpt_inst_w4 cpt_inst_w4;
	void *offset_vaddr;
	uint8_t op_minor;

	encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
	auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);
	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/* We don't support both AAD and auth data separately */
		auth_data_len = 0;
		auth_offset = 0;
		aad_len = fc_params->aad_buf.size;
		aad_buf = &fc_params->aad_buf;
	}
	se_ctx = fc_params->ctx_buf.vaddr;
	cipher_type = se_ctx->enc_cipher;
	hash_type = se_ctx->hash_type;
	mac_len = se_ctx->mac_len;
	op_minor = se_ctx->template_w4.s.opcode_minor;

	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
		iv_len = 0;
		iv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);
	}

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/*
		 * When AAD is given, data above encr_offset is pass through
		 * Since AAD is given as separate pointer and not as offset,
		 * this is a special case as we need to fragment input data
		 * into passthrough + encr_data and then insert AAD in between.
		 */
		if (hash_type != ROC_SE_GMAC_TYPE) {
			passthrough_len = encr_offset;
			auth_offset = passthrough_len + iv_len;
			encr_offset = passthrough_len + aad_len + iv_len;
			auth_data_len = aad_len + encr_data_len;
		} else {
			passthrough_len = 16 + aad_len;
			auth_offset = passthrough_len + iv_len;
			auth_data_len = aad_len;
		}
	} else {
		encr_offset += iv_len;
		auth_offset += iv_len;
	}

	/* Encryption */
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;
	cpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_ENCRYPT;
	cpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;

	if (hash_type == ROC_SE_GMAC_TYPE) {
		encr_offset = 0;
		encr_data_len = 0;
	}

	auth_dlen = auth_offset + auth_data_len;
	enc_dlen = encr_data_len + encr_offset;
	if (unlikely(encr_data_len & 0xf)) {
		if ((cipher_type == ROC_SE_DES3_CBC) ||
		    (cipher_type == ROC_SE_DES3_ECB))
			enc_dlen =
				RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;
		else if (likely((cipher_type == ROC_SE_AES_CBC) ||
				(cipher_type == ROC_SE_AES_ECB)))
			enc_dlen =
				RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;
	}

	if (unlikely(auth_dlen > enc_dlen)) {
		inputlen = auth_dlen;
		outputlen = auth_dlen + mac_len;
	} else {
		inputlen = enc_dlen;
		outputlen = enc_dlen + mac_len;
	}

	if (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)
		outputlen = enc_dlen;

	/* GP op header */
	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = fc_params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr =
			(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

	} else {
		void *m_vaddr = fc_params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;

		/* This falls under strict SG mode */
		offset_vaddr = m_vaddr;
		size = ROC_SE_OFF_CTRL_LEN + iv_len;

		m_vaddr = (uint8_t *)m_vaddr + size;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */

		i = 0;

		/* Offset control word that includes iv */
		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* Add input data */
		size = inputlen - iv_len;
		if (likely(size)) {
			uint32_t aad_offset = aad_len ? passthrough_len : 0;

			if (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {
				i = fill_sg_comp_from_buf_min(
					gather_comp, i, fc_params->bufs, &size);
			} else {
				i = fill_sg_comp_from_iov(
					gather_comp, i, fc_params->src_iov, 0,
					&size, aad_buf, aad_offset);
			}

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter list
		 */
		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* Add IV */
		if (likely(iv_len)) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* output data or output data + digest*/
		if (unlikely(flags & ROC_SE_VALID_MAC_BUF)) {
			size = outputlen - iv_len - mac_len;
			if (size) {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						scatter_comp, i,
						fc_params->bufs, &size);
				} else {
					i = fill_sg_comp_from_iov(
						scatter_comp, i,
						fc_params->dst_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
			/* mac_data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(scatter_comp, i,
							  &fc_params->mac_buf);
			}
		} else {
			/* Output including mac */
			size = outputlen - iv_len;
			if (likely(size)) {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						scatter_comp, i,
						fc_params->bufs, &size);
				} else {
					i = fill_sg_comp_from_iov(
						scatter_comp, i,
						fc_params->dst_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||
		     (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("iv_offset : %d", iv_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(
		((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |
		((uint64_t)auth_offset));

	inst->w4.u64 = cpt_inst_w4.u64;
	return 0;
}

static __rte_always_inline int
cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		  struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)
{
	uint32_t iv_offset = 0, size;
	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
	struct roc_se_ctx *se_ctx;
	int32_t hash_type, mac_len;
	uint8_t iv_len = 16;
	struct roc_se_buf_ptr *aad_buf = NULL;
	uint32_t encr_offset, auth_offset;
	uint32_t encr_data_len, auth_data_len, aad_len = 0;
	uint32_t passthrough_len = 0;
	union cpt_inst_w4 cpt_inst_w4;
	void *offset_vaddr;
	uint8_t op_minor;

	encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
	auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/* We don't support both AAD and auth data separately */
		auth_data_len = 0;
		auth_offset = 0;
		aad_len = fc_params->aad_buf.size;
		aad_buf = &fc_params->aad_buf;
	}

	se_ctx = fc_params->ctx_buf.vaddr;
	hash_type = se_ctx->hash_type;
	mac_len = se_ctx->mac_len;
	op_minor = se_ctx->template_w4.s.opcode_minor;

	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
		iv_len = 0;
		iv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);
	}

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/*
		 * When AAD is given, data above encr_offset is pass through
		 * Since AAD is given as separate pointer and not as offset,
		 * this is a special case as we need to fragment input data
		 * into passthrough + encr_data and then insert AAD in between.
		 */
		if (hash_type != ROC_SE_GMAC_TYPE) {
			passthrough_len = encr_offset;
			auth_offset = passthrough_len + iv_len;
			encr_offset = passthrough_len + aad_len + iv_len;
			auth_data_len = aad_len + encr_data_len;
		} else {
			passthrough_len = 16 + aad_len;
			auth_offset = passthrough_len + iv_len;
			auth_data_len = aad_len;
		}
	} else {
		encr_offset += iv_len;
		auth_offset += iv_len;
	}

	/* Decryption */
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;
	cpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_DECRYPT;
	cpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;

	if (hash_type == ROC_SE_GMAC_TYPE) {
		encr_offset = 0;
		encr_data_len = 0;
	}

	enc_dlen = encr_offset + encr_data_len;
	auth_dlen = auth_offset + auth_data_len;

	if (auth_dlen > enc_dlen) {
		inputlen = auth_dlen + mac_len;
		outputlen = auth_dlen;
	} else {
		inputlen = enc_dlen + mac_len;
		outputlen = enc_dlen;
	}

	if (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)
		outputlen = inputlen = enc_dlen;

	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = fc_params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr =
			(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

	} else {
		void *m_vaddr = fc_params->meta_buf.vaddr;
		uint32_t g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint8_t i = 0;

		/* This falls under strict SG mode */
		offset_vaddr = m_vaddr;
		size = ROC_SE_OFF_CTRL_LEN + iv_len;

		m_vaddr = (uint8_t *)m_vaddr + size;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word that includes iv */
		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* Add input data */
		if (flags & ROC_SE_VALID_MAC_BUF) {
			size = inputlen - iv_len - mac_len;
			if (size) {
				/* input data only */
				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						gather_comp, i, fc_params->bufs,
						&size);
				} else {
					uint32_t aad_offset =
						aad_len ? passthrough_len : 0;

					i = fill_sg_comp_from_iov(
						gather_comp, i,
						fc_params->src_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}

			/* mac data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(gather_comp, i,
							  &fc_params->mac_buf);
			}
		} else {
			/* input data + mac */
			size = inputlen - iv_len;
			if (size) {
				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						gather_comp, i, fc_params->bufs,
						&size);
				} else {
					uint32_t aad_offset =
						aad_len ? passthrough_len : 0;

					if (unlikely(!fc_params->src_iov)) {
						plt_dp_err("Bad input args");
						return -1;
					}

					i = fill_sg_comp_from_iov(
						gather_comp, i,
						fc_params->src_iov, 0, &size,
						aad_buf, aad_offset);
				}

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* Add iv */
		if (iv_len) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* Add output data */
		size = outputlen - iv_len;
		if (size) {
			if (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {
				/* handle single buffer here */
				i = fill_sg_comp_from_buf_min(scatter_comp, i,
							      fc_params->bufs,
							      &size);
			} else {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(!fc_params->dst_iov)) {
					plt_dp_err("Bad input args");
					return -1;
				}

				i = fill_sg_comp_from_iov(
					scatter_comp, i, fc_params->dst_iov, 0,
					&size, aad_buf, aad_offset);
			}

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}

		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||
		     (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("iv_offset : %d", iv_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(
		((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |
		((uint64_t)auth_offset));

	inst->w4.u64 = cpt_inst_w4.u64;
	return 0;
}

static __rte_always_inline int
cpt_zuc_snow3g_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
			struct roc_se_fc_params *params,
			struct cpt_inst_s *inst)
{
	uint32_t size;
	int32_t inputlen, outputlen;
	struct roc_se_ctx *se_ctx;
	uint32_t mac_len = 0;
	uint8_t pdcp_alg_type, j;
	uint32_t encr_offset = 0, auth_offset = 0;
	uint32_t encr_data_len = 0, auth_data_len = 0;
	int flags, iv_len = 16;
	uint64_t offset_ctrl;
	uint64_t *offset_vaddr;
	uint32_t *iv_s, iv[4];
	union cpt_inst_w4 cpt_inst_w4;

	se_ctx = params->ctx_buf.vaddr;
	flags = se_ctx->zsk_flags;
	mac_len = se_ctx->mac_len;
	pdcp_alg_type = se_ctx->pdcp_alg_type;

	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;

	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */

	cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |
				      (0 << 4) | (0 << 3) | (flags & 0x7));

	if (flags == 0x1) {
		/*
		 * Microcode expects offsets in bytes
		 * TODO: Rounding off
		 */
		auth_data_len = ROC_SE_AUTH_DLEN(d_lens);

		/* EIA3 or UIA2 */
		auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
		auth_offset = auth_offset / 8;

		/* consider iv len */
		auth_offset += iv_len;

		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
		outputlen = mac_len;

		offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);

	} else {
		/* EEA3 or UEA2 */
		/*
		 * Microcode expects offsets in bytes
		 * TODO: Rounding off
		 */
		encr_data_len = ROC_SE_ENCR_DLEN(d_lens);

		encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
		encr_offset = encr_offset / 8;
		/* consider iv len */
		encr_offset += iv_len;

		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
		outputlen = inputlen;

		/* iv offset is 0 */
		offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
	}

	if (unlikely((encr_offset >> 16) || (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	/* IV */
	iv_s = (flags == 0x1) ? params->auth_iv_buf : params->iv_buf;

	if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {
		/*
		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
		 */

		for (j = 0; j < 4; j++)
			iv[j] = iv_s[3 - j];
	} else {
		/* ZUC doesn't need a swap */
		for (j = 0; j < 4; j++)
			iv[j] = iv_s[j];
	}

	/*
	 * GP op header, lengths are expected in bits.
	 */
	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
					    ROC_SE_OFF_CTRL_LEN - iv_len);

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;
		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			memcpy(iv_d, iv, 16);
		}

		*offset_vaddr = offset_ctrl;
	} else {
		void *m_vaddr = params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint32_t *iv_d;

		/* save space for iv */
		offset_vaddr = m_vaddr;

		m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word followed by iv */

		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* iv offset is 0 */
		*offset_vaddr = offset_ctrl;

		iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
				    ROC_SE_OFF_CTRL_LEN);
		memcpy(iv_d, iv, 16);

		/* input data */
		size = inputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(gather_comp, i,
						  params->src_iov, 0, &size,
						  NULL, 0);
			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		if (flags == 0x1) {
			/* IV in SLIST only for EEA3 & UEA2 */
			iv_len = 0;
		}

		if (iv_len) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* Add output data */
		if (req_flags & ROC_SE_VALID_MAC_BUF) {
			size = outputlen - iv_len - mac_len;
			if (size) {
				i = fill_sg_comp_from_iov(scatter_comp, i,
							  params->dst_iov, 0,
							  &size, NULL, 0);

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer space,"
						   " size %d needed",
						   size);
					return -1;
				}
			}

			/* mac data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(scatter_comp, i,
							  &params->mac_buf);
			}
		} else {
			/* Output including mac */
			size = outputlen - iv_len;
			if (size) {
				i = fill_sg_comp_from_iov(scatter_comp, i,
							  params->dst_iov, 0,
							  &size, NULL, 0);

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer space,"
						   " size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	inst->w4.u64 = cpt_inst_w4.u64;

	return 0;
}

static __rte_always_inline int
cpt_zuc_snow3g_dec_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
			struct roc_se_fc_params *params,
			struct cpt_inst_s *inst)
{
	uint32_t size;
	int32_t inputlen = 0, outputlen;
	struct roc_se_ctx *se_ctx;
	uint8_t pdcp_alg_type, iv_len = 16;
	uint32_t encr_offset;
	uint32_t encr_data_len;
	int flags;
	uint64_t *offset_vaddr;
	uint32_t *iv_s, iv[4], j;
	union cpt_inst_w4 cpt_inst_w4;

	/*
	 * Microcode expects offsets in bytes
	 * TODO: Rounding off
	 */
	encr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);

	se_ctx = params->ctx_buf.vaddr;
	flags = se_ctx->zsk_flags;
	pdcp_alg_type = se_ctx->pdcp_alg_type;

	cpt_inst_w4.u64 = 0;
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;

	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */

	cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |
				      (0 << 4) | (0 << 3) | (flags & 0x7));

	/* consider iv len */
	encr_offset += iv_len;

	inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
	outputlen = inputlen;

	/* IV */
	iv_s = params->iv_buf;
	if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {
		/*
		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
		 */

		for (j = 0; j < 4; j++)
			iv[j] = iv_s[3 - j];
	} else {
		/* ZUC doesn't need a swap */
		for (j = 0; j < 4; j++)
			iv[j] = iv_s[j];
	}

	/*
	 * GP op header, lengths are expected in bits.
	 */
	cpt_inst_w4.s.param1 = encr_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
					    ROC_SE_OFF_CTRL_LEN - iv_len);

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			memcpy(iv_d, iv, 16);
		}

		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
	} else {
		void *m_vaddr = params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint32_t *iv_d;

		/* save space for offset and iv... */
		offset_vaddr = m_vaddr;

		m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word */

		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);

		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
				    ROC_SE_OFF_CTRL_LEN);
		memcpy(iv_d, iv, 16);

		/* Add input data */
		size = inputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(gather_comp, i,
						  params->src_iov, 0, &size,
						  NULL, 0);
			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* IV */
		i = fill_sg_comp(scatter_comp, i,
				 (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
				 iv_len);

		/* Add output data */
		size = outputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(scatter_comp, i,
						  params->dst_iov, 0, &size,
						  NULL, 0);

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		return -1;
	}

	inst->w4.u64 = cpt_inst_w4.u64;

	return 0;
}

static __rte_always_inline int
cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		     struct roc_se_fc_params *fc_params,
		     struct cpt_inst_s *inst)
{
	struct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;
	uint8_t fc_type;
	int ret = -1;

	fc_type = ctx->fc_type;

	if (likely(fc_type == ROC_SE_FC_GEN)) {
		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);
	} else if (fc_type == ROC_SE_PDCP) {
		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params,
					      inst);
	}
	return ret;
}

static __rte_always_inline int
cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		     struct roc_se_fc_params *fc_params,
		     struct cpt_inst_s *inst)
{
	struct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;
	uint8_t fc_type;
	int ret = -1;

	fc_type = ctx->fc_type;

	if (likely(fc_type == ROC_SE_FC_GEN)) {
		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, inst);
	} else if (fc_type == ROC_SE_PDCP) {
		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params,
					      inst);
	}

	return ret;
}

static __rte_always_inline int
fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
{
	struct rte_crypto_aead_xform *aead_form;
	roc_se_cipher_type enc_type = 0; /* NULL Cipher type */
	roc_se_auth_type auth_type = 0;	 /* NULL Auth type */
	uint32_t cipher_key_len = 0;
	uint8_t aes_gcm = 0;
	aead_form = &xform->aead;

	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
		sess->cpt_op |= ROC_SE_OP_CIPHER_ENCRYPT;
		sess->cpt_op |= ROC_SE_OP_AUTH_GENERATE;
	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT) {<commit_msg>crypto/cnxk: add KASUMI encryption<commit_after>/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(C) 2021 Marvell.
 */

#ifndef _CNXK_SE_H_
#define _CNXK_SE_H_
#include <stdbool.h>

#include "cnxk_cryptodev.h"
#include "cnxk_cryptodev_ops.h"

#define SRC_IOV_SIZE                                                           \
	(sizeof(struct roc_se_iov_ptr) +                                       \
	 (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))
#define DST_IOV_SIZE                                                           \
	(sizeof(struct roc_se_iov_ptr) +                                       \
	 (sizeof(struct roc_se_buf_ptr) * ROC_SE_MAX_SG_CNT))

struct cnxk_se_sess {
	uint16_t cpt_op : 4;
	uint16_t zsk_flag : 4;
	uint16_t aes_gcm : 1;
	uint16_t aes_ctr : 1;
	uint16_t chacha_poly : 1;
	uint16_t is_null : 1;
	uint16_t is_gmac : 1;
	uint16_t rsvd1 : 3;
	uint16_t aad_length;
	uint8_t mac_len;
	uint8_t iv_length;
	uint8_t auth_iv_length;
	uint16_t iv_offset;
	uint16_t auth_iv_offset;
	uint32_t salt;
	uint64_t cpt_inst_w7;
	struct roc_se_ctx roc_se_ctx;
} __rte_cache_aligned;

static __rte_always_inline int
cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)
{
	uint16_t mac_len = auth->digest_length;
	int ret;

	switch (auth->algo) {
	case RTE_CRYPTO_AUTH_MD5:
	case RTE_CRYPTO_AUTH_MD5_HMAC:
		ret = (mac_len == 16) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA1:
	case RTE_CRYPTO_AUTH_SHA1_HMAC:
		ret = (mac_len == 20) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA224:
	case RTE_CRYPTO_AUTH_SHA224_HMAC:
		ret = (mac_len == 28) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA256:
	case RTE_CRYPTO_AUTH_SHA256_HMAC:
		ret = (mac_len == 32) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA384:
	case RTE_CRYPTO_AUTH_SHA384_HMAC:
		ret = (mac_len == 48) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_SHA512:
	case RTE_CRYPTO_AUTH_SHA512_HMAC:
		ret = (mac_len == 64) ? 0 : -1;
		break;
	case RTE_CRYPTO_AUTH_NULL:
		ret = 0;
		break;
	default:
		ret = -1;
	}

	return ret;
}

static __rte_always_inline void
cpt_fc_salt_update(struct roc_se_ctx *se_ctx, uint8_t *salt)
{
	struct roc_se_context *fctx = &se_ctx->se_ctx.fctx;
	memcpy(fctx->enc.encr_iv, salt, 4);
}

static __rte_always_inline uint32_t
fill_sg_comp(struct roc_se_sglist_comp *list, uint32_t i, phys_addr_t dma_addr,
	     uint32_t size)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];

	to->u.s.len[i % 4] = rte_cpu_to_be_16(size);
	to->ptr[i % 4] = rte_cpu_to_be_64(dma_addr);
	i++;
	return i;
}

static __rte_always_inline uint32_t
fill_sg_comp_from_buf(struct roc_se_sglist_comp *list, uint32_t i,
		      struct roc_se_buf_ptr *from)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];

	to->u.s.len[i % 4] = rte_cpu_to_be_16(from->size);
	to->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);
	i++;
	return i;
}

static __rte_always_inline uint32_t
fill_sg_comp_from_buf_min(struct roc_se_sglist_comp *list, uint32_t i,
			  struct roc_se_buf_ptr *from, uint32_t *psize)
{
	struct roc_se_sglist_comp *to = &list[i >> 2];
	uint32_t size = *psize;
	uint32_t e_len;

	e_len = (size > from->size) ? from->size : size;
	to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
	to->ptr[i % 4] = rte_cpu_to_be_64((uint64_t)from->vaddr);
	*psize -= e_len;
	i++;
	return i;
}

/*
 * This fills the MC expected SGIO list
 * from IOV given by user.
 */
static __rte_always_inline uint32_t
fill_sg_comp_from_iov(struct roc_se_sglist_comp *list, uint32_t i,
		      struct roc_se_iov_ptr *from, uint32_t from_offset,
		      uint32_t *psize, struct roc_se_buf_ptr *extra_buf,
		      uint32_t extra_offset)
{
	int32_t j;
	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
	uint32_t size = *psize;
	struct roc_se_buf_ptr *bufs;

	bufs = from->bufs;
	for (j = 0; (j < from->buf_cnt) && size; j++) {
		uint64_t e_vaddr;
		uint32_t e_len;
		struct roc_se_sglist_comp *to = &list[i >> 2];

		if (unlikely(from_offset)) {
			if (from_offset >= bufs[j].size) {
				from_offset -= bufs[j].size;
				continue;
			}
			e_vaddr = (uint64_t)bufs[j].vaddr + from_offset;
			e_len = (size > (bufs[j].size - from_offset)) ?
					(bufs[j].size - from_offset) :
					size;
			from_offset = 0;
		} else {
			e_vaddr = (uint64_t)bufs[j].vaddr;
			e_len = (size > bufs[j].size) ? bufs[j].size : size;
		}

		to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
		to->ptr[i % 4] = rte_cpu_to_be_64(e_vaddr);

		if (extra_len && (e_len >= extra_offset)) {
			/* Break the data at given offset */
			uint32_t next_len = e_len - extra_offset;
			uint64_t next_vaddr = e_vaddr + extra_offset;

			if (!extra_offset) {
				i--;
			} else {
				e_len = extra_offset;
				size -= e_len;
				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
			}

			extra_len = RTE_MIN(extra_len, size);
			/* Insert extra data ptr */
			if (extra_len) {
				i++;
				to = &list[i >> 2];
				to->u.s.len[i % 4] =
					rte_cpu_to_be_16(extra_len);
				to->ptr[i % 4] = rte_cpu_to_be_64(
					(uint64_t)extra_buf->vaddr);
				size -= extra_len;
			}

			next_len = RTE_MIN(next_len, size);
			/* insert the rest of the data */
			if (next_len) {
				i++;
				to = &list[i >> 2];
				to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
				to->ptr[i % 4] = rte_cpu_to_be_64(next_vaddr);
				size -= next_len;
			}
			extra_len = 0;

		} else {
			size -= e_len;
		}
		if (extra_offset)
			extra_offset -= size;
		i++;
	}

	*psize = size;
	return (uint32_t)i;
}

static __rte_always_inline int
cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		  struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)
{
	uint32_t iv_offset = 0;
	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
	struct roc_se_ctx *se_ctx;
	uint32_t cipher_type, hash_type;
	uint32_t mac_len, size;
	uint8_t iv_len = 16;
	struct roc_se_buf_ptr *aad_buf = NULL;
	uint32_t encr_offset, auth_offset;
	uint32_t encr_data_len, auth_data_len, aad_len = 0;
	uint32_t passthrough_len = 0;
	union cpt_inst_w4 cpt_inst_w4;
	void *offset_vaddr;
	uint8_t op_minor;

	encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
	auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);
	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/* We don't support both AAD and auth data separately */
		auth_data_len = 0;
		auth_offset = 0;
		aad_len = fc_params->aad_buf.size;
		aad_buf = &fc_params->aad_buf;
	}
	se_ctx = fc_params->ctx_buf.vaddr;
	cipher_type = se_ctx->enc_cipher;
	hash_type = se_ctx->hash_type;
	mac_len = se_ctx->mac_len;
	op_minor = se_ctx->template_w4.s.opcode_minor;

	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
		iv_len = 0;
		iv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);
	}

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/*
		 * When AAD is given, data above encr_offset is pass through
		 * Since AAD is given as separate pointer and not as offset,
		 * this is a special case as we need to fragment input data
		 * into passthrough + encr_data and then insert AAD in between.
		 */
		if (hash_type != ROC_SE_GMAC_TYPE) {
			passthrough_len = encr_offset;
			auth_offset = passthrough_len + iv_len;
			encr_offset = passthrough_len + aad_len + iv_len;
			auth_data_len = aad_len + encr_data_len;
		} else {
			passthrough_len = 16 + aad_len;
			auth_offset = passthrough_len + iv_len;
			auth_data_len = aad_len;
		}
	} else {
		encr_offset += iv_len;
		auth_offset += iv_len;
	}

	/* Encryption */
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;
	cpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_ENCRYPT;
	cpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;

	if (hash_type == ROC_SE_GMAC_TYPE) {
		encr_offset = 0;
		encr_data_len = 0;
	}

	auth_dlen = auth_offset + auth_data_len;
	enc_dlen = encr_data_len + encr_offset;
	if (unlikely(encr_data_len & 0xf)) {
		if ((cipher_type == ROC_SE_DES3_CBC) ||
		    (cipher_type == ROC_SE_DES3_ECB))
			enc_dlen =
				RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;
		else if (likely((cipher_type == ROC_SE_AES_CBC) ||
				(cipher_type == ROC_SE_AES_ECB)))
			enc_dlen =
				RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset;
	}

	if (unlikely(auth_dlen > enc_dlen)) {
		inputlen = auth_dlen;
		outputlen = auth_dlen + mac_len;
	} else {
		inputlen = enc_dlen;
		outputlen = enc_dlen + mac_len;
	}

	if (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)
		outputlen = enc_dlen;

	/* GP op header */
	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = fc_params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr =
			(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

	} else {
		void *m_vaddr = fc_params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;

		/* This falls under strict SG mode */
		offset_vaddr = m_vaddr;
		size = ROC_SE_OFF_CTRL_LEN + iv_len;

		m_vaddr = (uint8_t *)m_vaddr + size;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */

		i = 0;

		/* Offset control word that includes iv */
		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* Add input data */
		size = inputlen - iv_len;
		if (likely(size)) {
			uint32_t aad_offset = aad_len ? passthrough_len : 0;

			if (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {
				i = fill_sg_comp_from_buf_min(
					gather_comp, i, fc_params->bufs, &size);
			} else {
				i = fill_sg_comp_from_iov(
					gather_comp, i, fc_params->src_iov, 0,
					&size, aad_buf, aad_offset);
			}

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter list
		 */
		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* Add IV */
		if (likely(iv_len)) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* output data or output data + digest*/
		if (unlikely(flags & ROC_SE_VALID_MAC_BUF)) {
			size = outputlen - iv_len - mac_len;
			if (size) {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						scatter_comp, i,
						fc_params->bufs, &size);
				} else {
					i = fill_sg_comp_from_iov(
						scatter_comp, i,
						fc_params->dst_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
			/* mac_data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(scatter_comp, i,
							  &fc_params->mac_buf);
			}
		} else {
			/* Output including mac */
			size = outputlen - iv_len;
			if (likely(size)) {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						scatter_comp, i,
						fc_params->bufs, &size);
				} else {
					i = fill_sg_comp_from_iov(
						scatter_comp, i,
						fc_params->dst_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||
		     (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("iv_offset : %d", iv_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(
		((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |
		((uint64_t)auth_offset));

	inst->w4.u64 = cpt_inst_w4.u64;
	return 0;
}

static __rte_always_inline int
cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		  struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst)
{
	uint32_t iv_offset = 0, size;
	int32_t inputlen, outputlen, enc_dlen, auth_dlen;
	struct roc_se_ctx *se_ctx;
	int32_t hash_type, mac_len;
	uint8_t iv_len = 16;
	struct roc_se_buf_ptr *aad_buf = NULL;
	uint32_t encr_offset, auth_offset;
	uint32_t encr_data_len, auth_data_len, aad_len = 0;
	uint32_t passthrough_len = 0;
	union cpt_inst_w4 cpt_inst_w4;
	void *offset_vaddr;
	uint8_t op_minor;

	encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
	auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/* We don't support both AAD and auth data separately */
		auth_data_len = 0;
		auth_offset = 0;
		aad_len = fc_params->aad_buf.size;
		aad_buf = &fc_params->aad_buf;
	}

	se_ctx = fc_params->ctx_buf.vaddr;
	hash_type = se_ctx->hash_type;
	mac_len = se_ctx->mac_len;
	op_minor = se_ctx->template_w4.s.opcode_minor;

	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
		iv_len = 0;
		iv_offset = ROC_SE_ENCR_IV_OFFSET(d_offs);
	}

	if (unlikely(flags & ROC_SE_VALID_AAD_BUF)) {
		/*
		 * When AAD is given, data above encr_offset is pass through
		 * Since AAD is given as separate pointer and not as offset,
		 * this is a special case as we need to fragment input data
		 * into passthrough + encr_data and then insert AAD in between.
		 */
		if (hash_type != ROC_SE_GMAC_TYPE) {
			passthrough_len = encr_offset;
			auth_offset = passthrough_len + iv_len;
			encr_offset = passthrough_len + aad_len + iv_len;
			auth_data_len = aad_len + encr_data_len;
		} else {
			passthrough_len = 16 + aad_len;
			auth_offset = passthrough_len + iv_len;
			auth_data_len = aad_len;
		}
	} else {
		encr_offset += iv_len;
		auth_offset += iv_len;
	}

	/* Decryption */
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;
	cpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_DECRYPT;
	cpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;

	if (hash_type == ROC_SE_GMAC_TYPE) {
		encr_offset = 0;
		encr_data_len = 0;
	}

	enc_dlen = encr_offset + encr_data_len;
	auth_dlen = auth_offset + auth_data_len;

	if (auth_dlen > enc_dlen) {
		inputlen = auth_dlen + mac_len;
		outputlen = auth_dlen;
	} else {
		inputlen = enc_dlen + mac_len;
		outputlen = enc_dlen;
	}

	if (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)
		outputlen = inputlen = enc_dlen;

	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = fc_params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr =
			(uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN - iv_len;
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

	} else {
		void *m_vaddr = fc_params->meta_buf.vaddr;
		uint32_t g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint8_t i = 0;

		/* This falls under strict SG mode */
		offset_vaddr = m_vaddr;
		size = ROC_SE_OFF_CTRL_LEN + iv_len;

		m_vaddr = (uint8_t *)m_vaddr + size;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		if (likely(iv_len)) {
			uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			uint64_t *src = fc_params->iv_buf;
			dest[0] = src[0];
			dest[1] = src[1];
		}

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word that includes iv */
		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* Add input data */
		if (flags & ROC_SE_VALID_MAC_BUF) {
			size = inputlen - iv_len - mac_len;
			if (size) {
				/* input data only */
				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						gather_comp, i, fc_params->bufs,
						&size);
				} else {
					uint32_t aad_offset =
						aad_len ? passthrough_len : 0;

					i = fill_sg_comp_from_iov(
						gather_comp, i,
						fc_params->src_iov, 0, &size,
						aad_buf, aad_offset);
				}
				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}

			/* mac data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(gather_comp, i,
							  &fc_params->mac_buf);
			}
		} else {
			/* input data + mac */
			size = inputlen - iv_len;
			if (size) {
				if (unlikely(flags &
					     ROC_SE_SINGLE_BUF_INPLACE)) {
					i = fill_sg_comp_from_buf_min(
						gather_comp, i, fc_params->bufs,
						&size);
				} else {
					uint32_t aad_offset =
						aad_len ? passthrough_len : 0;

					if (unlikely(!fc_params->src_iov)) {
						plt_dp_err("Bad input args");
						return -1;
					}

					i = fill_sg_comp_from_iov(
						gather_comp, i,
						fc_params->src_iov, 0, &size,
						aad_buf, aad_offset);
				}

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer"
						   " space, size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* Add iv */
		if (iv_len) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* Add output data */
		size = outputlen - iv_len;
		if (size) {
			if (unlikely(flags & ROC_SE_SINGLE_BUF_INPLACE)) {
				/* handle single buffer here */
				i = fill_sg_comp_from_buf_min(scatter_comp, i,
							      fc_params->bufs,
							      &size);
			} else {
				uint32_t aad_offset =
					aad_len ? passthrough_len : 0;

				if (unlikely(!fc_params->dst_iov)) {
					plt_dp_err("Bad input args");
					return -1;
				}

				i = fill_sg_comp_from_iov(
					scatter_comp, i, fc_params->dst_iov, 0,
					&size, aad_buf, aad_offset);
			}

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}

		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16) || (iv_offset >> 8) ||
		     (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("iv_offset : %d", iv_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(
		((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) |
		((uint64_t)auth_offset));

	inst->w4.u64 = cpt_inst_w4.u64;
	return 0;
}

static __rte_always_inline int
cpt_zuc_snow3g_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
			struct roc_se_fc_params *params,
			struct cpt_inst_s *inst)
{
	uint32_t size;
	int32_t inputlen, outputlen;
	struct roc_se_ctx *se_ctx;
	uint32_t mac_len = 0;
	uint8_t pdcp_alg_type, j;
	uint32_t encr_offset = 0, auth_offset = 0;
	uint32_t encr_data_len = 0, auth_data_len = 0;
	int flags, iv_len = 16;
	uint64_t offset_ctrl;
	uint64_t *offset_vaddr;
	uint32_t *iv_s, iv[4];
	union cpt_inst_w4 cpt_inst_w4;

	se_ctx = params->ctx_buf.vaddr;
	flags = se_ctx->zsk_flags;
	mac_len = se_ctx->mac_len;
	pdcp_alg_type = se_ctx->pdcp_alg_type;

	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;

	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */

	cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |
				      (0 << 4) | (0 << 3) | (flags & 0x7));

	if (flags == 0x1) {
		/*
		 * Microcode expects offsets in bytes
		 * TODO: Rounding off
		 */
		auth_data_len = ROC_SE_AUTH_DLEN(d_lens);

		/* EIA3 or UIA2 */
		auth_offset = ROC_SE_AUTH_OFFSET(d_offs);
		auth_offset = auth_offset / 8;

		/* consider iv len */
		auth_offset += iv_len;

		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
		outputlen = mac_len;

		offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);

	} else {
		/* EEA3 or UEA2 */
		/*
		 * Microcode expects offsets in bytes
		 * TODO: Rounding off
		 */
		encr_data_len = ROC_SE_ENCR_DLEN(d_lens);

		encr_offset = ROC_SE_ENCR_OFFSET(d_offs);
		encr_offset = encr_offset / 8;
		/* consider iv len */
		encr_offset += iv_len;

		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
		outputlen = inputlen;

		/* iv offset is 0 */
		offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
	}

	if (unlikely((encr_offset >> 16) || (auth_offset >> 8))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		plt_dp_err("auth_offset: %d", auth_offset);
		return -1;
	}

	/* IV */
	iv_s = (flags == 0x1) ? params->auth_iv_buf : params->iv_buf;

	if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {
		/*
		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
		 */

		for (j = 0; j < 4; j++)
			iv[j] = iv_s[3 - j];
	} else {
		/* ZUC doesn't need a swap */
		for (j = 0; j < 4; j++)
			iv[j] = iv_s[j];
	}

	/*
	 * GP op header, lengths are expected in bits.
	 */
	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
					    ROC_SE_OFF_CTRL_LEN - iv_len);

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;
		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			memcpy(iv_d, iv, 16);
		}

		*offset_vaddr = offset_ctrl;
	} else {
		void *m_vaddr = params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint32_t *iv_d;

		/* save space for iv */
		offset_vaddr = m_vaddr;

		m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word followed by iv */

		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		/* iv offset is 0 */
		*offset_vaddr = offset_ctrl;

		iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
				    ROC_SE_OFF_CTRL_LEN);
		memcpy(iv_d, iv, 16);

		/* input data */
		size = inputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(gather_comp, i,
						  params->src_iov, 0, &size,
						  NULL, 0);
			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		if (flags == 0x1) {
			/* IV in SLIST only for EEA3 & UEA2 */
			iv_len = 0;
		}

		if (iv_len) {
			i = fill_sg_comp(scatter_comp, i,
					 (uint64_t)offset_vaddr +
						 ROC_SE_OFF_CTRL_LEN,
					 iv_len);
		}

		/* Add output data */
		if (req_flags & ROC_SE_VALID_MAC_BUF) {
			size = outputlen - iv_len - mac_len;
			if (size) {
				i = fill_sg_comp_from_iov(scatter_comp, i,
							  params->dst_iov, 0,
							  &size, NULL, 0);

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer space,"
						   " size %d needed",
						   size);
					return -1;
				}
			}

			/* mac data */
			if (mac_len) {
				i = fill_sg_comp_from_buf(scatter_comp, i,
							  &params->mac_buf);
			}
		} else {
			/* Output including mac */
			size = outputlen - iv_len;
			if (size) {
				i = fill_sg_comp_from_iov(scatter_comp, i,
							  params->dst_iov, 0,
							  &size, NULL, 0);

				if (unlikely(size)) {
					plt_dp_err("Insufficient buffer space,"
						   " size %d needed",
						   size);
					return -1;
				}
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	inst->w4.u64 = cpt_inst_w4.u64;

	return 0;
}

static __rte_always_inline int
cpt_zuc_snow3g_dec_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
			struct roc_se_fc_params *params,
			struct cpt_inst_s *inst)
{
	uint32_t size;
	int32_t inputlen = 0, outputlen;
	struct roc_se_ctx *se_ctx;
	uint8_t pdcp_alg_type, iv_len = 16;
	uint32_t encr_offset;
	uint32_t encr_data_len;
	int flags;
	uint64_t *offset_vaddr;
	uint32_t *iv_s, iv[4], j;
	union cpt_inst_w4 cpt_inst_w4;

	/*
	 * Microcode expects offsets in bytes
	 * TODO: Rounding off
	 */
	encr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);

	se_ctx = params->ctx_buf.vaddr;
	flags = se_ctx->zsk_flags;
	pdcp_alg_type = se_ctx->pdcp_alg_type;

	cpt_inst_w4.u64 = 0;
	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;

	/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */

	cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |
				      (0 << 4) | (0 << 3) | (flags & 0x7));

	/* consider iv len */
	encr_offset += iv_len;

	inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
	outputlen = inputlen;

	/* IV */
	iv_s = params->iv_buf;
	if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {
		/*
		 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
		 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
		 */

		for (j = 0; j < 4; j++)
			iv[j] = iv_s[3 - j];
	} else {
		/* ZUC doesn't need a swap */
		for (j = 0; j < 4; j++)
			iv[j] = iv_s[j];
	}

	/*
	 * GP op header, lengths are expected in bits.
	 */
	cpt_inst_w4.s.param1 = encr_data_len;

	/*
	 * In cn9k, cn10k since we have a limitation of
	 * IV & Offset control word not part of instruction
	 * and need to be part of Data Buffer, we check if
	 * head room is there and then only do the Direct mode processing
	 */
	if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&
		   (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
		void *dm_vaddr = params->bufs[0].vaddr;

		/* Use Direct mode */

		offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
					    ROC_SE_OFF_CTRL_LEN - iv_len);

		/* DPTR */
		inst->dptr = (uint64_t)offset_vaddr;

		/* RPTR should just exclude offset control word */
		inst->rptr = (uint64_t)dm_vaddr - iv_len;

		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;

		if (likely(iv_len)) {
			uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
						      ROC_SE_OFF_CTRL_LEN);
			memcpy(iv_d, iv, 16);
		}

		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
	} else {
		void *m_vaddr = params->meta_buf.vaddr;
		uint32_t i, g_size_bytes, s_size_bytes;
		struct roc_se_sglist_comp *gather_comp;
		struct roc_se_sglist_comp *scatter_comp;
		uint8_t *in_buffer;
		uint32_t *iv_d;

		/* save space for offset and iv... */
		offset_vaddr = m_vaddr;

		m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;

		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;

		/* DPTR has SG list */
		in_buffer = m_vaddr;

		((uint16_t *)in_buffer)[0] = 0;
		((uint16_t *)in_buffer)[1] = 0;

		/* TODO Add error check if space will be sufficient */
		gather_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

		/*
		 * Input Gather List
		 */
		i = 0;

		/* Offset control word */

		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);

		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
				 ROC_SE_OFF_CTRL_LEN + iv_len);

		iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
				    ROC_SE_OFF_CTRL_LEN);
		memcpy(iv_d, iv, 16);

		/* Add input data */
		size = inputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(gather_comp, i,
						  params->src_iov, 0, &size,
						  NULL, 0);
			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
		g_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		/*
		 * Output Scatter List
		 */

		i = 0;
		scatter_comp =
			(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						      g_size_bytes);

		/* IV */
		i = fill_sg_comp(scatter_comp, i,
				 (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
				 iv_len);

		/* Add output data */
		size = outputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(scatter_comp, i,
						  params->dst_iov, 0, &size,
						  NULL, 0);

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
		s_size_bytes =
			((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

		size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

		/* This is DPTR len in case of SG mode */
		cpt_inst_w4.s.dlen = size;

		inst->dptr = (uint64_t)in_buffer;
	}

	if (unlikely((encr_offset >> 16))) {
		plt_dp_err("Offset not supported");
		plt_dp_err("enc_offset: %d", encr_offset);
		return -1;
	}

	inst->w4.u64 = cpt_inst_w4.u64;

	return 0;
}

static __rte_always_inline int
cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
		    struct roc_se_fc_params *params, struct cpt_inst_s *inst)
{
	void *m_vaddr = params->meta_buf.vaddr;
	uint32_t size;
	int32_t inputlen = 0, outputlen = 0;
	struct roc_se_ctx *se_ctx;
	uint32_t mac_len = 0;
	uint8_t i = 0;
	uint32_t encr_offset, auth_offset;
	uint32_t encr_data_len, auth_data_len;
	int flags;
	uint8_t *iv_s, *iv_d, iv_len = 8;
	uint8_t dir = 0;
	uint64_t *offset_vaddr;
	union cpt_inst_w4 cpt_inst_w4;
	uint8_t *in_buffer;
	uint32_t g_size_bytes, s_size_bytes;
	struct roc_se_sglist_comp *gather_comp;
	struct roc_se_sglist_comp *scatter_comp;

	encr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;
	auth_offset = ROC_SE_AUTH_OFFSET(d_offs) / 8;
	encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
	auth_data_len = ROC_SE_AUTH_DLEN(d_lens);

	se_ctx = params->ctx_buf.vaddr;
	flags = se_ctx->zsk_flags;
	mac_len = se_ctx->mac_len;

	if (flags == 0x0)
		iv_s = params->iv_buf;
	else
		iv_s = params->auth_iv_buf;

	dir = iv_s[8] & 0x1;

	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_SE_DMA_MODE;

	/* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
	cpt_inst_w4.s.opcode_minor = ((1 << 6) | (se_ctx->k_ecb << 5) |
				      (dir << 4) | (0 << 3) | (flags & 0x7));

	/*
	 * GP op header, lengths are expected in bits.
	 */
	cpt_inst_w4.s.param1 = encr_data_len;
	cpt_inst_w4.s.param2 = auth_data_len;

	/* consider iv len */
	if (flags == 0x0) {
		encr_offset += iv_len;
		auth_offset += iv_len;
	}

	/* save space for offset ctrl and iv */
	offset_vaddr = m_vaddr;

	m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;

	/* DPTR has SG list */
	in_buffer = m_vaddr;

	((uint16_t *)in_buffer)[0] = 0;
	((uint16_t *)in_buffer)[1] = 0;

	/* TODO Add error check if space will be sufficient */
	gather_comp = (struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);

	/*
	 * Input Gather List
	 */
	i = 0;

	/* Offset control word followed by iv */

	if (flags == 0x0) {
		inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
		outputlen = inputlen;
		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
		if (unlikely((encr_offset >> 16))) {
			plt_dp_err("Offset not supported");
			plt_dp_err("enc_offset: %d", encr_offset);
			return -1;
		}
	} else {
		inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
		outputlen = mac_len;
		/* iv offset is 0 */
		*offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
		if (unlikely((auth_offset >> 8))) {
			plt_dp_err("Offset not supported");
			plt_dp_err("auth_offset: %d", auth_offset);
			return -1;
		}
	}

	i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
			 ROC_SE_OFF_CTRL_LEN + iv_len);

	/* IV */
	iv_d = (uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN;
	memcpy(iv_d, iv_s, iv_len);

	/* input data */
	size = inputlen - iv_len;
	if (size) {
		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0,
					  &size, NULL, 0);

		if (unlikely(size)) {
			plt_dp_err("Insufficient buffer space,"
				   " size %d needed",
				   size);
			return -1;
		}
	}
	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
	g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

	/*
	 * Output Scatter List
	 */

	i = 0;
	scatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
						     g_size_bytes);

	if (flags == 0x1) {
		/* IV in SLIST only for F8 */
		iv_len = 0;
	}

	/* IV */
	if (iv_len) {
		i = fill_sg_comp(scatter_comp, i,
				 (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
				 iv_len);
	}

	/* Add output data */
	if (req_flags & ROC_SE_VALID_MAC_BUF) {
		size = outputlen - iv_len - mac_len;
		if (size) {
			i = fill_sg_comp_from_iov(scatter_comp, i,
						  params->dst_iov, 0, &size,
						  NULL, 0);

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}

		/* mac data */
		if (mac_len) {
			i = fill_sg_comp_from_buf(scatter_comp, i,
						  &params->mac_buf);
		}
	} else {
		/* Output including mac */
		size = outputlen - iv_len;
		if (size) {
			i = fill_sg_comp_from_iov(scatter_comp, i,
						  params->dst_iov, 0, &size,
						  NULL, 0);

			if (unlikely(size)) {
				plt_dp_err("Insufficient buffer space,"
					   " size %d needed",
					   size);
				return -1;
			}
		}
	}
	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
	s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);

	size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;

	/* This is DPTR len in case of SG mode */
	cpt_inst_w4.s.dlen = size;

	inst->dptr = (uint64_t)in_buffer;
	inst->w4.u64 = cpt_inst_w4.u64;

	return 0;
}

static __rte_always_inline int
cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		     struct roc_se_fc_params *fc_params,
		     struct cpt_inst_s *inst)
{
	struct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;
	uint8_t fc_type;
	int ret = -1;

	fc_type = ctx->fc_type;

	if (likely(fc_type == ROC_SE_FC_GEN)) {
		ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);
	} else if (fc_type == ROC_SE_PDCP) {
		ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params,
					      inst);
	}
	return ret;
}

static __rte_always_inline int
cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
		     struct roc_se_fc_params *fc_params,
		     struct cpt_inst_s *inst)
{
	struct roc_se_ctx *ctx = fc_params->ctx_buf.vaddr;
	uint8_t fc_type;
	int ret = -1;

	fc_type = ctx->fc_type;

	if (likely(fc_type == ROC_SE_FC_GEN)) {
		ret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, inst);
	} else if (fc_type == ROC_SE_PDCP) {
		ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params,
					      inst);
	} else if (fc_type == ROC_SE_KASUMI) {
		ret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params,
					  inst);
	}

	return ret;
}

static __rte_always_inline int
fill_sess_aead(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
{
	struct rte_crypto_aead_xform *aead_form;
	roc_se_cipher_type enc_type = 0; /* NULL Cipher type */
	roc_se_auth_type auth_type = 0;	 /* NULL Auth type */
	uint32_t cipher_key_len = 0;
	uint8_t aes_gcm = 0;
	aead_form = &xform->aead;

	if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
		sess->cpt_op |= ROC_SE_OP_CIPHER_ENCRYPT;
		sess->cpt_op |= ROC_SE_OP_AUTH_GENERATE;
	} else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT) {
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{'dir': 'git-commits-cleaned', 'id': '2463033', 'n_tokens_mistral': 36617, 'n_tokens_neox': 31570, 'n_words': 6289}