<commit_before>/*
 * Intel 5100 Memory Controllers kernel module
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * This module is based on the following document:
 *
 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
 *      http://download.intel.com/design/chipsets/datashts/318378.pdf
 *
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/delay.h>
#include <linux/mmzone.h>

#include "edac_core.h"

/* register addresses and bit field accessors... */

/* device 16, func 1 */
#define I5100_MS		0x44	/* Memory Status Register */
#define I5100_SPDDATA		0x48	/* Serial Presence Detect Status Reg */
#define		I5100_SPDDATA_RDO(a)	((a) >> 15 & 1)
#define		I5100_SPDDATA_SBE(a)	((a) >> 13 & 1)
#define		I5100_SPDDATA_BUSY(a)	((a) >> 12 & 1)
#define		I5100_SPDDATA_DATA(a)	((a)       & ((1 << 8) - 1))
#define I5100_SPDCMD		0x4c	/* Serial Presence Detect Command Reg */
#define		I5100_SPDCMD_DTI(a)	(((a) & ((1 << 4) - 1)) << 28)
#define		I5100_SPDCMD_CKOVRD(a)	(((a) & 1)              << 27)
#define		I5100_SPDCMD_SA(a)	(((a) & ((1 << 3) - 1)) << 24)
#define		I5100_SPDCMD_BA(a)	(((a) & ((1 << 8) - 1)) << 16)
#define		I5100_SPDCMD_DATA(a)	(((a) & ((1 << 8) - 1)) <<  8)
#define		I5100_SPDCMD_CMD(a)	((a) & 1)
#define I5100_TOLM		0x6c	/* Top of Low Memory */
#define		I5100_TOLM_TOLM(a)	((a) >> 12 & ((1 << 4) - 1))
#define I5100_MIR0		0x80	/* Memory Interleave Range 0 */
#define I5100_MIR1		0x84	/* Memory Interleave Range 1 */
#define I5100_AMIR_0		0x8c	/* Adjusted Memory Interleave Range 0 */
#define I5100_AMIR_1		0x90	/* Adjusted Memory Interleave Range 1 */
#define		I5100_MIR_LIMIT(a)	((a) >> 4 & ((1 << 12) - 1))
#define		I5100_MIR_WAY1(a)	((a) >> 1 & 1)
#define		I5100_MIR_WAY0(a)	((a)      & 1)
#define I5100_FERR_NF_MEM	0xa0	/* MC First Non Fatal Errors */
#define		I5100_FERR_NF_MEM_CHAN_INDX(a)	((a) >> 28 & 1)
#define		I5100_FERR_NF_MEM_SPD_MASK	(1 << 18)
#define		I5100_FERR_NF_MEM_M16ERR_MASK	(1 << 16)
#define		I5100_FERR_NF_MEM_M15ERR_MASK	(1 << 15)
#define		I5100_FERR_NF_MEM_M14ERR_MASK	(1 << 14)
#define		I5100_FERR_NF_MEM_
#define		I5100_FERR_NF_MEM_
#define		I5100_FERR_NF_MEM_ANY_MASK	\
			(I5100_FERR_NF_MEM_M16ERR_MASK | \
			I5100_FERR_NF_MEM_M15ERR_MASK | \
			I5100_FERR_NF_MEM_M14ERR_MASK)
#define		I5100_FERR_NF_MEM_ANY(a)  ((a) & I5100_FERR_NF_MEM_ANY_MASK)
#define	I5100_NERR_NF_MEM	0xa4	/* MC Next Non-Fatal Errors */
#define		I5100_NERR_NF_MEM_ANY(a)  I5100_FERR_NF_MEM_ANY(a)

/* device 21 and 22, func 0 */
#define I5100_MTR_0	0x154	/* Memory Technology Registers 0-3 */
#define I5100_DMIR	0x15c	/* DIMM Interleave Range */
#define		I5100_DMIR_LIMIT(a)	((a) >> 16 & ((1 << 11) - 1))
#define		I5100_DMIR_RANK(a, i)	((a) >> (4 * i) & ((1 <<  2) - 1))
#define I5100_MTR_4	0x1b0	/* Memory Technology Registers 4,5 */
#define		I5100_MTR_PRESENT(a)	((a) >> 10 & 1)
#define		I5100_MTR_ETHROTTLE(a)	((a) >>  9 & 1)
#define		I5100_MTR_WIDTH(a)	((a) >>  8 & 1)
#define		I5100_MTR_NUMBANK(a)	((a) >>  6 & 1)
#define		I5100_MTR_NUMROW(a)	((a) >>  2 & ((1 << 2) - 1))
#define		I5100_MTR_NUMCOL(a)	((a)       & ((1 << 2) - 1))
#define	I5100_VALIDLOG	0x18c	/* Valid Log Markers */
#define		I5100_VALIDLOG_REDMEMVALID(a)	((a) >> 2 & 1)
#define		I5100_VALIDLOG_RECMEMVALID(a)	((a) >> 1 & 1)
#define		I5100_VALIDLOG_NRECMEMVALID(a)	((a)      & 1)
#define	I5100_NRECMEMA	0x190	/* Non-Recoverable Memory Error Log Reg A */
#define		I5100_NRECMEMA_MERR(a)		((a) >> 15 & ((1 << 5) - 1))
#define		I5100_NRECMEMA_BANK(a)		((a) >> 12 & ((1 << 3) - 1))
#define		I5100_NRECMEMA_RANK(a)		((a) >>  8 & ((1 << 3) - 1))
#define		I5100_NRECMEMA_DM_BUF_ID(a)	((a)       & ((1 << 8) - 1))
#define	I5100_NRECMEMB	0x194	/* Non-Recoverable Memory Error Log Reg B */
#define		I5100_NRECMEMB_CAS(a)		((a) >> 16 & ((1 << 13) - 1))
#define		I5100_NRECMEMB_RAS(a)		((a)       & ((1 << 16) - 1))
#define	I5100_REDMEMA	0x198	/* Recoverable Memory Data Error Log Reg A */<commit_msg>edac: i5100 fix missing bits<commit_after>/*
 * Intel 5100 Memory Controllers kernel module
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * This module is based on the following document:
 *
 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
 *      http://download.intel.com/design/chipsets/datashts/318378.pdf
 *
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/delay.h>
#include <linux/mmzone.h>

#include "edac_core.h"

/* register addresses and bit field accessors... */

/* device 16, func 1 */
#define I5100_MS		0x44	/* Memory Status Register */
#define I5100_SPDDATA		0x48	/* Serial Presence Detect Status Reg */
#define		I5100_SPDDATA_RDO(a)	((a) >> 15 & 1)
#define		I5100_SPDDATA_SBE(a)	((a) >> 13 & 1)
#define		I5100_SPDDATA_BUSY(a)	((a) >> 12 & 1)
#define		I5100_SPDDATA_DATA(a)	((a)       & ((1 << 8) - 1))
#define I5100_SPDCMD		0x4c	/* Serial Presence Detect Command Reg */
#define		I5100_SPDCMD_DTI(a)	(((a) & ((1 << 4) - 1)) << 28)
#define		I5100_SPDCMD_CKOVRD(a)	(((a) & 1)              << 27)
#define		I5100_SPDCMD_SA(a)	(((a) & ((1 << 3) - 1)) << 24)
#define		I5100_SPDCMD_BA(a)	(((a) & ((1 << 8) - 1)) << 16)
#define		I5100_SPDCMD_DATA(a)	(((a) & ((1 << 8) - 1)) <<  8)
#define		I5100_SPDCMD_CMD(a)	((a) & 1)
#define I5100_TOLM		0x6c	/* Top of Low Memory */
#define		I5100_TOLM_TOLM(a)	((a) >> 12 & ((1 << 4) - 1))
#define I5100_MIR0		0x80	/* Memory Interleave Range 0 */
#define I5100_MIR1		0x84	/* Memory Interleave Range 1 */
#define I5100_AMIR_0		0x8c	/* Adjusted Memory Interleave Range 0 */
#define I5100_AMIR_1		0x90	/* Adjusted Memory Interleave Range 1 */
#define		I5100_MIR_LIMIT(a)	((a) >> 4 & ((1 << 12) - 1))
#define		I5100_MIR_WAY1(a)	((a) >> 1 & 1)
#define		I5100_MIR_WAY0(a)	((a)      & 1)
#define I5100_FERR_NF_MEM	0xa0	/* MC First Non Fatal Errors */
#define		I5100_FERR_NF_MEM_CHAN_INDX(a)	((a) >> 28 & 1)
#define		I5100_FERR_NF_MEM_SPD_MASK	(1 << 18)
#define		I5100_FERR_NF_MEM_M16ERR_MASK	(1 << 16)
#define		I5100_FERR_NF_MEM_M15ERR_MASK	(1 << 15)
#define		I5100_FERR_NF_MEM_M14ERR_MASK	(1 << 14)
#define		I5100_FERR_NF_MEM_M12ERR_MASK	(1 << 12)
#define		I5100_FERR_NF_MEM_M11ERR_MASK	(1 << 11)
#define		I5100_FERR_NF_MEM_M10ERR_MASK	(1 << 10)
#define		I5100_FERR_NF_MEM_M6ERR_MASK	(1 << 6)
#define		I5100_FERR_NF_MEM_M5ERR_MASK	(1 << 5)
#define		I5100_FERR_NF_MEM_M4ERR_MASK	(1 << 4)
#define		I5100_FERR_NF_MEM_M1ERR_MASK	1
#define		I5100_FERR_NF_MEM_ANY_MASK	\
			(I5100_FERR_NF_MEM_M16ERR_MASK | \
			I5100_FERR_NF_MEM_M15ERR_MASK | \
			I5100_FERR_NF_MEM_M14ERR_MASK | \
			I5100_FERR_NF_MEM_M12ERR_MASK | \
			I5100_FERR_NF_MEM_M11ERR_MASK | \
			I5100_FERR_NF_MEM_M10ERR_MASK | \
			I5100_FERR_NF_MEM_M6ERR_MASK | \
			I5100_FERR_NF_MEM_M5ERR_MASK | \
			I5100_FERR_NF_MEM_M4ERR_MASK | \
			I5100_FERR_NF_MEM_M1ERR_MASK)
#define		I5100_FERR_NF_MEM_ANY(a)  ((a) & I5100_FERR_NF_MEM_ANY_MASK)
#define	I5100_NERR_NF_MEM	0xa4	/* MC Next Non-Fatal Errors */
#define		I5100_NERR_NF_MEM_ANY(a)  I5100_FERR_NF_MEM_ANY(a)

/* device 21 and 22, func 0 */
#define I5100_MTR_0	0x154	/* Memory Technology Registers 0-3 */
#define I5100_DMIR	0x15c	/* DIMM Interleave Range */
#define		I5100_DMIR_LIMIT(a)	((a) >> 16 & ((1 << 11) - 1))
#define		I5100_DMIR_RANK(a, i)	((a) >> (4 * i) & ((1 <<  2) - 1))
#define I5100_MTR_4	0x1b0	/* Memory Technology Registers 4,5 */
#define		I5100_MTR_PRESENT(a)	((a) >> 10 & 1)
#define		I5100_MTR_ETHROTTLE(a)	((a) >>  9 & 1)
#define		I5100_MTR_WIDTH(a)	((a) >>  8 & 1)
#define		I5100_MTR_NUMBANK(a)	((a) >>  6 & 1)
#define		I5100_MTR_NUMROW(a)	((a) >>  2 & ((1 << 2) - 1))
#define		I5100_MTR_NUMCOL(a)	((a)       & ((1 << 2) - 1))
#define	I5100_VALIDLOG	0x18c	/* Valid Log Markers */
#define		I5100_VALIDLOG_REDMEMVALID(a)	((a) >> 2 & 1)
#define		I5100_VALIDLOG_RECMEMVALID(a)	((a) >> 1 & 1)
#define		I5100_VALIDLOG_NRECMEMVALID(a)	((a)      & 1)
#define	I5100_NRECMEMA	0x190	/* Non-Recoverable Memory Error Log Reg A */
#define		I5100_NRECMEMA_MERR(a)		((a) >> 15 & ((1 << 5) - 1))
#define		I5100_NRECMEMA_BANK(a)		((a) >> 12 & ((1 << 3) - 1))
#define		I5100_NRECMEMA_RANK(a)		((a) >>  8 & ((1 << 3) - 1))
#define		I5100_NRECMEMA_DM_BUF_ID(a)	((a)       & ((1 << 8) - 1))
#define	I5100_NRECMEMB	0x194	/* Non-Recoverable Memory Error Log Reg B */
#define		I5100_NRECMEMB_CAS(a)		((a) >> 16 & ((1 << 13) - 1))
#define		I5100_NRECMEMB_RAS(a)		((a)       & ((1 << 16) - 1))
#define	I5100_REDMEMA	0x198	/* Recoverable Memory Data Error Log Reg A */
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