<commit_before>/*
 * core.sv
 */

import riscv::*;

/**
 * Module: core
 *
 */
module core (
    input  logic  clk,
    input  logic  reset,
    output logic [3:0] led
);
    wire resetn = ~reset;

    // Control signals<commit_msg>core: use active low reset again<commit_after>/*
 * core.sv
 */

import riscv::*;

/**
 * Module: core
 *
 */
module core (
    input  logic  clk,
    input  logic  resetn,
    output logic [3:0] led
);
    // Control signals
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