<commit_before>package hevs.especial.dsl.components.core.logic

import hevs.especial.dsl.components._

case class And2() extends AbstractLogic(2, "&") with In2 with Out1 with HwImplemented {
  override val description = s"And2 gate"

  val in1 = in(1)

  val in2 = in(2)
}

case class And3() extends AbstractLogic(3, "&") with In3 with Out1 with HwImplemented {
  override val description = s"And3 gate"

  val in1 = in(1)

  val in2 = in(2)

  val in3 = in(3)
}

case class And4() extends AbstractLogic(4, "&") with In4 with Out1 with HwImplemented {
  override val description = s"And4 gate"

  val in1 = in(1)

  val in2 = in(2)

  val in3 = in(3)

  val in4 = in(4)
}

case class Or2() extends AbstractLogic(2, "|") with In2 with Out1 with HwImplemented {
  override val description = s"Or2 gate"

  val in1 = in(1)

  val in2 = in(2)
}<commit_msg>Return type is neede here. See SI-5091. https://issues.scala-lang.org/browse/SI-5091<commit_after>package hevs.especial.dsl.components.core.logic

import hevs.especial.dsl.components._

case class And2() extends AbstractLogic(2, "&") with In2 with Out1 {
  override val description = s"And2 gate"

  override val in1 = in(0)
  override val in2 = in(1)

  override val out: OutputPort[bool] = out(0)
}

case class And3() extends AbstractLogic(3, "&") with In3 with Out1 {
  override val description = s"And3 gate"

  override val in1 = in(0)
  override val in2 = in(1)
  override val in3 = in(2)

  override val out: OutputPort[bool] = out(0)
}

case class And4() extends AbstractLogic(4, "&") with In4 with Out1 {
  override val description = s"And4 gate"

  override val in1 = in(0)
  override val in2 = in(1)
  override val in3 = in(2)
  override val in4 = in(3)

  override val out: OutputPort[bool] = out(0)
}



case class Or2() extends AbstractLogic(2, "|") with In2 with Out1 {
  override val description = s"Or2 gate"

  override val in1 = in(0)
  override val in2 = in(1)

  override val out: OutputPort[bool] = out(0)
}

case class Or3() extends AbstractLogic(3, "|") with In3 with Out1 {
  override val description = s"Or3 gate"

  override val in1 = in(0)
  override val in2 = in(1)
  override val in3 = in(2)

  override val out: OutputPort[bool] = out(0)
}

case class Or4() extends AbstractLogic(4, "|") with In4 with Out1 {
  override val description = s"Or4 gate"

  override val in1 = in(0)
  override val in2 = in(1)
  override val in3 = in(2)
  override val in4 = in(4)

  override val out: OutputPort[bool] = out(0)
}
{'fraction_non_alphanumeric': 0.11606425702811245, 'fraction_numerical': 0.04899598393574297, 'mean_word_length': 3.7178030303030303, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 1, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6818607', 'n_tokens_mistral': 941, 'n_tokens_neox': 910, 'n_words': 298}