<commit_before>/**
 *
 * \file cc2430_sfr.h
 * \brief CC2430 registers header file for CC2430.
 *
 *  Definitions for CC2430 SFR registers.
 *   
 *	
 */

#ifndef REG_CC2430_H
#define REG_CC2430_H

/*  BYTE Register  */

__sfr __at (0x80) P0   ;
/* P0 */
__sbit __at (0x87) P0_7 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x80) P0_0 ;

__sfr __at (0x81) SP   ;
__sfr __at (0x82) DPL0  ;
__sfr __at (0x83) DPH0  ;
/*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
__sfr __at (0x84)   DPL1;
__sfr __at (0x85)   DPH1;
__sfr __at (0x86)   U0CSR;
#define U_MODE	0x80
#define U_RE	0x40
#define U_SLAVE	0x20
#define U_FE	0x10
#define U_ERR	0x08
#define U_RXB	0x04
#define	U_TXB	0x02
#define U_ACTIVE 0x01

__sfr __at (0x87) PCON ;
/*  PCON (0x87) */
#define IDLE 0x01

__sfr __at (0x88) TCON ;
/*  TCON (0x88) */
__sbit __at (0x8F) TCON_URX1IF;
/*__sbit __at (0x8E) RES;*/
__sbit __at (0x8D) TCON_ADCIF;
/*__sbit __at (0x8C) RES;*/
__sbit __at (0x8B) TCON_URX0IF;
__sbit __at (0x8A) TCON_IT1;
__sbit __at (0x89) TCON_RFERRIF;
__sbit __at (0x88) TCON_IT0;


__sfr __at (0x89)   P0IFG;
__sfr __at (0x8A)   P1IFG;
__sfr __at (0x8B)   P2IFG;
__sfr __at (0x8C)   PICTL;
/*PICTL bits*/
#define PADSC	0x40
#define P2IEN	0x20
#define P0IENH	0x10
#define P0IENL	0x08
#define P2ICON	0x04
#define P1ICON	0x02
#define P0ICON	0x01

__sfr __at (0x8D)   P1IEN;
__sfr __at (0x8F)   P0INP;

__sfr __at (0x90) P1   ;
/* P1 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;

__sfr __at (0x91)   RFIM;
__sfr __at (0x92)   DPS;
__sfr __at (0x93)   _XPAGE; /*MPAGE as paging register for sdcc*/
__sfr __at (0x94)   T2CMP;
__sfr __at (0x95)   ST0;
__sfr __at (0x96)   ST1;
__sfr __at (0x97)   ST2;
__sfr __at (0x98)   S0CON ;

__sbit __at (0x99) S0CON_ENCIF_1;
__sbit __at (0x98) S0CON_ENCIF_0;

__sfr __at (0x99)   HSRC;
__sfr __at (0x9A)   IEN2;
/*IEN2 bits*/
#define WDTIE	0x20
#define P1IE	0x10
#define UTX1IE	0x08
#define UTX0IE	0x04
#define P2IE	0x02
#define RFIE	0x01
__sfr __at (0x9B)   S1CON;
/*S1CON bits*/
#define RFIF_1	0x02
#define RFIF_0	0x01
__sfr __at (0x9C)   T2PEROF0;
__sfr __at (0x9D)   T2PEROF1;
__sfr __at (0x9E)   T2PEROF2;
/*T2PEROF2 bits*/
#define CMPIM	0x80
#define PERIM	0x40
#define OFCMPIM	0x20

#define PEROF23	0x08
#define PEROF22	0x04
#define PEROF21	0x02
#define PEROF20	0x01

__sfr __at (0x9F) FMAP;

__sfr __at (0xA0) P2   ;
/* P2 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
/*__sbit __at (0xA5) P2_5 ;<commit_msg>add definition for PSBANK used in sdcc crtbank.asm<commit_after>/**
 *
 * \file cc2430_sfr.h
 * \brief CC2430 registers header file for CC2430.
 *
 *  Definitions for CC2430 SFR registers.
 *   
 *	
 */

#ifndef REG_CC2430_H
#define REG_CC2430_H

/*  BYTE Register  */

__sfr __at (0x80) P0   ;
/* P0 */
__sbit __at (0x87) P0_7 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x80) P0_0 ;

__sfr __at (0x81) SP   ;
__sfr __at (0x82) DPL0  ;
__sfr __at (0x83) DPH0  ;
/*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
__sfr __at (0x84)   DPL1;
__sfr __at (0x85)   DPH1;
__sfr __at (0x86)   U0CSR;
#define U_MODE	0x80
#define U_RE	0x40
#define U_SLAVE	0x20
#define U_FE	0x10
#define U_ERR	0x08
#define U_RXB	0x04
#define	U_TXB	0x02
#define U_ACTIVE 0x01

__sfr __at (0x87) PCON ;
/*  PCON (0x87) */
#define IDLE 0x01

__sfr __at (0x88) TCON ;
/*  TCON (0x88) */
__sbit __at (0x8F) TCON_URX1IF;
/*__sbit __at (0x8E) RES;*/
__sbit __at (0x8D) TCON_ADCIF;
/*__sbit __at (0x8C) RES;*/
__sbit __at (0x8B) TCON_URX0IF;
__sbit __at (0x8A) TCON_IT1;
__sbit __at (0x89) TCON_RFERRIF;
__sbit __at (0x88) TCON_IT0;


__sfr __at (0x89)   P0IFG;
__sfr __at (0x8A)   P1IFG;
__sfr __at (0x8B)   P2IFG;
__sfr __at (0x8C)   PICTL;
/*PICTL bits*/
#define PADSC	0x40
#define P2IEN	0x20
#define P0IENH	0x10
#define P0IENL	0x08
#define P2ICON	0x04
#define P1ICON	0x02
#define P0ICON	0x01

__sfr __at (0x8D)   P1IEN;
__sfr __at (0x8F)   P0INP;

__sfr __at (0x90) P1   ;
/* P1 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;

__sfr __at (0x91)   RFIM;
__sfr __at (0x92)   DPS;
__sfr __at (0x93)   _XPAGE; /*MPAGE as paging register for sdcc*/
__sfr __at (0x94)   T2CMP;
__sfr __at (0x95)   ST0;
__sfr __at (0x96)   ST1;
__sfr __at (0x97)   ST2;
__sfr __at (0x98)   S0CON ;

__sbit __at (0x99) S0CON_ENCIF_1;
__sbit __at (0x98) S0CON_ENCIF_0;

__sfr __at (0x99)   HSRC;
__sfr __at (0x9A)   IEN2;
/*IEN2 bits*/
#define WDTIE	0x20
#define P1IE	0x10
#define UTX1IE	0x08
#define UTX0IE	0x04
#define P2IE	0x02
#define RFIE	0x01
__sfr __at (0x9B)   S1CON;
/*S1CON bits*/
#define RFIF_1	0x02
#define RFIF_0	0x01
__sfr __at (0x9C)   T2PEROF0;
__sfr __at (0x9D)   T2PEROF1;
__sfr __at (0x9E)   T2PEROF2;
/*T2PEROF2 bits*/
#define CMPIM	0x80
#define PERIM	0x40
#define OFCMPIM	0x20

#define PEROF23	0x08
#define PEROF22	0x04
#define PEROF21	0x02
#define PEROF20	0x01

__sfr __at (0x9F) FMAP;
__sfr __at (0x9F) PSBANK;

__sfr __at (0xA0) P2   ;
/* P2 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
/*__sbit __at (0xA5) P2_5 ;
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