<commit_before>// Copyright (C) 2015 <NAME>, <NAME>
// License: BSD 2-Clause (see LICENSE for details)

package TurboRav

import Chisel._
import Constants._

class Writeback extends Module {

  val io = new WritebackIO()

  val mem_wrb = Reg(init = new MemoryWriteback())
  unless(io.hdu_wrb.stall){
    mem_wrb := io.mem_wrb
  }

  val ctrl = mem_wrb.wrb_ctrl
  val word = mem_wrb.mem_read_data

  val half_of_word = UInt(word(16 - 1, 0), width = 16)
  val byte_of_word = UInt(word(8  - 1, 0), width = 8 )

  val mem_read = MuxCase( word, Array(
    ( ctrl.sign_extend && ctrl.is_halfword ) -> SignExtend(half_of_word, 32),
    (!ctrl.sign_extend && ctrl.is_halfword ) -> ZeroExtend(half_of_word, 32),
    ( ctrl.sign_extend && ctrl.is_byte     ) -> SignExtend(byte_of_word, 32),
    (!ctrl.sign_extend && ctrl.is_byte     ) -> ZeroExtend(byte_of_word, 32)
  ))

  val rd_data = Mux(ctrl.rd_sel === RD_PC,  mem_wrb.pc + UInt(4),
                Mux(ctrl.rd_sel === RD_MEM, mem_read,
                                            mem_wrb.alu_result))

  io.fwu_wrb.rd_addr             := mem_wrb.rd_addr
  io.wrb_exe.reg_write.bits.addr := mem_wrb.rd_addr
  io.wrb_exe.rd_data             := rd_data
  io.wrb_exe.reg_write.bits.data := rd_data
  io.fwu_wrb.rd_wen              := mem_wrb.wrb_ctrl.rd_wen
  io.wrb_exe.reg_write.valid     := mem_wrb.wrb_ctrl.rd_wen
}
<commit_msg>writeback: Refactor<commit_after>// Copyright (C) 2015 <NAME>, <NAME>
// License: BSD 2-Clause (see LICENSE for details)

package TurboRav

import Chisel._
import Constants._

class Writeback extends Module {

  val io = new WritebackIO()

  val mem_wrb = Reg(init = new MemoryWriteback())
  unless(io.hdu_wrb.stall){
    mem_wrb := io.mem_wrb
  }

  val ctrl = mem_wrb.wrb_ctrl
  val word = mem_wrb.mem_read_data

  val half_of_word = UInt(word(16 - 1, 0), width = 16)
  val byte_of_word = UInt(word(8  - 1, 0), width = 8 )

  val mem_read = MuxCase( word, Array(
    ( ctrl.sign_extend && ctrl.is_halfword ) -> SignExtend(half_of_word, 32),
    (!ctrl.sign_extend && ctrl.is_halfword ) -> ZeroExtend(half_of_word, 32),
    ( ctrl.sign_extend && ctrl.is_byte     ) -> SignExtend(byte_of_word, 32),
    (!ctrl.sign_extend && ctrl.is_byte     ) -> ZeroExtend(byte_of_word, 32)
  ))

  val pc_next = mem_wrb.pc + UInt(4) // TODO: This was expensive, 8ns

  val rd_data = Lookup(
    addr    = ctrl.rd_sel,
    default = mem_wrb.alu_result,
    mapping = Array(
      RD_PC  -> pc_next,
      RD_MEM -> mem_read
    )
  )

  io.fwu_wrb.rd_addr             := mem_wrb.rd_addr
  io.wrb_exe.reg_write.bits.addr := mem_wrb.rd_addr
  io.wrb_exe.rd_data             := rd_data
  io.wrb_exe.reg_write.bits.data := rd_data
  io.fwu_wrb.rd_wen              := mem_wrb.wrb_ctrl.rd_wen
  io.wrb_exe.reg_write.valid     := mem_wrb.wrb_ctrl.rd_wen
}

{'fraction_non_alphanumeric': 0.12562277580071174, 'fraction_numerical': 0.017437722419928827, 'mean_word_length': 2.8089430894308944, 'pattern_counts': {'":': 0, '<': 7, '<?xml version=': 0, '>': 17, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 2, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4718394', 'n_tokens_mistral': 1190, 'n_tokens_neox': 1114, 'n_words': 209}