<commit_before>import gen
import os
import sys
import string
from string import Template
from gen import Gen

from nysa.ibuilder.lib import utils
from nysa.ibuilder.lib import verilog_utils as vutils

class GenMemInterconnect(Gen):

  def __init__(self):
    return

  def gen_script (self, tags = {}, buf = "", user_paths = [], debug=False):
    buf = generate_wb_mem_interconnect(tags = tags, user_paths = user_paths, debug = debug)
    return buf

  def get_name (self):
    print "wishbone_mem_interconnect.py"



def generate_wb_mem_interconnect(tags = {}, user_paths = [], debug = False):

  num_slaves = len(tags["MEMORY"].keys())
  if debug: print "Number of slaves: %d" % num_slaves


  buf = ""

  #Allow errors to pass up to the calling class
  directory = utils.get_local_verilog_path("nysa-verilog")
  wb_i_loc = os.path.join(  directory,
                            "verilog",
                            "wishbone",
                            "interconnect",
                            "wishbone_mem_interconnect.v")

  f = open(wb_i_loc, "r")
  buf = f.read()<commit_msg>gen_mem_interconnect will now return with an empty buffer if no memory devices are specified<commit_after>import gen
import os
import sys
import string
from string import Template
from gen import Gen

from nysa.ibuilder.lib import utils
from nysa.ibuilder.lib import verilog_utils as vutils

class GenMemInterconnect(Gen):

  def __init__(self):
    return

  def gen_script (self, tags = {}, buf = "", user_paths = [], debug=False):
    buf = generate_wb_mem_interconnect(tags = tags, user_paths = user_paths, debug = debug)
    return buf

  def get_name (self):
    print "wishbone_mem_interconnect.py"



def generate_wb_mem_interconnect(tags = {}, user_paths = [], debug = False):

  if "MEMORY" not in tags:
    return ""

  num_slaves = len(tags["MEMORY"].keys())
  if debug: print "Number of slaves: %d" % num_slaves


  buf = ""

  #Allow errors to pass up to the calling class
  directory = utils.get_local_verilog_path("nysa-verilog")
  wb_i_loc = os.path.join(  directory,
                            "verilog",
                            "wishbone",
                            "interconnect",
                            "wishbone_mem_interconnect.v")

  f = open(wb_i_loc, "r")
  buf = f.read()
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{'dir': 'git-commits-cleaned', 'id': '526135', 'n_tokens_mistral': 739, 'n_tokens_neox': 723, 'n_words': 200}