<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p10/procedures/hwp/pm/p10_qme_sram_access.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2015,2020                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */

///
/// @file  p10_qme_sram_access.C
/// @brief Access data to or from the targetted QME's SRAM array.
///
// *HWP HWP Owner       : <NAME> <<EMAIL>>
// *HWP FW Owner        : <NAME> <<EMAIL>>
// *HWP Team            : PM
// *HWP Consumed by     : HS:CRO:SBE
///

// -----------------------------------------------------------------------------
//  Includes
// -----------------------------------------------------------------------------
#include <p10_qme_sram_access.H>
#include <p10_pm_sram_access_utils.H>
#include <multicast_group_defs.H>
#include "p10_scom_eq.H"

using namespace scomt::eq;
enum DELAY_VALUE
{
    NS_DELAY = 1000000,// 1,000,000 ns = 1ms
    SIM_CYCLE_DELAY = 1000
};

// ----------------------------------------------------------------------
// Constants
// ----------------------------------------------------------------------
const uint32_t QSAR_AUTO_INCREMENT_BIT = 63;
const uint32_t QSCR_SRAM_ACCESS_MODE_BIT = 0;

// These really should come from hcd_common RTC 210851
const uint32_t QME_SRAM_SIZE = 64 * 1024;
const uint32_t QME_SRAM_BASE_ADDR = 0xFFFF0000;

// -----------------------------------------------------------------------------
//  Loal Functions
// -----------------------------------------------------------------------------
fapi2::ReturnCode qme_sram_read_qsar(
    const fapi2::Target < fapi2::TARGET_TYPE_EQ | fapi2::TARGET_TYPE_MULTICAST, fapi2::MULTICAST_AND > & i_qme_target)
{
    fapi2::buffer<uint64_t> l_data64;

    auto l_chip = i_qme_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
    auto l_eq_vector = l_chip.getChildren<fapi2::TARGET_TYPE_EQ> (fapi2::TARGET_STATE_FUNCTIONAL);

    for (auto& eq : l_eq_vector)
    {
        FAPI_TRY(fapi2::getScom(eq, QME_QSAR, l_data64));
        FAPI_DBG("   QSAR = 0x%016llX", l_data64);
    }

fapi_try_exit:
    return fapi2::current_err;
}

// -----------------------------------------------------------------------------
//  Function definitions
// -----------------------------------------------------------------------------

/// @brief Internal function that that read/write data from/to the targetted
///        QME's SRAM array.
///
/// @param [in]  i_qme_target         EQ target
/// @param [in]  i_start_address      Start Address is between 0xFFFF80000 and 0xFFFFFFFF and must be 8B aligned
/// @param [in]  i_length             i_useByteBuffer = true : Length in bytes
///                                                     false: Length in double words
/// @param [in]  i_operation          Access operation to perform (GET/PUT/)
/// @param [out] io_data              In/Output Data pointer
/// @param [out] o_num_accessed       i_useByteBuffer = true : Number of byte accessed
///                                                     false: Number of double words accessed
/// @param [in]  i_useByteBuffer      true: data buffer is byte wide
///                                   false: data buffer is word wide.
///
/// @return fapi2::ReturnCode  FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode p10_qme_sram_access_internal(
    const fapi2::Target < fapi2::TARGET_TYPE_EQ | fapi2::TARGET_TYPE_MULTICAST, fapi2::MULTICAST_AND > & i_qme_target,
    const uint32_t i_start_address,
    const uint32_t i_length,
    const qmesram::Op i_operation,
    uint64_t*  io_data,
    uint32_t&  o_num_accessed,
    const bool i_useByteBuf = false)
{
    FAPI_DBG("> p10_qme_sram_access_internal - i_useByteBuf %d", i_useByteBuf);

    fapi2::buffer<uint64_t> l_data64;
    fapi2::buffer<uint64_t> l_qsar;
    fapi2::buffer<uint64_t> l_qscr;
    qmesram::Op     l_op;
    uint32_t l_timeout = 0;

    // These are initialized before being used.
    // Not doing an initial assignment to 0 to save space on the SBE.
    uint32_t l_norm_address;
    uint32_t l_words_to_access = i_length;

    if (i_useByteBuf)
    {
        l_words_to_access = i_length % 8 ? (i_length >> 3) + 1 : i_length >> 3; // 64-bit len
    }

    // Ensure the address is between 0xFFFF0000 and 0xFFFFFFFF.
    // No need to check the upper limit, since that will overflow the uint32_t data type.
    if (i_start_address < 0xFFFF0000)
    {
        // Return Error - invalid start address
        FAPI_DBG("Invalid Start Address 0x%.8X", i_start_address);
        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
                    "Invalid QME Start address");
    }

    if ((i_start_address & 0x00000007) != 0)
    {
        // Return Error - invalid start address alignment
        FAPI_DBG("Invalid Start Address alignment 0x%.8X", i_start_address);
        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
                    "Invalid QME Start address alignment");
    }

    //Check the qme sram ownership access
    FAPI_TRY(fapi2::getScom(i_qme_target, QME_FLAGS_RW, l_data64));
    FAPI_TRY(fapi2::getScom(i_qme_target, QME_QSCR_RW, l_qscr));

    l_timeout = 100; //wait for 100 ms
    FAPI_DBG("Waiting for the ownership and access mode to be cleared");

    while (l_data64.getBit(22) || l_qscr.getBit(QME_QSCR_SRAM_ACCESS_MODE))
    {
        FAPI_TRY(fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY));

        if (!l_timeout)
        {
            break;
        }

        FAPI_TRY(fapi2::getScom(i_qme_target, QME_FLAGS_RW, l_data64));
        FAPI_TRY(fapi2::getScom(i_qme_target, QME_QSCR_RW, l_qscr));
        l_timeout--;
    }

    if (!l_timeout)
    {
        FAPI_ERR("QME SRAM is not accessible , need to be retried");
        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_DENIED().
                    set_EQ_TARGET(i_qme_target).set_QME_FLAG(l_data64).
                    set_QSCR(l_qscr),<commit_msg>PM HWP: Some bug fixes in power down and qme sram access hwp<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p10/procedures/hwp/pm/p10_qme_sram_access.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2015,2020                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */

///
/// @file  p10_qme_sram_access.C
/// @brief Access data to or from the targetted QME's SRAM array.
///
// *HWP HWP Owner       : <NAME> <<EMAIL>>
// *HWP FW Owner        : <NAME> <<EMAIL>>
// *HWP Team            : PM
// *HWP Consumed by     : HS:CRO:SBE
///

// -----------------------------------------------------------------------------
//  Includes
// -----------------------------------------------------------------------------
#include <p10_qme_sram_access.H>
#include <p10_pm_sram_access_utils.H>
#include <multicast_group_defs.H>
#include "p10_scom_eq.H"

using namespace scomt::eq;
enum DELAY_VALUE
{
    NS_DELAY = 1000000,// 1,000,000 ns = 1ms
    SIM_CYCLE_DELAY = 1000
};

// ----------------------------------------------------------------------
// Constants
// ----------------------------------------------------------------------
const uint32_t QSAR_AUTO_INCREMENT_BIT = 63;
const uint32_t QSCR_SRAM_ACCESS_MODE_BIT = 0;

// These really should come from hcd_common RTC 210851
const uint32_t QME_SRAM_SIZE = 64 * 1024;
const uint32_t QME_SRAM_BASE_ADDR = 0xFFFF0000;

// -----------------------------------------------------------------------------
//  Loal Functions
// -----------------------------------------------------------------------------
fapi2::ReturnCode qme_sram_read_qsar(
    const fapi2::Target < fapi2::TARGET_TYPE_EQ | fapi2::TARGET_TYPE_MULTICAST, fapi2::MULTICAST_AND > & i_qme_target)
{
    fapi2::buffer<uint64_t> l_data64;

    auto l_chip = i_qme_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
    auto l_eq_vector = l_chip.getChildren<fapi2::TARGET_TYPE_EQ> (fapi2::TARGET_STATE_FUNCTIONAL);

    for (auto& eq : l_eq_vector)
    {
        FAPI_TRY(fapi2::getScom(eq, QME_QSAR, l_data64));
        FAPI_DBG("   QSAR = 0x%016llX", l_data64);
    }

fapi_try_exit:
    return fapi2::current_err;
}

// -----------------------------------------------------------------------------
//  Function definitions
// -----------------------------------------------------------------------------

/// @brief Internal function that that read/write data from/to the targetted
///        QME's SRAM array.
///
/// @param [in]  i_qme_target         EQ target
/// @param [in]  i_start_address      Start Address is between 0xFFFF80000 and 0xFFFFFFFF and must be 8B aligned
/// @param [in]  i_length             i_useByteBuffer = true : Length in bytes
///                                                     false: Length in double words
/// @param [in]  i_operation          Access operation to perform (GET/PUT/)
/// @param [out] io_data              In/Output Data pointer
/// @param [out] o_num_accessed       i_useByteBuffer = true : Number of byte accessed
///                                                     false: Number of double words accessed
/// @param [in]  i_useByteBuffer      true: data buffer is byte wide
///                                   false: data buffer is word wide.
///
/// @return fapi2::ReturnCode  FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode p10_qme_sram_access_internal(
    const fapi2::Target < fapi2::TARGET_TYPE_EQ | fapi2::TARGET_TYPE_MULTICAST, fapi2::MULTICAST_AND > & i_qme_target,
    const uint32_t i_start_address,
    const uint32_t i_length,
    const qmesram::Op i_operation,
    uint64_t*  io_data,
    uint32_t&  o_num_accessed,
    const bool i_useByteBuf = false)
{
    FAPI_DBG("> p10_qme_sram_access_internal - i_useByteBuf %d", i_useByteBuf);

    fapi2::buffer<uint64_t> l_data64;
    fapi2::buffer<uint64_t> l_qsar;
    fapi2::buffer<uint64_t> l_qscr;
    qmesram::Op     l_op;
    uint32_t l_timeout = 0;

    // These are initialized before being used.
    // Not doing an initial assignment to 0 to save space on the SBE.
    uint32_t l_norm_address;
    uint32_t l_words_to_access = i_length;

    if (i_useByteBuf)
    {
        l_words_to_access = i_length % 8 ? (i_length >> 3) + 1 : i_length >> 3; // 64-bit len
    }

    // Ensure the address is between 0xFFFF0000 and 0xFFFFFFFF.
    // No need to check the upper limit, since that will overflow the uint32_t data type.
    if (i_start_address < 0xFFFF0000)
    {
        // Return Error - invalid start address
        FAPI_DBG("Invalid Start Address 0x%.8X", i_start_address);
        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
                    "Invalid QME Start address");
    }

    if ((i_start_address & 0x00000007) != 0)
    {
        // Return Error - invalid start address alignment
        FAPI_DBG("Invalid Start Address alignment 0x%.8X", i_start_address);
        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
                    "Invalid QME Start address alignment");
    }

    //Check the qme sram ownership access
    FAPI_TRY(fapi2::getScom(i_qme_target, QME_FLAGS_RW, l_data64));
    FAPI_TRY(fapi2::getScom(i_qme_target, QME_QSCR_RW, l_qscr));

    l_timeout = 100; //wait for 100 ms
    FAPI_DBG("Waiting for the ownership and access mode to be cleared");

    while (l_data64.getBit(22) || l_qscr.getBit(QME_QSCR_SRAM_ACCESS_MODE))
    {
        FAPI_TRY(fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY));

        if (!l_timeout)
        {
            break;
        }

        FAPI_TRY(fapi2::getScom(i_qme_target, QME_FLAGS_RW, l_data64));
        FAPI_TRY(fapi2::getScom(i_qme_target, QME_QSCR_RW, l_qscr));
        l_timeout--;
    }

    if (!l_timeout)
    {
        FAPI_ERR("QME SRAM is not accessible , need to be retried");
        l_data64.flush<0>().setBit(0);
        FAPI_TRY(fapi2::putScom(i_qme_target, QME_QSCR_WO_CLEAR, l_data64));

        FAPI_ASSERT(false,
                    fapi2::QME_SRAM_ACCESS_DENIED().
                    set_EQ_TARGET(i_qme_target).set_QME_FLAG(l_data64).
                    set_QSCR(l_qscr),
{'fraction_non_alphanumeric': 0.16781534460338102, 'fraction_numerical': 0.026072821846553965, 'mean_word_length': 1.4070422535211267, 'pattern_counts': {'":': 0, '<': 40, '<?xml version=': 0, '>': 48, 'https://': 0, 'lorem ipsum': 0, 'www.': 2, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 6, 'word_list_counts': {'cursed_substrings.json': 72, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7485832', 'n_tokens_mistral': 4650, 'n_tokens_neox': 4306, 'n_words': 1037}