<commit_before>#=========================================================================
# verilog_behavioral.py
#=========================================================================

import ast, _ast
import collections
import inspect
import StringIO
import textwrap

from ..ast_helpers import get_method_ast, print_simple_ast
from ..signals     import InPort, OutPort

# TODO: HACKY
from verilog_structural import signal_to_str

import visitors

#-------------------------------------------------------------------------
# translate_logic_blocks
#-------------------------------------------------------------------------
def translate_logic_blocks( model, o ):

  blocks = ( model.get_posedge_clk_blocks()
           + model.get_combinational_blocks()
           + model.get_tick_blocks() )

  behavioral_code = StringIO.StringIO()

  # TODO: remove regs logic, move to own visitor that visits _ast.Store
  #       nodes!
  regs   = set()
  ints   = set()
  params = set()
  arrays = set()
  #temps = []

  for func in blocks:

    # Type Check the AST
    tree, src  = get_method_ast( func )
    new_tree   = ast_pipeline( tree, model, func )
    r,i,p,a    = visitors.GetRegsIntsParamsTempsArrays().get( new_tree )

    regs      |= r
    ints      |= i
    params    |= p
    arrays    |= a

    # Store the PyMTL source inline with the behavioral code
    block_code = ("  // PYMTL SOURCE:\n"
                  "  // {}\n\n").format( "\n  // ".join( src.splitlines()))

    # Print the Verilog translation
    visitor     = TranslateBehavioralVerilog()
    block_code += visitor.visit( new_tree )

    print >> behavioral_code, block_code

    # TODO: check for conflicts, ensure that signals are not written in
    #       two different behavioral blocks!

  # Print the reg declarations
  if regs:
    print   >> o, '  // register declarations'
    for signal in regs:
      print >> o, '  reg    [{:4}:0] {};'.format( signal.nbits-1,
          signal_to_str( signal, None, model ))

  # Print the parameter declarations
  if params:
    print   >> o, '  // param declarations'
    for param, value in params:
      print >> o, '  parameter {} = {};'.format( param, value )

  # Print the int declarations
  if ints:
    print   >> o, '  // loop variable declarations'
    for signal in ints:
      print >> o, '  integer {};'.format( signal )

  # Print the array declarations
  if arrays:
    print   >> o, '  // array declarations'
    for name, ports in arrays:
      print >> o, '  reg    [{:4}:0] {}[0:{}];'.format(
          ports[0].nbits-1, name, len(ports)-1)
      # TODO: check if input or output port
      if isinstance( ports[0], OutPort ):
        for i, port in enumerate(ports):
          print >> o, '  assign {0} = {1}[{2:3}];'.format(
              signal_to_str( port, None, model ), name, i )
      else:
        for i, port in enumerate(ports):
          print >> o, '  assign {1}[{2:3}] = {0};'.format(
              signal_to_str( port, None, model ), name, i )



  ## Print the temporary declarations
  ## TODO: this doesn't really work, need to set type of temp
  #if temps:
  #  print   >> o, '  // temporary declarations'
  #  for signal in temps:
  #    print >> o, '  reg {};'.format( signal )

  ## TODO: clean this up and move it somewhere else! Ugly!
  #print >> o
  #if array:
  #  print   >> o, '  // temporary arrays'
  #  for x in array:
  #    # declare the array
  #    nports = len( x )
  #    nbits  = x[0].nbits
  #    name   = x[0].name.split('[')[0]<commit_msg>[translation] fix bug with InPort array translation<commit_after>#=========================================================================
# verilog_behavioral.py
#=========================================================================

import ast, _ast
import collections
import inspect
import StringIO
import textwrap

from ..ast_helpers import get_method_ast, print_simple_ast
from ..signals     import InPort, OutPort

# TODO: HACKY
from verilog_structural import signal_to_str

import visitors

#-------------------------------------------------------------------------
# translate_logic_blocks
#-------------------------------------------------------------------------
def translate_logic_blocks( model, o ):

  blocks = ( model.get_posedge_clk_blocks()
           + model.get_combinational_blocks()
           + model.get_tick_blocks() )

  behavioral_code = StringIO.StringIO()

  # TODO: remove regs logic, move to own visitor that visits _ast.Store
  #       nodes!
  regs   = set()
  ints   = set()
  params = set()
  arrays = set()
  #temps = []

  for func in blocks:

    # Type Check the AST
    tree, src  = get_method_ast( func )
    new_tree   = ast_pipeline( tree, model, func )
    r,i,p,a    = visitors.GetRegsIntsParamsTempsArrays().get( new_tree )

    regs      |= r
    ints      |= i
    params    |= p
    arrays    |= a

    # Store the PyMTL source inline with the behavioral code
    block_code = ("  // PYMTL SOURCE:\n"
                  "  // {}\n\n").format( "\n  // ".join( src.splitlines()))

    # Print the Verilog translation
    visitor     = TranslateBehavioralVerilog()
    block_code += visitor.visit( new_tree )

    print >> behavioral_code, block_code

    # TODO: check for conflicts, ensure that signals are not written in
    #       two different behavioral blocks!

  # Print the reg declarations
  if regs:
    print   >> o, '  // register declarations'
    for signal in regs:
      print >> o, '  reg    [{:4}:0] {};'.format( signal.nbits-1,
          signal_to_str( signal, None, model ))

  # Print the parameter declarations
  if params:
    print   >> o, '  // param declarations'
    for param, value in params:
      print >> o, '  parameter {} = {};'.format( param, value )

  # Print the int declarations
  if ints:
    print   >> o, '  // loop variable declarations'
    for signal in ints:
      print >> o, '  integer {};'.format( signal )

  # Print the array declarations
  if arrays:
    print   >> o, '  // array declarations'
    for name, ports in arrays:
      # Output Port
      if isinstance( ports[0], OutPort ):
        print >> o, '  reg    [{:4}:0] {}[0:{}];'.format(
            ports[0].nbits-1, name, len(ports)-1)
        for i, port in enumerate(ports):
          print >> o, '  assign {0} = {1}[{2:3}];'.format(
              signal_to_str( port, None, model ), name, i )
      # Input Port
      else:
        print >> o, '  wire   [{:4}:0] {}[0:{}];'.format(
            ports[0].nbits-1, name, len(ports)-1)
        for i, port in enumerate(ports):
          print >> o, '  assign {1}[{2:3}] = {0};'.format(
              signal_to_str( port, None, model ), name, i )



  ## Print the temporary declarations
  ## TODO: this doesn't really work, need to set type of temp
  #if temps:
  #  print   >> o, '  // temporary declarations'
  #  for signal in temps:
  #    print >> o, '  reg {};'.format( signal )

  ## TODO: clean this up and move it somewhere else! Ugly!
  #print >> o
  #if array:
  #  print   >> o, '  // temporary arrays'
  #  for x in array:
  #    # declare the array
  #    nports = len( x )
  #    nbits  = x[0].nbits
  #    name   = x[0].name.split('[')[0]
{'fraction_non_alphanumeric': 0.1988312230416029, 'fraction_numerical': 0.006678725476554891, 'mean_word_length': 2.2117962466487935, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 65, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4662980', 'n_tokens_mistral': 2228, 'n_tokens_neox': 2128, 'n_words': 666}