<commit_before>/******************************************************************************\
* Project:  MSP Simulation Layer for Scalar Unit Operations                    *
* Authors:  Iconoclast                                                         *
* Release:  2015.01.27                                                         *
* License:  CC0 Public Domain Dedication                                       *
*                                                                              *
* To the extent possible under law, the author(s) have dedicated all copyright *
* and related and neighboring rights to this software to the public domain     *
* worldwide. This software is distributed without any warranty.                *
*                                                                              *
* You should have received a copy of the CC0 Public Domain Dedication along    *
* with this software.                                                          *
* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.             *
\******************************************************************************/

#define EMULATE_STATIC_PC

#include "su.h"

/*
 * including modular interface structure to access configuration settings...
 * Some of the parallel timing features require perfect timing or configs.
 */
#include "module.h"

int CPU_running;

u32 inst;

i32 SR[32];
typedef VECTOR_OPERATION(*p_vector_func)(v16, v16);

pu8 DRAM;
pu8 DMEM;
pu8 IMEM;

NOINLINE void res_S(void)
{
    message("RESERVED.");
    return;
}

void set_PC(int address)
{
    temp_PC = 0x04001000 + (address & 0xFFC);
#ifndef EMULATE_STATIC_PC
    stage = 1;
#endif
    return;
}

static word_32 SR_temp;

/*
 * All other behaviors defined below this point in the file are specific to
 * the SGI N64 extension to the MIPS R4000 and are not entirely implemented.
 */

pu32 CR[16];
u8 conf[32];

void SP_CP0_MF(int rt, int rd)
{
    SR[rt] = *(CR[rd]);
    SR[0] = 0x00000000;
    if (rd == 0x7)
    {
        if (CFG_MEND_SEMAPHORE_LOCK == 0)
            return;
        GET_RCP_REG(SP_SEMAPHORE_REG) = 0x00000001;
        GET_RCP_REG(SP_STATUS_REG) |= SP_STATUS_HALT; /* temporary hack */
        CPU_running = ~GET_RCP_REG(SP_STATUS_REG) & SP_STATUS_HALT;
        return;
    }
    if (rd == 0x4)
    {
        if (CFG_WAIT_FOR_CPU_HOST == 0)
            return;
        ++MFC0_count[rt];
        GET_RCP_REG(SP_STATUS_REG) |= (MFC0_count[rt] > 07);
        CPU_running = ~GET_RCP_REG(SP_STATUS_REG) & 1;
    }
    return;
}

static void MT_DMA_CACHE(int rt)
{
    *CR[0x0] = SR[rt] & 0xFFFFFFF8; /* & 0x00001FF8 */
    return; /* Reserved upper bits are ignored during DMA R/W. */
}
static void MT_DMA_DRAM(int rt)
{
    *CR[0x1] = SR[rt] & 0xFFFFFFF8; /* & 0x00FFFFF8 */
    return; /* Let the reserved bits get sent, but the pointer is 24-bit. */
}
static void MT_DMA_READ_LENGTH(int rt)
{
    *CR[0x2] = SR[rt] | 07;
    SP_DMA_READ();
    return;<commit_msg>changed MFC0 timeout interval from 8 to 8192 (stable, helps test)<commit_after>/******************************************************************************\
* Project:  MSP Simulation Layer for Scalar Unit Operations                    *
* Authors:  Iconoclast                                                         *
* Release:  2015.01.27                                                         *
* License:  CC0 Public Domain Dedication                                       *
*                                                                              *
* To the extent possible under law, the author(s) have dedicated all copyright *
* and related and neighboring rights to this software to the public domain     *
* worldwide. This software is distributed without any warranty.                *
*                                                                              *
* You should have received a copy of the CC0 Public Domain Dedication along    *
* with this software.                                                          *
* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.             *
\******************************************************************************/

#define EMULATE_STATIC_PC

/*
 * The number of times to tolerate executing `MFC0    $at, $c4`.
 * Replace $at with any register--the timeout limit is per each.
 *
 * Set to a higher value to avoid prematurely quitting the interpreter.
 * Set to a lower value for speed...you could get away with 10 sometimes.
 */
#define MF_SP_STATUS_TIMEOUT    8192

#include "su.h"

/*
 * including modular interface structure to access configuration settings...
 * Some of the parallel timing features require perfect timing or configs.
 */
#include "module.h"

int CPU_running;

u32 inst;

i32 SR[32];
typedef VECTOR_OPERATION(*p_vector_func)(v16, v16);

pu8 DRAM;
pu8 DMEM;
pu8 IMEM;

NOINLINE void res_S(void)
{
    message("RESERVED.");
    return;
}

void set_PC(int address)
{
    temp_PC = 0x04001000 + (address & 0xFFC);
#ifndef EMULATE_STATIC_PC
    stage = 1;
#endif
    return;
}

static word_32 SR_temp;

/*
 * All other behaviors defined below this point in the file are specific to
 * the SGI N64 extension to the MIPS R4000 and are not entirely implemented.
 */

pu32 CR[16];
u8 conf[32];

void SP_CP0_MF(int rt, int rd)
{
    SR[rt] = *(CR[rd]);
    SR[0] = 0x00000000;
    if (rd == 0x7)
    {
        if (CFG_MEND_SEMAPHORE_LOCK == 0)
            return;
        GET_RCP_REG(SP_SEMAPHORE_REG) = 0x00000001;
        GET_RCP_REG(SP_STATUS_REG) |= SP_STATUS_HALT; /* temporary hack */
        CPU_running = ~GET_RCP_REG(SP_STATUS_REG) & SP_STATUS_HALT;
        return;
    }
    if (rd == 0x4)
    {
        if (CFG_WAIT_FOR_CPU_HOST == 0)
            return;
        ++MFC0_count[rt];
        GET_RCP_REG(SP_STATUS_REG) |= (MFC0_count[rt] >= MF_SP_STATUS_TIMEOUT);
        CPU_running = ~GET_RCP_REG(SP_STATUS_REG) & 1;
    }
    return;
}

static void MT_DMA_CACHE(int rt)
{
    *CR[0x0] = SR[rt] & 0xFFFFFFF8ul; /* & 0x00001FF8 */
    return; /* Reserved upper bits are ignored during DMA R/W. */
}
static void MT_DMA_DRAM(int rt)
{
    *CR[0x1] = SR[rt] & 0xFFFFFFF8ul; /* & 0x00FFFFF8 */
    return; /* Let the reserved bits get sent, but the pointer is 24-bit. */
}
static void MT_DMA_READ_LENGTH(int rt)
{
    *CR[0x2] = SR[rt] | 07;
    SP_DMA_READ();
    return;
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