<commit_before>/*
 * @brief
 *
 * @note
 * Author: Mikeqin Fengling.<EMAIL>
 * 		   <EMAIL>
 *
 * @par
 * This is free and unencumbered software released into the public domain.
 * For details see the UNLICENSE file at the root of the source tree.
 */

#include <string.h>

#include "board.h"
#include "defines.h"
#include "avalon_a3222.h"
#include "protocol.h"
#include "sha2.h"

#define A3222_WORK_SIZE		(23 * 4)
#define A3222_WORK_CNT		8

#define A3222_REPORT_SIZE	12 /* work_id (8bytes) + nonce (4bytes) */
#define A3222_REPORT_CNT	12

static uint8_t g_asic_index;
static uint8_t g_freqflag;
static uint32_t g_freq[ASIC_COUNT][3];

static uint8_t g_a3222_works[A3222_WORK_SIZE * A3222_WORK_CNT];
static uint8_t g_a3222_reports[A3222_REPORT_SIZE * A3222_REPORT_CNT];
RINGBUFF_T a3222_txrb;
RINGBUFF_T a3222_rxrb;

static void load_init(void)
{
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 2, (IOCON_FUNC0));	/* LOAD */
	Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 2);

	Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 29, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* SCK0 */
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* MISO0 */
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* MOSI0 */
}

static void load_set(bool On)
{
	Chip_GPIO_SetPinState(LPC_GPIO, 0, 2, On);
}

static void spi_init(void)
{
	Chip_SSP_Init(LPC_SSP0);

	Chip_SSP_SetFormat(LPC_SSP0, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_MODE0);
	Chip_SSP_SetMaster(LPC_SSP0, 1);
	Chip_SSP_SetBitRate(LPC_SSP0, 1*1000*1000);
	Chip_SSP_Enable(LPC_SSP0);
}

void a3222_hw_init(void)
{
	load_init();
	spi_init();

	load_set(0);

	RingBuffer_Init(&a3222_txrb, g_a3222_works, A3222_WORK_SIZE, A3222_WORK_CNT);
	RingBuffer_Init(&a3222_rxrb, g_a3222_reports, A3222_REPORT_SIZE, A3222_REPORT_CNT);
}
void a3222_sw_init(void)
{
	uint8_t i;

	load_set(0);

	g_freqflag = 0;

	for (i = 0; i < ASIC_COUNT; i++) {
		g_freq[i][0] = A3222_DEFAULT_FREQ;
		g_freq[i][1] = A3222_DEFAULT_FREQ;
		g_freq[i][2] = A3222_DEFAULT_FREQ;
	}

	RingBuffer_Flush(&a3222_txrb);
	RingBuffer_Flush(&a3222_rxrb);
}

void a3222_roll_work(uint8_t *pkg, int ntime_offset)
{
	uint32_t timev;

	PACK32(pkg + 56, &timev);
	timev += ntime_offset;
	UNPACK32(timev, pkg + 56);<commit_msg>Firmware: Asic initialize<commit_after>/*
 * @brief
 *
 * @note
 * Author: Mikeqin <EMAIL>
 * 		   <EMAIL>
 *
 * @par
 * This is free and unencumbered software released into the public domain.
 * For details see the UNLICENSE file at the root of the source tree.
 */

#include <string.h>

#include "board.h"
#include "defines.h"
#include "avalon_a3222.h"
#include "protocol.h"
#include "sha2.h"

#define A3222_WORK_SIZE		(23 * 4)
#define A3222_WORK_CNT		8

#define A3222_REPORT_SIZE	12 /* work_id (8bytes) + nonce (4bytes) */
#define A3222_REPORT_CNT	12

static uint8_t g_asic_index;
static uint8_t g_freqflag;
static uint32_t g_freq[ASIC_COUNT][3];

static uint8_t g_a3222_works[A3222_WORK_SIZE * A3222_WORK_CNT];
static uint8_t g_a3222_reports[A3222_REPORT_SIZE * A3222_REPORT_CNT];
RINGBUFF_T a3222_txrb;
RINGBUFF_T a3222_rxrb;

static void load_init(void)
{
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 2, (IOCON_FUNC0));	/* LOAD */
	Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 2);

	Chip_IOCON_PinMuxSet(LPC_IOCON, 1, 29, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* SCK0 */
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* MISO0 */
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP));	/* MOSI0 */
}

static void load_set(bool On)
{
	Chip_GPIO_SetPinState(LPC_GPIO, 0, 2, On);
}

static void spi_init(void)
{
	Chip_SSP_Init(LPC_SSP0);

	Chip_SSP_SetFormat(LPC_SSP0, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_MODE0);
	Chip_SSP_SetMaster(LPC_SSP0, 1);
	Chip_SSP_SetBitRate(LPC_SSP0, 1*1000*1000);
	Chip_SSP_Enable(LPC_SSP0);
}

static void clk_init(void)
{
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 1, (IOCON_FUNC1 | IOCON_MODE_INACT));
	Chip_Clock_SetCLKOUTSource(SYSCTL_CLKOUTSRC_MAINSYSCLK, 2);
}

static void a3222_reset(void)
{
	Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 20);

	/* high -> low -> high */
	Chip_GPIO_SetPinState(LPC_GPIO, 0, 2, true);
	__NOP();
	Chip_GPIO_SetPinState(LPC_GPIO, 0, 2, false);
	__NOP();
	Chip_GPIO_SetPinState(LPC_GPIO, 0, 2, true);
	__NOP();
}

void a3222_hw_init(void)
{
	load_init();
	spi_init();
	clk_init();
	a3222_reset();

	load_set(0);

	RingBuffer_Init(&a3222_txrb, g_a3222_works, A3222_WORK_SIZE, A3222_WORK_CNT);
	RingBuffer_Init(&a3222_rxrb, g_a3222_reports, A3222_REPORT_SIZE, A3222_REPORT_CNT);
}
void a3222_sw_init(void)
{
	uint8_t i;

	load_set(0);

	g_freqflag = 0;

	for (i = 0; i < ASIC_COUNT; i++) {
		g_freq[i][0] = A3222_DEFAULT_FREQ;
		g_freq[i][1] = A3222_DEFAULT_FREQ;
		g_freq[i][2] = A3222_DEFAULT_FREQ;
	}

	RingBuffer_Flush(&a3222_txrb);
	RingBuffer_Flush(&a3222_rxrb);
}

void a3222_roll_work(uint8_t *pkg, int ntime_offset)
{
	uint32_t timev;

	PACK32(pkg + 56, &timev);
	timev += ntime_offset;
	UNPACK32(timev, pkg + 56);
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