<commit_before>{-# LANGUAGE
    DeriveDataTypeable #-}

-- | Types provided by the disassembler.
module Udis86.Types
  (  -- * Instructions
    Instruction(..)
  , Prefix(..)
  , Operand(..), Memory(..), Register(..), Pointer(..), Immediate(..)

    -- * Register types
  , GPR(..), Half(..)
  , Segment(..), ControlRegister(..), DebugRegister(..)
  , MMXRegister(..), X87Register(..), XMMRegister(..)

    -- * Word sizes
  , WordSize(..), bitsInWord

    -- * Opcodes
  , Opcode(..)

    -- * For internal use
  , register, opcode
  ) where

import Udis86.C
import Udis86.Opcode

import Data.Typeable ( Typeable )
import Data.Data     ( Data )
import Data.Maybe
import Data.Word

import qualified Data.IntMap as IM

-- | Some fields, such as immediate operands, come in different
--   widths.  We store the equivalent integer value in a @'Word64'@,
--   along with a @'WordSize'@ to indicate the original width.
data WordSize
  = Bits8
  | Bits16
  | Bits32
  | Bits64
  deriving (Eq, Ord, Show, Typeable, Data, Enum, Bounded)

-- | Number of bits in a word of a given size.
bitsInWord :: WordSize -> Int
bitsInWord Bits8  = 8
bitsInWord Bits16 = 16
bitsInWord Bits32 = 32
bitsInWord Bits64 = 64

-- | An `x86` \/ `amd64` register.
data Register
  = RegNone                 -- ^ No register specified.
  | Reg8   GPR Half         -- ^ Either 8-bit half of the low 16 bits
                            --   of a general-purpose register
  | Reg16  GPR              -- ^ Low 16 bits of a general-purpose register
                            --   (full register in 16-bit mode)
  | Reg32  GPR              -- ^ Low 32 bits of a general-purpose register
                            --   (full register in 32-bit mode)
  | Reg64  GPR              -- ^ Full 64-bit general-purpose register
  | RegSeg Segment          -- ^ Segment register
  | RegCtl ControlRegister  -- ^ Control register
  | RegDbg DebugRegister    -- ^ Debug register
  | RegMMX MMXRegister      -- ^ MMX register
  | RegX87 X87Register      -- ^ @x87@ floating point unit register
  | RegXMM XMMRegister      -- ^ XMM register
  | RegIP                   -- ^ Instruction pointer
  deriving (Eq, Ord, Show, Typeable, Data)

-- | A general-purpose register.
--
-- Names taken from the 64-bit architecture, but they map onto<commit_msg>doc changes<commit_after>{-# LANGUAGE
    DeriveDataTypeable #-}

-- | Types provided by the disassembler.
module Udis86.Types
  (  -- * Instructions
    Instruction(..)
  , Prefix(..)
  , Operand(..), Memory(..), Pointer(..), Immediate(..)

    -- * Registers
  , Register(..), GPR(..), Half(..)
  , Segment(..), ControlRegister(..), DebugRegister(..)
  , MMXRegister(..), X87Register(..), XMMRegister(..)

    -- * Word sizes
  , WordSize(..), bitsInWord

    -- * Opcodes
  , Opcode(..)

    -- * For internal use
  , register, opcode
  ) where

import Udis86.C
import Udis86.Opcode

import Data.Typeable ( Typeable )
import Data.Data     ( Data )
import Data.Maybe
import Data.Word

import qualified Data.IntMap as IM

-- | Some fields, such as immediate operands, come in different
--   widths.  We store the equivalent integer value in a @'Word64'@,
--   along with a @'WordSize'@ to indicate the original width.
data WordSize
  = Bits8
  | Bits16
  | Bits32
  | Bits64
  deriving (Eq, Ord, Show, Typeable, Data, Enum, Bounded)

-- | Number of bits in a word of a given size.
bitsInWord :: WordSize -> Int
bitsInWord Bits8  = 8
bitsInWord Bits16 = 16
bitsInWord Bits32 = 32
bitsInWord Bits64 = 64

-- | An `x86` \/ `amd64` register.
data Register
  = RegNone                 -- ^ No register specified.
  | Reg8   GPR Half         -- ^ Either 8-bit half of the low 16 bits
                            --   of a general-purpose register
  | Reg16  GPR              -- ^ Low 16 bits of a general-purpose register
                            --   (full register in 16-bit mode)
  | Reg32  GPR              -- ^ Low 32 bits of a general-purpose register
                            --   (full register in 32-bit mode)
  | Reg64  GPR              -- ^ Full 64-bit general-purpose register
  | RegSeg Segment          -- ^ Segment register
  | RegCtl ControlRegister  -- ^ Control register
  | RegDbg DebugRegister    -- ^ Debug register
  | RegMMX MMXRegister      -- ^ MMX register
  | RegX87 X87Register      -- ^ @x87@ floating point unit register
  | RegXMM XMMRegister      -- ^ XMM register
  | RegIP                   -- ^ Instruction pointer
  deriving (Eq, Ord, Show, Typeable, Data)

-- | A general-purpose register.
--
-- The names are taken from the 64-bit architecture, but they map onto
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{'dir': 'git-commits-cleaned', 'id': '57139', 'n_tokens_mistral': 1534, 'n_tokens_neox': 1433, 'n_words': 469}