<commit_before>/*
 * Copyright (C) 2016 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */

/**
 * @ingroup     cpu_atmega2560
 * @{
 *
 * @file
 * @brief       CMSIS style register definitions for the atmega2560
 *
 * @author      <NAME> <<EMAIL>>
 */

#ifndef ATMEGA2560_REGS_H
#define ATMEGA2560_REGS_H

#include <avr/io.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief   Register types
 * @{
 */
#define REG8                    volatile uint8_t
#define REG16                   volatile uint16_t
/** @} */

/**
 * @brief   Timer register map
 */
typedef struct {
    REG8    CRA;            /**< control A */
    REG8    CRB;            /**< control B */
    REG8    CRC;            /**< control C */
    REG8    reserved;       /**< reserved */
    REG16   CNT;            /**< counter */
    REG16   ICR;            /**< input capture */
    REG16   OCR[3];         /**< output compare */
} mega_timer_t;

/**
 * @brief   UART register map
 */
typedef struct {
    REG8    CSRA;               /**< control and status register A */
    REG8    CSRB;               /**< control and status register B */
    REG8    CSRC;               /**< control and status register C */
    REG8    reserved;           /**< reserved */
    REG16   BRR;                /**< baud rate register */
    REG8    DR;                 /**< data register */
} mega_uart_t;

/**
 * @brief    Base register address definitions
 * @{
 */
#define MEGA_TIMER1_BASE        (uint16_t *)(&TCCR1A)
#define MEGA_TIMER3_BASE        (uint16_t *)(&TCCR3A)
#define MEGA_TIMER4_BASE        (uint16_t *)(&TCCR4A)
#define MEGA_TIMER5_BASE        (uint16_t *)(&TCCR5A)

#define MEGA_UART0_BASE         ((uint16_t *)(&UCSR0A))
#define MEGA_UART1_BASE         ((uint16_t *)(&UCSR1A))
#define MEGA_UART2_BASE         ((uint16_t *)(&UCSR2A))
#define MEGA_UART3_BASE         ((uint16_t *)(&UCSR2A))
/** @} */

/**
 * @brief    Peripheral instances
 * @{
 */
#define MEGA_TIMER1             ((mega_timer_t *)MEGA_TIMER1_BASE)
#define MEGA_TIMER3             ((mega_timer_t *)MEGA_TIMER3_BASE)
#define MEGA_TIMER4             ((mega_timer_t *)MEGA_TIMER4_BASE)
#define MEGA_TIMER5             ((mega_timer_t *)MEGA_TIMER5_BASE)

#define MEGA_UART0              ((mega_uart_t *)MEGA_UART0_BASE)
#define MEGA_UART1              ((mega_uart_t *)MEGA_UART1_BASE)
#define MEGA_UART2              ((mega_uart_t *)MEGA_UART2_BASE)
#define MEGA_UART3              ((mega_uart_t *)MEGA_UART3_BASE)
/** @} */

#ifdef __cplusplus
}
#endif

#endif /* ATMEGA2560_REGS_H */
/** @} */
<commit_msg>cpu/atmega2560: fixed typo in reg definition<commit_after>/*
 * Copyright (C) 2016 <NAME>
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */

/**
 * @ingroup     cpu_atmega2560
 * @{
 *
 * @file
 * @brief       CMSIS style register definitions for the atmega2560
 *
 * @author      <NAME> <<EMAIL>>
 */

#ifndef ATMEGA2560_REGS_H
#define ATMEGA2560_REGS_H

#include <avr/io.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief   Register types
 * @{
 */
#define REG8                    volatile uint8_t
#define REG16                   volatile uint16_t
/** @} */

/**
 * @brief   Timer register map
 */
typedef struct {
    REG8    CRA;            /**< control A */
    REG8    CRB;            /**< control B */
    REG8    CRC;            /**< control C */
    REG8    reserved;       /**< reserved */
    REG16   CNT;            /**< counter */
    REG16   ICR;            /**< input capture */
    REG16   OCR[3];         /**< output compare */
} mega_timer_t;

/**
 * @brief   UART register map
 */
typedef struct {
    REG8    CSRA;               /**< control and status register A */
    REG8    CSRB;               /**< control and status register B */
    REG8    CSRC;               /**< control and status register C */
    REG8    reserved;           /**< reserved */
    REG16   BRR;                /**< baud rate register */
    REG8    DR;                 /**< data register */
} mega_uart_t;

/**
 * @brief    Base register address definitions
 * @{
 */
#define MEGA_TIMER1_BASE        (uint16_t *)(&TCCR1A)
#define MEGA_TIMER3_BASE        (uint16_t *)(&TCCR3A)
#define MEGA_TIMER4_BASE        (uint16_t *)(&TCCR4A)
#define MEGA_TIMER5_BASE        (uint16_t *)(&TCCR5A)

#define MEGA_UART0_BASE         ((uint16_t *)(&UCSR0A))
#define MEGA_UART1_BASE         ((uint16_t *)(&UCSR1A))
#define MEGA_UART2_BASE         ((uint16_t *)(&UCSR2A))
#define MEGA_UART3_BASE         ((uint16_t *)(&UCSR3A))
/** @} */

/**
 * @brief    Peripheral instances
 * @{
 */
#define MEGA_TIMER1             ((mega_timer_t *)MEGA_TIMER1_BASE)
#define MEGA_TIMER3             ((mega_timer_t *)MEGA_TIMER3_BASE)
#define MEGA_TIMER4             ((mega_timer_t *)MEGA_TIMER4_BASE)
#define MEGA_TIMER5             ((mega_timer_t *)MEGA_TIMER5_BASE)

#define MEGA_UART0              ((mega_uart_t *)MEGA_UART0_BASE)
#define MEGA_UART1              ((mega_uart_t *)MEGA_UART1_BASE)
#define MEGA_UART2              ((mega_uart_t *)MEGA_UART2_BASE)
#define MEGA_UART3              ((mega_uart_t *)MEGA_UART3_BASE)
/** @} */

#ifdef __cplusplus
}
#endif

#endif /* ATMEGA2560_REGS_H */
/** @} */

{'fraction_non_alphanumeric': 0.12867443150305047, 'fraction_numerical': 0.036975411351451284, 'mean_word_length': 2.125361062969382, 'pattern_counts': {'":': 0, '<': 38, '<?xml version=': 0, '>': 12, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4427404', 'n_tokens_mistral': 2015, 'n_tokens_neox': 1888, 'n_words': 447}