<commit_before>#
# ------------------------------------------------------------
# Copyright (c) All rights reserved
# SiLab, Institute of Physics, University of Bonn
# ------------------------------------------------------------
#

import logging

from basil.HL.HardwareLayer import HardwareLayer

class MIO_PLL(HardwareLayer):
    '''
    CY22150 PLL
    
    Output frequency range: 80 kHz to 200 MHz
    
    Physical connection on MIO board:
     - 48 MHz reference clock input from USB uC
     - LCK1 PLL clock output connected to FPGA (LOC P9, GCLK2)
    
    Use yaml configuration:
    
    - name      : MIO_PLL
      type      : MIO_PLL<commit_msg>add whitespavce<commit_after>#
# ------------------------------------------------------------
# Copyright (c) All rights reserved
# SiLab, Institute of Physics, University of Bonn
# ------------------------------------------------------------
#

import logging

from basil.HL.HardwareLayer import HardwareLayer


class MIO_PLL(HardwareLayer):
    '''
    CY22150 PLL
    
    Output frequency range: 80 kHz to 200 MHz
    
    Physical connection on MIO board:
     - 48 MHz reference clock input from USB uC
     - LCK1 PLL clock output connected to FPGA (LOC P9, GCLK2)
    
    Use yaml configuration:
    
    - name      : MIO_PLL
      type      : MIO_PLL
{'fraction_non_alphanumeric': 0.2304776345716452, 'fraction_numerical': 0.022744503411675512, 'mean_word_length': 1.4220183486238531, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1260792', 'n_tokens_mistral': 384, 'n_tokens_neox': 334, 'n_words': 122}