<commit_before>/* SPDX-License-Identifier: BSD-2-Clause */
/*
 * Copyright (c) 2016, Linaro Limited
 * Copyright (c) 2014, STMicroelectronics International N.V.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef ARM32_H
#define ARM32_H

#include <sys/cdefs.h>
#include <stdint.h>
#include <util.h>

#define CORTEX_A7_PART_NUM		0xC07
#define CORTEX_A8_PART_NUM		0xC08
#define CORTEX_A9_PART_NUM		0xC09
#define CORTEX_A15_PART_NUM		0xC0F
#define CORTEX_A17_PART_NUM		0xC0E
#define CORTEX_A57_PART_NUM		0xD07
#define CORTEX_A72_PART_NUM		0xD08
#define CORTEX_A73_PART_NUM		0xD09
#define CORTEX_A75_PART_NUM		0xD0A

#define MIDR_PRIMARY_PART_NUM_SHIFT	4
#define MIDR_PRIMARY_PART_NUM_WIDTH	12

#define MIDR_IMPLEMENTER_SHIFT		24
#define MIDR_IMPLEMENTER_WIDTH		8
#define MIDR_IMPLEMENTER_ARM		0x41

#define CPSR_MODE_MASK	ARM32_CPSR_MODE_MASK
#define CPSR_MODE_USR	ARM32_CPSR_MODE_USR
#define CPSR_MODE_FIQ	ARM32_CPSR_MODE_FIQ
#define CPSR_MODE_IRQ	ARM32_CPSR_MODE_IRQ
#define CPSR_MODE_SVC	ARM32_CPSR_MODE_SVC
#define CPSR_MODE_MON	ARM32_CPSR_MODE_MON
#define CPSR_MODE_ABT	ARM32_CPSR_MODE_ABT
#define CPSR_MODE_UND	ARM32_CPSR_MODE_UND
#define CPSR_MODE_SYS	ARM32_CPSR_MODE_SYS

#define CPSR_T		ARM32_CPSR_T
#define CPSR_F_SHIFT	ARM32_CPSR_F_SHIFT
#define CPSR_F		ARM32_CPSR_F
#define CPSR_I		ARM32_CPSR_I
#define CPSR_A		ARM32_CPSR_A
#define CPSR_FIA	ARM32_CPSR_FIA
#define CPSR_IT_MASK	ARM32_CPSR_IT_MASK
#define CPSR_IT_MASK1	ARM32_CPSR_IT_MASK1
#define CPSR_IT_MASK2	ARM32_CPSR_IT_MASK2

#define SCR_NS		BIT32(0)
#define SCR_IRQ		BIT32(1)
#define SCR_FIQ		BIT32(2)
#define SCR_EA		BIT32(3)
#define SCR_FW		BIT32(4)
#define SCR_AW		BIT32(5)
#define SCR_NET		BIT32(6)
#define SCR_SCD		BIT32(7)
#define SCR_HCE		BIT32(8)
#define SCR_SIF		BIT32(9)

#define SCTLR_M		BIT32(0)
#define SCTLR_A		BIT32(1)
#define SCTLR_C		BIT32(2)
#define SCTLR_CP15BEN	BIT32(5)
#define SCTLR_SW	BIT32(10)
#define SCTLR_Z		BIT32(11)
#define SCTLR_I		BIT32(12)
#define SCTLR_V		BIT32(13)
#define SCTLR_RR	BIT32(14)
#define SCTLR_HA	BIT32(17)
#define SCTLR_WXN	BIT32(19)
#define SCTLR_UWXN	BIT32(20)
#define SCTLR_FI	BIT32(21)
#define SCTLR_VE	BIT32(24)
#define SCTLR_EE	BIT32(25)
#define SCTLR_NMFI	BIT32(26)
#define SCTLR_TRE	BIT32(28)
#define SCTLR_AFE	BIT32(29)
#define SCTLR_TE	BIT32(30)

#define ACTLR_SMP	BIT32(6)
#define ACTLR_DODMBS	BIT32(10)
#define ACTLR_L2RADIS	BIT32(11)
#define ACTLR_L1RADIS	BIT32(12)
#define ACTLR_L1PCTL	BIT32(13)
#define ACTLR_DDVM	BIT32(15)
#define ACTLR_DDI	BIT32(28)

#define NSACR_CP10	BIT32(10)
#define NSACR_CP11	BIT32(11)
#define NSACR_NSD32DIS	BIT32(14)
#define NSACR_NSASEDIS	BIT32(15)
#define NSACR_NS_L2ERR	BIT32(17)
#define NSACR_NS_SMP	BIT32(18)

#define CPACR_ASEDIS	BIT32(31)
#define CPACR_D32DIS	BIT32(30)
#define CPACR_CP(co_proc, access)	SHIFT_U32((access), ((co_proc) * 2))
#define CPACR_CP_ACCESS_DENIED		0x0
#define CPACR_CP_ACCESS_PL1_ONLY	0x1
#define CPACR_CP_ACCESS_FULL		0x3


#define DACR_DOMAIN(num, perm)		SHIFT_U32((perm), ((num) * 2))<commit_msg>core: arm32.h: remove unused ACTLR_* defines<commit_after>/* SPDX-License-Identifier: BSD-2-Clause */
/*
 * Copyright (c) 2016, Linaro Limited
 * Copyright (c) 2014, STMicroelectronics International N.V.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef ARM32_H
#define ARM32_H

#include <sys/cdefs.h>
#include <stdint.h>
#include <util.h>

#define CORTEX_A7_PART_NUM		0xC07
#define CORTEX_A8_PART_NUM		0xC08
#define CORTEX_A9_PART_NUM		0xC09
#define CORTEX_A15_PART_NUM		0xC0F
#define CORTEX_A17_PART_NUM		0xC0E
#define CORTEX_A57_PART_NUM		0xD07
#define CORTEX_A72_PART_NUM		0xD08
#define CORTEX_A73_PART_NUM		0xD09
#define CORTEX_A75_PART_NUM		0xD0A

#define MIDR_PRIMARY_PART_NUM_SHIFT	4
#define MIDR_PRIMARY_PART_NUM_WIDTH	12

#define MIDR_IMPLEMENTER_SHIFT		24
#define MIDR_IMPLEMENTER_WIDTH		8
#define MIDR_IMPLEMENTER_ARM		0x41

#define CPSR_MODE_MASK	ARM32_CPSR_MODE_MASK
#define CPSR_MODE_USR	ARM32_CPSR_MODE_USR
#define CPSR_MODE_FIQ	ARM32_CPSR_MODE_FIQ
#define CPSR_MODE_IRQ	ARM32_CPSR_MODE_IRQ
#define CPSR_MODE_SVC	ARM32_CPSR_MODE_SVC
#define CPSR_MODE_MON	ARM32_CPSR_MODE_MON
#define CPSR_MODE_ABT	ARM32_CPSR_MODE_ABT
#define CPSR_MODE_UND	ARM32_CPSR_MODE_UND
#define CPSR_MODE_SYS	ARM32_CPSR_MODE_SYS

#define CPSR_T		ARM32_CPSR_T
#define CPSR_F_SHIFT	ARM32_CPSR_F_SHIFT
#define CPSR_F		ARM32_CPSR_F
#define CPSR_I		ARM32_CPSR_I
#define CPSR_A		ARM32_CPSR_A
#define CPSR_FIA	ARM32_CPSR_FIA
#define CPSR_IT_MASK	ARM32_CPSR_IT_MASK
#define CPSR_IT_MASK1	ARM32_CPSR_IT_MASK1
#define CPSR_IT_MASK2	ARM32_CPSR_IT_MASK2

#define SCR_NS		BIT32(0)
#define SCR_IRQ		BIT32(1)
#define SCR_FIQ		BIT32(2)
#define SCR_EA		BIT32(3)
#define SCR_FW		BIT32(4)
#define SCR_AW		BIT32(5)
#define SCR_NET		BIT32(6)
#define SCR_SCD		BIT32(7)
#define SCR_HCE		BIT32(8)
#define SCR_SIF		BIT32(9)

#define SCTLR_M		BIT32(0)
#define SCTLR_A		BIT32(1)
#define SCTLR_C		BIT32(2)
#define SCTLR_CP15BEN	BIT32(5)
#define SCTLR_SW	BIT32(10)
#define SCTLR_Z		BIT32(11)
#define SCTLR_I		BIT32(12)
#define SCTLR_V		BIT32(13)
#define SCTLR_RR	BIT32(14)
#define SCTLR_HA	BIT32(17)
#define SCTLR_WXN	BIT32(19)
#define SCTLR_UWXN	BIT32(20)
#define SCTLR_FI	BIT32(21)
#define SCTLR_VE	BIT32(24)
#define SCTLR_EE	BIT32(25)
#define SCTLR_NMFI	BIT32(26)
#define SCTLR_TRE	BIT32(28)
#define SCTLR_AFE	BIT32(29)
#define SCTLR_TE	BIT32(30)

#define ACTLR_SMP	BIT32(6)

#define NSACR_CP10	BIT32(10)
#define NSACR_CP11	BIT32(11)
#define NSACR_NSD32DIS	BIT32(14)
#define NSACR_NSASEDIS	BIT32(15)
#define NSACR_NS_L2ERR	BIT32(17)
#define NSACR_NS_SMP	BIT32(18)

#define CPACR_ASEDIS	BIT32(31)
#define CPACR_D32DIS	BIT32(30)
#define CPACR_CP(co_proc, access)	SHIFT_U32((access), ((co_proc) * 2))
#define CPACR_CP_ACCESS_DENIED		0x0
#define CPACR_CP_ACCESS_PL1_ONLY	0x1
#define CPACR_CP_ACCESS_FULL		0x3


#define DACR_DOMAIN(num, perm)		SHIFT_U32((perm), ((num) * 2))
{'fraction_non_alphanumeric': 0.06892439780586693, 'fraction_numerical': 0.06642022418316242, 'mean_word_length': 6.211521926053311, 'pattern_counts': {'":': 0, '<': 9, '<?xml version=': 0, '>': 9, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2948561', 'n_tokens_mistral': 3841, 'n_tokens_neox': 3500, 'n_words': 908}