<commit_before>use bit_field::BitField;
use core::instruction::Instruction;
use core::ThumbCode;

#[cfg(test)]
use core::register::{Reg, SpecialReg};
#[cfg(test)]
use core::instruction::CpsEffect;

#[cfg(test)]
use core::condition::Condition;

mod and;
mod adc;
mod add;
mod adr;
mod asr;

mod b;
mod bic;
mod blx;
mod bx;
mod bl;
mod bkpt;

mod cmn;
mod cmp;
mod control;
mod cps;

mod eor;

mod ldm;
mod ldr;
mod ldrb;
mod ldrh;
mod ldrsh;
mod ldrsb;
mod lsl;
mod lsr;
mod mov;
mod mvn;
mod mul;
mod mrs;
mod msr;

mod nop;
mod orr;

mod push;
mod pop;

mod rev;
mod rsb;
mod ror;

mod sbc;
mod stm;
mod str;
mod sub;
mod sxt;
mod tst;
mod uxt;

use decoder::adc::*;
use decoder::add::*;
use decoder::adr::*;
use decoder::and::*;
use decoder::asr::*;

use decoder::b::*;
use decoder::bic::*;
use decoder::bx::*;
use decoder::blx::*;
use decoder::bl::*;
use decoder::bkpt::*;

use decoder::cmn::*;
use decoder::cmp::*;
use decoder::control::*;
use decoder::cps::*;

use decoder::eor::*;

use decoder::ldm::*;
use decoder::ldr::*;
use decoder::ldrb::*;
use decoder::ldrh::*;
use decoder::ldrsh::*;
use decoder::ldrsb::*;
use decoder::lsl::*;
use decoder::lsr::*;

use decoder::mov::*;
use decoder::mul::*;
use decoder::mvn::*;
use decoder::mrs::*;
use decoder::msr::*;

use decoder::nop::*;
use decoder::orr::*;
use decoder::push::*;
use decoder::pop::*;

use decoder::rev::*;
use decoder::rsb::*;
use decoder::ror::*;

use decoder::sbc::*;
use decoder::sub::*;
use decoder::stm::*;
use decoder::str::*;
use decoder::sxt::*;
use decoder::tst::*;
use decoder::uxt::*;

pub fn is_thumb32(word: u16) -> bool {
    match word.get_bits(11..16) {
        0b11101 | 0b11110 | 0b11111 => true,
        _ => false,
    }
}

#[allow(non_snake_case)]
fn decode_undefined(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}


#[allow(non_snake_case)]
fn decode_WFI_t1(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}

#[allow(non_snake_case)]
fn decode_WFE_t1(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}

#[allow(non_snake_case)]
fn decode_YIELD_t1(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}

#[allow(non_snake_case)]
fn decode_SEV_t1(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}

pub fn decode_16(opcode: u16) -> Instruction {
    match opcode {
        0...2047 => decode_MOV_reg_t2_LSL_imm_t1(opcode),
        2048...4095 => decode_LSR_imm_t1(opcode),
        4096...6143 => decode_ASR_imm_t1(opcode),
        6144...6655 => decode_ADD_reg_t1(opcode),
        6656...7167 => decode_SUB_reg_t1(opcode),
        7168...7679 => decode_ADD_imm_t1(opcode),
        7680...8191 => decode_SUB_imm_t1(opcode),
        8192...10239 => decode_MOV_imm_t1(opcode),
        10240...12287 => decode_CMP_imm_t1(opcode),
        12288...14335 => decode_ADD_imm_t2(opcode),
        14336...16383 => decode_SUB_imm_t2(opcode),
        16384...16447 => decode_AND_reg_t1(opcode),
        16448...16511 => decode_EOR_reg_t1(opcode),
        16512...16575 => decode_LSL_reg_t1(opcode),
        16576...16639 => decode_LSR_reg_t1(opcode),
        16640...16703 => decode_ASR_reg_t1(opcode),
        16704...16767 => decode_ADC_reg_t1(opcode),
        16768...16831 => decode_SBC_reg_t1(opcode),
        16832...16895 => decode_ROR_reg_t1(opcode),
        16896...16959 => decode_TST_reg_t1(opcode),
        16960...17023 => decode_RSB_imm_t1(opcode),
        17024...17087 => decode_CMP_reg_t1(opcode),
        17088...17151 => decode_CMN_reg_t1(opcode),
        17152...17215 => decode_ORR_reg_t1(opcode),
        17216...17279 => decode_MUL_t1(opcode),
        17280...17343 => decode_BIC_reg_t1(opcode),
        17344...17407 => decode_MVN_reg_t1(opcode),
        17408...17663 => decode_ADD_reg_t2_ADD_SP_reg(opcode),
        17664...17919 => decode_CMP_reg_t2(opcode),
        17920...18175 => decode_MOV_reg_t1(opcode),
        18176...18296 => decode_BX_t1(opcode),
        18304...18424 => decode_BLX_t1(opcode),
        18432...20479 => decode_LDR_lit_t1(opcode),
        20480...20991 => decode_STR_reg_t1(opcode),
        20992...21503 => decode_STRH_reg_t1(opcode),
        21504...22015 => decode_STRB_reg_t1(opcode),
        22016...22527 => decode_LDRSB_reg_t1(opcode),
        22528...23039 => decode_LDR_reg_t1(opcode),
        23040...23551 => decode_LDRH_reg_t1(opcode),
        23552...24063 => decode_LDRB_reg_t1(opcode),
        24064...24575 => decode_LDRSH_reg_t1(opcode),
        24576...26623 => decode_STR_imm_t1(opcode),
        26624...28671 => decode_LDR_imm_t1(opcode),
        28672...30719 => decode_STRB_imm_t1(opcode),
        30720...32767 => decode_LDRB_imm_t1(opcode),
        32768...34815 => decode_STRH_imm_t1(opcode),
        34816...36863 => decode_LDRH_imm_t1(opcode),
        36864...38911 => decode_STR_imm_t2(opcode),
        38912...40959 => decode_LDR_imm_t2(opcode),
        40960...43007 => decode_ADR_t1(opcode),
        43008...45055 => decode_ADD_SP_imm_t1(opcode),
        45056...45183 => decode_ADD_SP_imm_t2(opcode),
        45184...45311 => decode_SUB_SP_imm_t1(opcode),
        45568...45631 => decode_SXTH_t1(opcode),
        45632...45695 => decode_SXTB_t1(opcode),
        45696...45759 => decode_UXTH_t1(opcode),
        45760...45823 => decode_UXTB_t1(opcode),
        46080...46591 => decode_PUSH_t1(opcode),
        46690...46706 => decode_CPS_t1(opcode),
        47616...47679 => decode_REV_t1(opcode),
        47680...47743 => decode_REV16_t1(opcode),
        47808...47871 => decode_REVSH_t1(opcode),
        48128...48639 => decode_POP_reg_t1(opcode),
        48640...48895 => decode_BKPT_t1(opcode),
        48896...48896 => decode_NOP_t1(opcode),
        48912...48912 => decode_YIELD_t1(opcode),
        48928...48928 => decode_WFE_t1(opcode),
        48944...48944 => decode_WFI_t1(opcode),
        48960...48960 => decode_SEV_t1(opcode),
        49152...51199 => decode_STM_t1(opcode),
        51200...53247 => decode_LDM_t1(opcode),
        53248...57343 => decode_B_t1_SVC_t1(opcode),
        57344...59391 => decode_B_t2(opcode),
        _ => decode_undefined(opcode),
    }
}

//A 5.3.1 Branch and misc (thumb32)
pub fn decode_branch_and_misc(t1: u16, t2: u16) -> Instruction {
    let op2 = t2.get_bits(12..15);
    let op1 = t1.get_bits(4..11);

    match op2 {
        0x7 | 0x5 => decode_bl(t1, t2),
        0 => match op1 {
            0b0111000 | 0b0111001 => decode_msr_reg(t1, t2),
            0b0111011 => decode_control(t1, t2),
            0b0111111 | 0b0111110 => decode_mrs(t1, t2),
            _ => Instruction::UDF {
                imm32: 0,
                opcode: ThumbCode::from(((t1 as u32) << 16) + t2 as u32),
            },
        },
        _ => Instruction::UDF {
            imm32: 0,
            opcode: ThumbCode::from(((t1 as u32) << 16) + t2 as u32),
        },
    }
}
<commit_msg>WFE, WFI, YIELD, SEV decoding<commit_after>use bit_field::BitField;
use core::instruction::Instruction;
use core::ThumbCode;

#[cfg(test)]
use core::register::{Reg, SpecialReg};
#[cfg(test)]
use core::instruction::CpsEffect;

#[cfg(test)]
use core::condition::Condition;

mod and;
mod adc;
mod add;
mod adr;
mod asr;

mod b;
mod bic;
mod blx;
mod bx;
mod bl;
mod bkpt;

mod cmn;
mod cmp;
mod control;
mod cps;

mod eor;

mod ldm;
mod ldr;
mod ldrb;
mod ldrh;
mod ldrsh;
mod ldrsb;
mod lsl;
mod lsr;
mod mov;
mod mvn;
mod mul;
mod mrs;
mod msr;

mod nop;
mod orr;

mod push;
mod pop;

mod rev;
mod rsb;
mod ror;

mod sbc;
mod stm;
mod str;
mod sub;
mod sxt;
mod tst;
mod uxt;

use decoder::adc::*;
use decoder::add::*;
use decoder::adr::*;
use decoder::and::*;
use decoder::asr::*;

use decoder::b::*;
use decoder::bic::*;
use decoder::bx::*;
use decoder::blx::*;
use decoder::bl::*;
use decoder::bkpt::*;

use decoder::cmn::*;
use decoder::cmp::*;
use decoder::control::*;
use decoder::cps::*;

use decoder::eor::*;

use decoder::ldm::*;
use decoder::ldr::*;
use decoder::ldrb::*;
use decoder::ldrh::*;
use decoder::ldrsh::*;
use decoder::ldrsb::*;
use decoder::lsl::*;
use decoder::lsr::*;

use decoder::mov::*;
use decoder::mul::*;
use decoder::mvn::*;
use decoder::mrs::*;
use decoder::msr::*;

use decoder::nop::*;
use decoder::orr::*;
use decoder::push::*;
use decoder::pop::*;

use decoder::rev::*;
use decoder::rsb::*;
use decoder::ror::*;

use decoder::sbc::*;
use decoder::sub::*;
use decoder::stm::*;
use decoder::str::*;
use decoder::sxt::*;
use decoder::tst::*;
use decoder::uxt::*;

pub fn is_thumb32(word: u16) -> bool {
    match word.get_bits(11..16) {
        0b11101 | 0b11110 | 0b11111 => true,
        _ => false,
    }
}

#[allow(non_snake_case)]
fn decode_undefined(opcode: u16) -> Instruction {
    Instruction::UDF {
        imm32: 0,
        opcode: ThumbCode::from(opcode),
    }
}

pub fn decode_16(opcode: u16) -> Instruction {
    match opcode {
        0...2047 => decode_MOV_reg_t2_LSL_imm_t1(opcode),
        2048...4095 => decode_LSR_imm_t1(opcode),
        4096...6143 => decode_ASR_imm_t1(opcode),
        6144...6655 => decode_ADD_reg_t1(opcode),
        6656...7167 => decode_SUB_reg_t1(opcode),
        7168...7679 => decode_ADD_imm_t1(opcode),
        7680...8191 => decode_SUB_imm_t1(opcode),
        8192...10239 => decode_MOV_imm_t1(opcode),
        10240...12287 => decode_CMP_imm_t1(opcode),
        12288...14335 => decode_ADD_imm_t2(opcode),
        14336...16383 => decode_SUB_imm_t2(opcode),
        16384...16447 => decode_AND_reg_t1(opcode),
        16448...16511 => decode_EOR_reg_t1(opcode),
        16512...16575 => decode_LSL_reg_t1(opcode),
        16576...16639 => decode_LSR_reg_t1(opcode),
        16640...16703 => decode_ASR_reg_t1(opcode),
        16704...16767 => decode_ADC_reg_t1(opcode),
        16768...16831 => decode_SBC_reg_t1(opcode),
        16832...16895 => decode_ROR_reg_t1(opcode),
        16896...16959 => decode_TST_reg_t1(opcode),
        16960...17023 => decode_RSB_imm_t1(opcode),
        17024...17087 => decode_CMP_reg_t1(opcode),
        17088...17151 => decode_CMN_reg_t1(opcode),
        17152...17215 => decode_ORR_reg_t1(opcode),
        17216...17279 => decode_MUL_t1(opcode),
        17280...17343 => decode_BIC_reg_t1(opcode),
        17344...17407 => decode_MVN_reg_t1(opcode),
        17408...17663 => decode_ADD_reg_t2_ADD_SP_reg(opcode),
        17664...17919 => decode_CMP_reg_t2(opcode),
        17920...18175 => decode_MOV_reg_t1(opcode),
        18176...18296 => decode_BX_t1(opcode),
        18304...18424 => decode_BLX_t1(opcode),
        18432...20479 => decode_LDR_lit_t1(opcode),
        20480...20991 => decode_STR_reg_t1(opcode),
        20992...21503 => decode_STRH_reg_t1(opcode),
        21504...22015 => decode_STRB_reg_t1(opcode),
        22016...22527 => decode_LDRSB_reg_t1(opcode),
        22528...23039 => decode_LDR_reg_t1(opcode),
        23040...23551 => decode_LDRH_reg_t1(opcode),
        23552...24063 => decode_LDRB_reg_t1(opcode),
        24064...24575 => decode_LDRSH_reg_t1(opcode),
        24576...26623 => decode_STR_imm_t1(opcode),
        26624...28671 => decode_LDR_imm_t1(opcode),
        28672...30719 => decode_STRB_imm_t1(opcode),
        30720...32767 => decode_LDRB_imm_t1(opcode),
        32768...34815 => decode_STRH_imm_t1(opcode),
        34816...36863 => decode_LDRH_imm_t1(opcode),
        36864...38911 => decode_STR_imm_t2(opcode),
        38912...40959 => decode_LDR_imm_t2(opcode),
        40960...43007 => decode_ADR_t1(opcode),
        43008...45055 => decode_ADD_SP_imm_t1(opcode),
        45056...45183 => decode_ADD_SP_imm_t2(opcode),
        45184...45311 => decode_SUB_SP_imm_t1(opcode),
        45568...45631 => decode_SXTH_t1(opcode),
        45632...45695 => decode_SXTB_t1(opcode),
        45696...45759 => decode_UXTH_t1(opcode),
        45760...45823 => decode_UXTB_t1(opcode),
        46080...46591 => decode_PUSH_t1(opcode),
        46690...46706 => decode_CPS_t1(opcode),
        47616...47679 => decode_REV_t1(opcode),
        47680...47743 => decode_REV16_t1(opcode),
        47808...47871 => decode_REVSH_t1(opcode),
        48128...48639 => decode_POP_reg_t1(opcode),
        48640...48895 => decode_BKPT_t1(opcode),
        48896...48896 => decode_NOP_t1(opcode),
        48912...48912 => Instruction::YIELD,
        48928...48928 => Instruction::WFE,
        48944...48944 => Instruction::WFI,
        48960...48960 => Instruction::SEV,
        49152...51199 => decode_STM_t1(opcode),
        51200...53247 => decode_LDM_t1(opcode),
        53248...57343 => decode_B_t1_SVC_t1(opcode),
        57344...59391 => decode_B_t2(opcode),
        _ => decode_undefined(opcode),
    }
}

//A 5.3.1 Branch and misc (thumb32)
pub fn decode_branch_and_misc(t1: u16, t2: u16) -> Instruction {
    let op2 = t2.get_bits(12..15);
    let op1 = t1.get_bits(4..11);

    match op2 {
        0x7 | 0x5 => decode_bl(t1, t2),
        0 => match op1 {
            0b0111000 | 0b0111001 => decode_msr_reg(t1, t2),
            0b0111011 => decode_control(t1, t2),
            0b0111111 | 0b0111110 => decode_mrs(t1, t2),
            _ => Instruction::UDF {
                imm32: 0,
                opcode: ThumbCode::from(((t1 as u32) << 16) + t2 as u32),
            },
        },
        _ => Instruction::UDF {
            imm32: 0,
            opcode: ThumbCode::from(((t1 as u32) << 16) + t2 as u32),
        },
    }
}

{'fraction_non_alphanumeric': 0.16890947863813516, 'fraction_numerical': 0.13721597176262962, 'mean_word_length': 2.9650145772594754, 'pattern_counts': {'":': 0, '<': 11, '<?xml version=': 0, '>': 181, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7566295', 'n_tokens_mistral': 6366, 'n_tokens_neox': 5417, 'n_words': 894}