<commit_before>/* 10G controller driver for Samsung SoCs
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: <NAME> <<EMAIL>>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __SXGBE_REGMAP_H__
#define __SXGBE_REGMAP_H__

/* SXGBE MAC Registers */
#define SXGBE_CORE_TX_CONFIG_REG	0x0000
#define SXGBE_CORE_RX_CONFIG_REG	0x0004
#define SXGBE_CORE_PKT_FILTER_REG	0x0008
#define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
#define SXGBE_CORE_HASH_TABLE_REG0	0x0010
#define SXGBE_CORE_HASH_TABLE_REG1	0x0014
#define SXGBE_CORE_HASH_TABLE_REG2	0x0018
#define SXGBE_CORE_HASH_TABLE_REG3	0x001C
#define SXGBE_CORE_HASH_TABLE_REG4	0x0020
#define SXGBE_CORE_HASH_TABLE_REG5	0x0024
#define SXGBE_CORE_HASH_TABLE_REG6	0x0028
#define SXGBE_CORE_HASH_TABLE_REG7	0x002C

/* EEE-LPI Registers */
#define SXGBE_CORE_LPI_CTRL_STATUS	0x00D0
#define SXGBE_CORE_LPI_TIMER_CTRL	0x00D4

/* VLAN Specific Registers */
#define SXGBE_CORE_VLAN_TAG_REG		0x0050
#define SXGBE_CORE_VLAN_HASHTAB_REG	0x0058
#define SXGBE_CORE_VLAN_INSCTL_REG	0x0060
#define SXGBE_CORE_VLAN_INNERCTL_REG	0x0064
#define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C

/* Flow Contol Registers */
#define SXGBE_CORE_TX_Q0_FLOWCTL_REG	0x0070
#define SXGBE_CORE_TX_Q1_FLOWCTL_REG	0x0074
#define SXGBE_CORE_TX_Q2_FLOWCTL_REG	0x0078
#define SXGBE_CORE_TX_Q3_FLOWCTL_REG	0x007C
#define SXGBE_CORE_TX_Q4_FLOWCTL_REG	0x0080
#define SXGBE_CORE_TX_Q5_FLOWCTL_REG	0x0084
#define SXGBE_CORE_TX_Q6_FLOWCTL_REG	0x0088
#define SXGBE_CORE_TX_Q7_FLOWCTL_REG	0x008C
#define SXGBE_CORE_RX_FLOWCTL_REG	0x0090
#define SXGBE_CORE_RX_CTL0_REG		0x00A0
#define SXGBE_CORE_RX_CTL1_REG		0x00A4
#define SXGBE_CORE_RX_CTL2_REG		0x00A8
#define SXGBE_CORE_RX_CTL3_REG		0x00AC

#define SXGBE_CORE_RXQ_ENABLE_MASK	0x0003
#define SXGBE_CORE_RXQ_ENABLE		0x0002
#define SXGBE_CORE_RXQ_DISABLE		0x0000

/* Interrupt Registers */
#define SXGBE_CORE_INT_STATUS_REG	0x00B0
#define SXGBE_CORE_INT_ENABLE_REG	0x00B4
#define SXGBE_CORE_RXTX_ERR_STATUS_REG	0x00B8
#define SXGBE_CORE_PMT_CTL_STATUS_REG	0x00C0
#define SXGBE_CORE_RWK_PKT_FILTER_REG	0x00C4
#define SXGBE_CORE_VERSION_REG		0x0110
#define SXGBE_CORE_DEBUG_REG		0x0114
#define SXGBE_CORE_HW_FEA_REG(index)	(0x011C + index * 4)

/* SMA(MDIO) module registers */
#define SXGBE_MDIO_SCMD_ADD_REG		0x0200
#define SXGBE_MDIO_SCMD_DATA_REG	0x0204
#define SXGBE_MDIO_CCMD_WADD_REG	0x0208
#define SXGBE_MDIO_CCMD_WDATA_REG	0x020C
#define SXGBE_MDIO_CSCAN_PORT_REG	0x0210
#define SXGBE_MDIO_INT_STATUS_REG	0x0214
#define SXGBE_MDIO_INT_ENABLE_REG	0x0218
#define SXGBE_MDIO_PORT_CONDCON_REG	0x021C
#define SXGBE_MDIO_CLAUSE22_PORT_REG	0x0220

/* port specific, addr = 0-3 */
#define SXGBE_MDIO_DEV_BASE_REG		0x0230
#define SXGBE_MDIO_PORT_DEV_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0)
#define SXGBE_MDIO_PORT_LSTATUS_REG(addr)		\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4)
#define SXGBE_MDIO_PORT_ALIVE_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8)

#define SXGBE_CORE_GPIO_CTL_REG		0x0278
#define SXGBE_CORE_GPIO_STATUS_REG	0x027C

/* Address registers for filtering */
#define SXGBE_CORE_ADD_BASE_REG		0x0300

/* addr = 0-31 */
#define SXGBE_CORE_ADD_HIGHOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0)
#define SXGBE_CORE_ADD_LOWOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4)

/* SXGBE MMC registers */
#define SXGBE_MMC_CTL_REG		0x0800
#define SXGBE_MMC_RXINT_STATUS_REG	0x0804
#define SXGBE_MMC_TXINT_STATUS_REG	0x0808
#define SXGBE_MMC_RXINT_ENABLE_REG	0x080C
#define SXGBE_MMC_TXINT_ENABLE_REG	0x0810

/* TX specific counters */
#define SXGBE_MMC_TXOCTETHI_GBCNT_REG	0x0814
#define SXGBE_MMC_TXOCTETLO_GBCNT_REG	0x0818
#define SXGBE_MMC_TXFRAMELO_GBCNT_REG	0x081C
#define SXGBE_MMC_TXFRAMEHI_GBCNT_REG	0x0820
#define SXGBE_MMC_TXBROADLO_GCNT_REG	0x0824
#define SXGBE_MMC_TXBROADHI_GCNT_REG	0x0828
#define SXGBE_MMC_TXMULTILO_GCNT_REG	0x082C
#define SXGBE_MMC_TXMULTIHI_GCNT_REG	0x0830
#define SXGBE_MMC_TX64LO_GBCNT_REG	0x0834
#define SXGBE_MMC_TX64HI_GBCNT_REG	0x0838
#define SXGBE_MMC_TX65TO127LO_GBCNT_REG		0x083C
#define SXGBE_MMC_TX65TO127HI_GBCNT_REG		0x0840
#define SXGBE_MMC_TX128TO255LO_GBCNT_REG	0x0844
#define SXGBE_MMC_TX128TO255HI_GBCNT_REG	0x0848
#define SXGBE_MMC_TX256TO511LO_GBCNT_REG	0x084C
#define SXGBE_MMC_TX256TO511HI_GBCNT_REG	0x0850
#define SXGBE_MMC_TX512TO1023LO_GBCNT_REG	0x0854
#define SXGBE_MMC_TX512TO1023HI_GBCNT_REG	0x0858
#define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG	0x085C
#define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG	0x0860
#define SXGBE_MMC_TXUNICASTLO_GBCNT_REG		0x0864
#define SXGBE_MMC_TXUNICASTHI_GBCNT_REG		0x0868
#define SXGBE_MMC_TXMULTILO_GBCNT_REG		0x086C
#define SXGBE_MMC_TXMULTIHI_GBCNT_REG		0x0870
#define SXGBE_MMC_TXBROADLO_GBCNT_REG		0x0874
#define SXGBE_MMC_TXBROADHI_GBCNT_REG		0x0878
#define SXGBE_MMC_TXUFLWLO_GBCNT_REG		0x087C
#define SXGBE_MMC_TXUFLWHI_GBCNT_REG		0x0880
#define SXGBE_MMC_TXOCTETLO_GCNT_REG	0x0884
#define SXGBE_MMC_TXOCTETHI_GCNT_REG	0x0888
#define SXGBE_MMC_TXFRAMELO_GCNT_REG	0x088C
#define SXGBE_MMC_TXFRAMEHI_GCNT_REG	0x0890
#define SXGBE_MMC_TXPAUSELO_CNT_REG	0x0894
#define SXGBE_MMC_TXPAUSEHI_CNT_REG	0x0898
#define SXGBE_MMC_TXVLANLO_GCNT_REG	0x089C
#define SXGBE_MMC_TXVLANHI_GCNT_REG	0x08A0

/* RX specific counters */
#define SXGBE_MMC_RXFRAMELO_GBCNT_REG	0x0900
#define SXGBE_MMC_RXFRAMEHI_GBCNT_REG	0x0904
#define SXGBE_MMC_RXOCTETLO_GBCNT_REG	0x0908
#define SXGBE_MMC_RXOCTETHI_GBCNT_REG	0x090C
#define SXGBE_MMC_RXOCTETLO_GCNT_REG	0x0910
#define SXGBE_MMC_RXOCTETHI_GCNT_REG	0x0914
#define SXGBE_MMC_RXBROADLO_GCNT_REG	0x0918
#define SXGBE_MMC_RXBROADHI_GCNT_REG	0x091C
#define SXGBE_MMC_RXMULTILO_GCNT_REG	0x0920
#define SXGBE_MMC_RXMULTIHI_GCNT_REG	0x0924
#define SXGBE_MMC_RXCRCERRLO_REG	0x0928
#define SXGBE_MMC_RXCRCERRHI_REG	0x092C
#define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG	0x0930
#define SXGBE_MMC_RXJABBERERR_REG		0x0934
#define SXGBE_MMC_RXSHORT64BFRAME_COR_REG	0x0938
#define SXGBE_MMC_RXOVERMAXFRAME_COR_REG	0x093C
#define SXGBE_MMC_RX64LO_GBCNT_REG		0x0940
#define SXGBE_MMC_RX64HI_GBCNT_REG		0x0944
#define SXGBE_MMC_RX65TO127LO_GBCNT_REG		0x0948
#define SXGBE_MMC_RX65TO127HI_GBCNT_REG		0x094C
#define SXGBE_MMC_RX128TO255LO_GBCNT_REG	0x0950
#define SXGBE_MMC_RX128TO255HI_GBCNT_REG	0x0954
#define SXGBE_MMC_RX256TO511LO_GBCNT_REG	0x0958
#define SXGBE_MMC_RX256TO511HI_GBCNT_REG	0x095C
#define SXGBE_MMC_RX512TO1023LO_GBCNT_REG	0x0960
#define SXGBE_MMC_RX512TO1023HI_GBCNT_REG	0x0964
#define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG	0x0968
#define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG	0x096C
#define SXGBE_MMC_RXUNICASTLO_GCNT_REG		0x0970
#define SXGBE_MMC_RXUNICASTHI_GCNT_REG		0x0974
#define SXGBE_MMC_RXLENERRLO_REG		0x0978
#define SXGBE_MMC_RXLENERRHI_REG		0x097C
#define SXGBE_MMC_RXOUTOFRANGETYPELO_REG	0x0980
#define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG	0x0984
#define SXGBE_MMC_RXPAUSELO_CNT_REG		0x0988
#define SXGBE_MMC_RXPAUSEHI_CNT_REG		0x098C
#define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG	0x0990
#define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG	0x0994
#define SXGBE_MMC_RXVLANLO_GBCNT_REG		0x0998
#define SXGBE_MMC_RXVLANHI_GBCNT_REG		0x099C
#define SXGBE_MMC_RXWATCHDOG_ERR_REG		0x09A0

/* L3/L4 function registers */
#define SXGBE_CORE_L34_ADDCTL_REG	0x0C00
#define SXGBE_CORE_L34_ADDCTL_REG	0x0C00
#define SXGBE_CORE_L34_DATA_REG		0x0C04

/* ARP registers */
#define SXGBE_CORE_ARP_ADD_REG		0x0C10

/* RSS registers */
#define SXGBE_CORE_RSS_CTL_REG		0x0C80
#define SXGBE_CORE_RSS_ADD_REG		0x0C88
#define SXGBE_CORE_RSS_DATA_REG		0x0C8C

/* RSS control register bits */
#define SXGBE_CORE_RSS_CTL_UDP4TE	BIT(3)
#define SXGBE_CORE_RSS_CTL_TCP4TE	BIT(2)
#define SXGBE_CORE_RSS_CTL_IP2TE	BIT(1)
#define SXGBE_CORE_RSS_CTL_RSSE		BIT(0)

/* IEEE 1588 registers */
#define SXGBE_CORE_TSTAMP_CTL_REG	0x0D00
#define SXGBE_CORE_SUBSEC_INC_REG	0x0D04
#define SXGBE_CORE_SYSTIME_SEC_REG	0x0D0C
#define SXGBE_CORE_SYSTIME_NSEC_REG	0x0D10
#define SXGBE_CORE_SYSTIME_SECUP_REG	0x0D14
#define SXGBE_CORE_TSTAMP_ADD_REG	0x0D18
#define SXGBE_CORE_SYSTIME_HWORD_REG	0x0D1C<commit_msg>net: sxgbe: remove duplicate SXGBE_CORE_L34_ADDCTL_REG define<commit_after>/* 10G controller driver for Samsung SoCs
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: <NAME> <<EMAIL>>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __SXGBE_REGMAP_H__
#define __SXGBE_REGMAP_H__

/* SXGBE MAC Registers */
#define SXGBE_CORE_TX_CONFIG_REG	0x0000
#define SXGBE_CORE_RX_CONFIG_REG	0x0004
#define SXGBE_CORE_PKT_FILTER_REG	0x0008
#define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
#define SXGBE_CORE_HASH_TABLE_REG0	0x0010
#define SXGBE_CORE_HASH_TABLE_REG1	0x0014
#define SXGBE_CORE_HASH_TABLE_REG2	0x0018
#define SXGBE_CORE_HASH_TABLE_REG3	0x001C
#define SXGBE_CORE_HASH_TABLE_REG4	0x0020
#define SXGBE_CORE_HASH_TABLE_REG5	0x0024
#define SXGBE_CORE_HASH_TABLE_REG6	0x0028
#define SXGBE_CORE_HASH_TABLE_REG7	0x002C

/* EEE-LPI Registers */
#define SXGBE_CORE_LPI_CTRL_STATUS	0x00D0
#define SXGBE_CORE_LPI_TIMER_CTRL	0x00D4

/* VLAN Specific Registers */
#define SXGBE_CORE_VLAN_TAG_REG		0x0050
#define SXGBE_CORE_VLAN_HASHTAB_REG	0x0058
#define SXGBE_CORE_VLAN_INSCTL_REG	0x0060
#define SXGBE_CORE_VLAN_INNERCTL_REG	0x0064
#define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C

/* Flow Contol Registers */
#define SXGBE_CORE_TX_Q0_FLOWCTL_REG	0x0070
#define SXGBE_CORE_TX_Q1_FLOWCTL_REG	0x0074
#define SXGBE_CORE_TX_Q2_FLOWCTL_REG	0x0078
#define SXGBE_CORE_TX_Q3_FLOWCTL_REG	0x007C
#define SXGBE_CORE_TX_Q4_FLOWCTL_REG	0x0080
#define SXGBE_CORE_TX_Q5_FLOWCTL_REG	0x0084
#define SXGBE_CORE_TX_Q6_FLOWCTL_REG	0x0088
#define SXGBE_CORE_TX_Q7_FLOWCTL_REG	0x008C
#define SXGBE_CORE_RX_FLOWCTL_REG	0x0090
#define SXGBE_CORE_RX_CTL0_REG		0x00A0
#define SXGBE_CORE_RX_CTL1_REG		0x00A4
#define SXGBE_CORE_RX_CTL2_REG		0x00A8
#define SXGBE_CORE_RX_CTL3_REG		0x00AC

#define SXGBE_CORE_RXQ_ENABLE_MASK	0x0003
#define SXGBE_CORE_RXQ_ENABLE		0x0002
#define SXGBE_CORE_RXQ_DISABLE		0x0000

/* Interrupt Registers */
#define SXGBE_CORE_INT_STATUS_REG	0x00B0
#define SXGBE_CORE_INT_ENABLE_REG	0x00B4
#define SXGBE_CORE_RXTX_ERR_STATUS_REG	0x00B8
#define SXGBE_CORE_PMT_CTL_STATUS_REG	0x00C0
#define SXGBE_CORE_RWK_PKT_FILTER_REG	0x00C4
#define SXGBE_CORE_VERSION_REG		0x0110
#define SXGBE_CORE_DEBUG_REG		0x0114
#define SXGBE_CORE_HW_FEA_REG(index)	(0x011C + index * 4)

/* SMA(MDIO) module registers */
#define SXGBE_MDIO_SCMD_ADD_REG		0x0200
#define SXGBE_MDIO_SCMD_DATA_REG	0x0204
#define SXGBE_MDIO_CCMD_WADD_REG	0x0208
#define SXGBE_MDIO_CCMD_WDATA_REG	0x020C
#define SXGBE_MDIO_CSCAN_PORT_REG	0x0210
#define SXGBE_MDIO_INT_STATUS_REG	0x0214
#define SXGBE_MDIO_INT_ENABLE_REG	0x0218
#define SXGBE_MDIO_PORT_CONDCON_REG	0x021C
#define SXGBE_MDIO_CLAUSE22_PORT_REG	0x0220

/* port specific, addr = 0-3 */
#define SXGBE_MDIO_DEV_BASE_REG		0x0230
#define SXGBE_MDIO_PORT_DEV_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0)
#define SXGBE_MDIO_PORT_LSTATUS_REG(addr)		\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4)
#define SXGBE_MDIO_PORT_ALIVE_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8)

#define SXGBE_CORE_GPIO_CTL_REG		0x0278
#define SXGBE_CORE_GPIO_STATUS_REG	0x027C

/* Address registers for filtering */
#define SXGBE_CORE_ADD_BASE_REG		0x0300

/* addr = 0-31 */
#define SXGBE_CORE_ADD_HIGHOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0)
#define SXGBE_CORE_ADD_LOWOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4)

/* SXGBE MMC registers */
#define SXGBE_MMC_CTL_REG		0x0800
#define SXGBE_MMC_RXINT_STATUS_REG	0x0804
#define SXGBE_MMC_TXINT_STATUS_REG	0x0808
#define SXGBE_MMC_RXINT_ENABLE_REG	0x080C
#define SXGBE_MMC_TXINT_ENABLE_REG	0x0810

/* TX specific counters */
#define SXGBE_MMC_TXOCTETHI_GBCNT_REG	0x0814
#define SXGBE_MMC_TXOCTETLO_GBCNT_REG	0x0818
#define SXGBE_MMC_TXFRAMELO_GBCNT_REG	0x081C
#define SXGBE_MMC_TXFRAMEHI_GBCNT_REG	0x0820
#define SXGBE_MMC_TXBROADLO_GCNT_REG	0x0824
#define SXGBE_MMC_TXBROADHI_GCNT_REG	0x0828
#define SXGBE_MMC_TXMULTILO_GCNT_REG	0x082C
#define SXGBE_MMC_TXMULTIHI_GCNT_REG	0x0830
#define SXGBE_MMC_TX64LO_GBCNT_REG	0x0834
#define SXGBE_MMC_TX64HI_GBCNT_REG	0x0838
#define SXGBE_MMC_TX65TO127LO_GBCNT_REG		0x083C
#define SXGBE_MMC_TX65TO127HI_GBCNT_REG		0x0840
#define SXGBE_MMC_TX128TO255LO_GBCNT_REG	0x0844
#define SXGBE_MMC_TX128TO255HI_GBCNT_REG	0x0848
#define SXGBE_MMC_TX256TO511LO_GBCNT_REG	0x084C
#define SXGBE_MMC_TX256TO511HI_GBCNT_REG	0x0850
#define SXGBE_MMC_TX512TO1023LO_GBCNT_REG	0x0854
#define SXGBE_MMC_TX512TO1023HI_GBCNT_REG	0x0858
#define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG	0x085C
#define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG	0x0860
#define SXGBE_MMC_TXUNICASTLO_GBCNT_REG		0x0864
#define SXGBE_MMC_TXUNICASTHI_GBCNT_REG		0x0868
#define SXGBE_MMC_TXMULTILO_GBCNT_REG		0x086C
#define SXGBE_MMC_TXMULTIHI_GBCNT_REG		0x0870
#define SXGBE_MMC_TXBROADLO_GBCNT_REG		0x0874
#define SXGBE_MMC_TXBROADHI_GBCNT_REG		0x0878
#define SXGBE_MMC_TXUFLWLO_GBCNT_REG		0x087C
#define SXGBE_MMC_TXUFLWHI_GBCNT_REG		0x0880
#define SXGBE_MMC_TXOCTETLO_GCNT_REG	0x0884
#define SXGBE_MMC_TXOCTETHI_GCNT_REG	0x0888
#define SXGBE_MMC_TXFRAMELO_GCNT_REG	0x088C
#define SXGBE_MMC_TXFRAMEHI_GCNT_REG	0x0890
#define SXGBE_MMC_TXPAUSELO_CNT_REG	0x0894
#define SXGBE_MMC_TXPAUSEHI_CNT_REG	0x0898
#define SXGBE_MMC_TXVLANLO_GCNT_REG	0x089C
#define SXGBE_MMC_TXVLANHI_GCNT_REG	0x08A0

/* RX specific counters */
#define SXGBE_MMC_RXFRAMELO_GBCNT_REG	0x0900
#define SXGBE_MMC_RXFRAMEHI_GBCNT_REG	0x0904
#define SXGBE_MMC_RXOCTETLO_GBCNT_REG	0x0908
#define SXGBE_MMC_RXOCTETHI_GBCNT_REG	0x090C
#define SXGBE_MMC_RXOCTETLO_GCNT_REG	0x0910
#define SXGBE_MMC_RXOCTETHI_GCNT_REG	0x0914
#define SXGBE_MMC_RXBROADLO_GCNT_REG	0x0918
#define SXGBE_MMC_RXBROADHI_GCNT_REG	0x091C
#define SXGBE_MMC_RXMULTILO_GCNT_REG	0x0920
#define SXGBE_MMC_RXMULTIHI_GCNT_REG	0x0924
#define SXGBE_MMC_RXCRCERRLO_REG	0x0928
#define SXGBE_MMC_RXCRCERRHI_REG	0x092C
#define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG	0x0930
#define SXGBE_MMC_RXJABBERERR_REG		0x0934
#define SXGBE_MMC_RXSHORT64BFRAME_COR_REG	0x0938
#define SXGBE_MMC_RXOVERMAXFRAME_COR_REG	0x093C
#define SXGBE_MMC_RX64LO_GBCNT_REG		0x0940
#define SXGBE_MMC_RX64HI_GBCNT_REG		0x0944
#define SXGBE_MMC_RX65TO127LO_GBCNT_REG		0x0948
#define SXGBE_MMC_RX65TO127HI_GBCNT_REG		0x094C
#define SXGBE_MMC_RX128TO255LO_GBCNT_REG	0x0950
#define SXGBE_MMC_RX128TO255HI_GBCNT_REG	0x0954
#define SXGBE_MMC_RX256TO511LO_GBCNT_REG	0x0958
#define SXGBE_MMC_RX256TO511HI_GBCNT_REG	0x095C
#define SXGBE_MMC_RX512TO1023LO_GBCNT_REG	0x0960
#define SXGBE_MMC_RX512TO1023HI_GBCNT_REG	0x0964
#define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG	0x0968
#define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG	0x096C
#define SXGBE_MMC_RXUNICASTLO_GCNT_REG		0x0970
#define SXGBE_MMC_RXUNICASTHI_GCNT_REG		0x0974
#define SXGBE_MMC_RXLENERRLO_REG		0x0978
#define SXGBE_MMC_RXLENERRHI_REG		0x097C
#define SXGBE_MMC_RXOUTOFRANGETYPELO_REG	0x0980
#define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG	0x0984
#define SXGBE_MMC_RXPAUSELO_CNT_REG		0x0988
#define SXGBE_MMC_RXPAUSEHI_CNT_REG		0x098C
#define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG	0x0990
#define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG	0x0994
#define SXGBE_MMC_RXVLANLO_GBCNT_REG		0x0998
#define SXGBE_MMC_RXVLANHI_GBCNT_REG		0x099C
#define SXGBE_MMC_RXWATCHDOG_ERR_REG		0x09A0

/* L3/L4 function registers */
#define SXGBE_CORE_L34_ADDCTL_REG	0x0C00
#define SXGBE_CORE_L34_DATA_REG		0x0C04

/* ARP registers */
#define SXGBE_CORE_ARP_ADD_REG		0x0C10

/* RSS registers */
#define SXGBE_CORE_RSS_CTL_REG		0x0C80
#define SXGBE_CORE_RSS_ADD_REG		0x0C88
#define SXGBE_CORE_RSS_DATA_REG		0x0C8C

/* RSS control register bits */
#define SXGBE_CORE_RSS_CTL_UDP4TE	BIT(3)
#define SXGBE_CORE_RSS_CTL_TCP4TE	BIT(2)
#define SXGBE_CORE_RSS_CTL_IP2TE	BIT(1)
#define SXGBE_CORE_RSS_CTL_RSSE		BIT(0)

/* IEEE 1588 registers */
#define SXGBE_CORE_TSTAMP_CTL_REG	0x0D00
#define SXGBE_CORE_SUBSEC_INC_REG	0x0D04
#define SXGBE_CORE_SYSTIME_SEC_REG	0x0D0C
#define SXGBE_CORE_SYSTIME_NSEC_REG	0x0D10
#define SXGBE_CORE_SYSTIME_SECUP_REG	0x0D14
#define SXGBE_CORE_TSTAMP_ADD_REG	0x0D18
#define SXGBE_CORE_SYSTIME_HWORD_REG	0x0D1C
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