<commit_before>#!/usr/bin/env python3

from nexys_base import *

from litevideo.output.hdmi.s7 import S7HDMIOutClocking

from litevideo.output.hdmi.s7 import S7HDMIOutPHY

from litevideo.output.core import TimingGenerator


class VideoOutSoC(BaseSoC):
    def __init__(self, platform, *args, **kwargs):
        BaseSoC.__init__(self, platform, *args, **kwargs)

        pads = platform.request("hdmi_out")
        self.comb += pads.scl.eq(1)

        # # #

        self.submodules.vtg = ClockDomainsRenamer("pix")(TimingGenerator(1))
        self.comb += [
            self.vtg.timing.valid.eq(1),

            self.vtg.timing.hres.eq(1920),
            self.vtg.timing.hsync_start.eq(1920+88),
            self.vtg.timing.hsync_end.eq(1920+88+44),
            self.vtg.timing.hscan.eq(2200),

            self.vtg.timing.vres.eq(1080),
            self.vtg.timing.vsync_start.eq(1080+4),
            self.vtg.timing.vsync_end.eq(1080+4+5),
            self.vtg.timing.vscan.eq(1125),

            self.vtg.pixels.valid.eq(1)
        ]

        self.submodules.hdmi_clocking = S7HDMIOutClocking(self.crg.clk100, pads)<commit_msg>nexys_video: use 720p60 video pattern (1080p works but is out of spec)<commit_after>#!/usr/bin/env python3

from nexys_base import *

from litevideo.output.hdmi.s7 import S7HDMIOutClocking

from litevideo.output.hdmi.s7 import S7HDMIOutPHY

from litevideo.output.core import TimingGenerator


class VideoOutSoC(BaseSoC):
    def __init__(self, platform, *args, **kwargs):
        BaseSoC.__init__(self, platform, *args, **kwargs)

        pads = platform.request("hdmi_out")
        self.comb += pads.scl.eq(1)

        # # #

        self.submodules.vtg = ClockDomainsRenamer("pix")(TimingGenerator(1))
        self.comb += [
            self.vtg.timing.valid.eq(1),

            self.vtg.timing.hres.eq(1280),
            self.vtg.timing.hsync_start.eq(1390),
            self.vtg.timing.hsync_end.eq(1430),
            self.vtg.timing.hscan.eq(1650),

            self.vtg.timing.vres.eq(720),
            self.vtg.timing.vsync_start.eq(725),
            self.vtg.timing.vsync_end.eq(730),
            self.vtg.timing.vscan.eq(750),

            self.vtg.pixels.valid.eq(1)
        ]

        self.submodules.hdmi_clocking = S7HDMIOutClocking(self.crg.clk100, pads)
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{'dir': 'git-commits-cleaned', 'id': '2918181', 'n_tokens_mistral': 929, 'n_tokens_neox': 846, 'n_words': 106}