<commit_before>//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Subclass of MipsTargetLowering specialized for mips32/64.
//
//===----------------------------------------------------------------------===//
#include "MipsSEISelLowering.h"
#include "MipsRegisterInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetInstrInfo.h"

using namespace llvm;

static cl::opt<bool>
EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
                    cl::desc("MIPS: Enable tail calls."), cl::init(false));

static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
                                   cl::desc("Expand double precision loads and "
                                            "stores to their single precision "
                                            "counterparts"));

MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
  : MipsTargetLowering(TM) {
  // Set up the register classes

  clearRegisterClasses();

  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);

  if (HasMips64)
    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);

  if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
    // Expand all truncating stores and extending loads.
    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;

    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
        setTruncStoreAction((MVT::SimpleValueType)VT0,
                            (MVT::SimpleValueType)VT1, Expand);
<commit_msg>[mips] Delete unnecessary code.<commit_after>//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Subclass of MipsTargetLowering specialized for mips32/64.
//
//===----------------------------------------------------------------------===//
#include "MipsSEISelLowering.h"
#include "MipsRegisterInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetInstrInfo.h"

using namespace llvm;

static cl::opt<bool>
EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
                    cl::desc("MIPS: Enable tail calls."), cl::init(false));

static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
                                   cl::desc("Expand double precision loads and "
                                            "stores to their single precision "
                                            "counterparts"));

MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
  : MipsTargetLowering(TM) {
  // Set up the register classes
  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);

  if (HasMips64)
    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);

  if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
    // Expand all truncating stores and extending loads.
    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;

    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
        setTruncStoreAction((MVT::SimpleValueType)VT0,
                            (MVT::SimpleValueType)VT1, Expand);

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