<commit_before>#ifndef HALIDE_TARGET_H
#define HALIDE_TARGET_H

/** \file
 * Defines the structure that describes a Halide target.
 */

#include <stdint.h>
#include <string>
#include "Util.h"

namespace llvm {
class Module;
class LLVMContext;
}

namespace Halide {

/** A struct representing a target machine and os to generate code for. */
struct Target {
    /** The operating system used by the target. Determines which
     * system calls to generate. */
    enum OS {OSUnknown = 0, Linux, Windows, OSX, Android, IOS, NaCl} os;

    /** The architecture used by the target. Determines the
     * instruction set to use. For the PNaCl target, the "instruction
     * set" is actually llvm bitcode. */
    enum Arch {ArchUnknown = 0, X86, ARM, PNaCl} arch;

    /** The bit-width of the target machine. Must be 0 for unknown, or 32 or 64. */
    int bits;

    /** Optional features a target can have. */
    enum Features {JIT       = 1 << 0,  ///< Generate code that will run immediately inside the calling process.
                   SSE41     = 1 << 1,  ///< Use SSE 4.1 and earlier instructions. Only relevant on x86.
                   AVX       = 1 << 2,  ///< Use AVX 1 instructions. Only relevant on x86.
                   AVX2      = 1 << 3,  ///< Use AVX 2 instructions. Only relevant on x86.
                   CUDA      = 1 << 4,  ///< Enable the CUDA runtime.
                   OpenCL    = 1 << 5,  ///< Enable the OpenCL runtime.
                   OpenGL    = 1 << 6,  ///< Enable the OpenGL runtime.
                   GPUDebug  = 1 << 7,  ///< Increase the level of checking and the verbosity of the gpu runtimes.
                   NoAsserts = 1 << 8,  ///< Disable all runtime checks, for slightly tighter code.
                   NoBoundsQuery = 1 << 9, ///< Disable the bounds querying functionality.
                   ARMv7s    = 1 << 10,  ///< Generate code for ARMv7s. Only relevant for 32-bit ARM.
                   CLDoubles = 1 << 11, ///< Enable double support on OpenCL targets
                   FMA       = 1 << 12, /// Enable x86 FMA instruction
                   FMA4      = 1 << 13, /// Enable x86 (AMD) FMA4 instruction set
                   F16C      = 1 << 14  /// Enable x86 16-bit float support
    };

    /** A bitmask that stores the active features. */
    uint64_t features;

    Target() : os(OSUnknown), arch(ArchUnknown), bits(0), features(0) {}
    Target(OS o, Arch a, int b, uint64_t f) : os(o), arch(a), bits(b), features(f) {}

    bool has_gpu_feature() const {
        return (features & (CUDA|OpenCL));
    }

    bool operator==(const Target &other) const {
      return os == other.os &&
          arch == other.arch &&
          bits == other.bits &&
          features == other.features;
    }

    bool operator!=(const Target &other) const {<commit_msg>Target::has_gpu_feature() should return true for OpenGL<commit_after>#ifndef HALIDE_TARGET_H
#define HALIDE_TARGET_H

/** \file
 * Defines the structure that describes a Halide target.
 */

#include <stdint.h>
#include <string>
#include "Util.h"

namespace llvm {
class Module;
class LLVMContext;
}

namespace Halide {

/** A struct representing a target machine and os to generate code for. */
struct Target {
    /** The operating system used by the target. Determines which
     * system calls to generate. */
    enum OS {OSUnknown = 0, Linux, Windows, OSX, Android, IOS, NaCl} os;

    /** The architecture used by the target. Determines the
     * instruction set to use. For the PNaCl target, the "instruction
     * set" is actually llvm bitcode. */
    enum Arch {ArchUnknown = 0, X86, ARM, PNaCl} arch;

    /** The bit-width of the target machine. Must be 0 for unknown, or 32 or 64. */
    int bits;

    /** Optional features a target can have. */
    enum Features {JIT       = 1 << 0,  ///< Generate code that will run immediately inside the calling process.
                   SSE41     = 1 << 1,  ///< Use SSE 4.1 and earlier instructions. Only relevant on x86.
                   AVX       = 1 << 2,  ///< Use AVX 1 instructions. Only relevant on x86.
                   AVX2      = 1 << 3,  ///< Use AVX 2 instructions. Only relevant on x86.
                   CUDA      = 1 << 4,  ///< Enable the CUDA runtime.
                   OpenCL    = 1 << 5,  ///< Enable the OpenCL runtime.
                   OpenGL    = 1 << 6,  ///< Enable the OpenGL runtime.
                   GPUDebug  = 1 << 7,  ///< Increase the level of checking and the verbosity of the gpu runtimes.
                   NoAsserts = 1 << 8,  ///< Disable all runtime checks, for slightly tighter code.
                   NoBoundsQuery = 1 << 9, ///< Disable the bounds querying functionality.
                   ARMv7s    = 1 << 10,  ///< Generate code for ARMv7s. Only relevant for 32-bit ARM.
                   CLDoubles = 1 << 11, ///< Enable double support on OpenCL targets
                   FMA       = 1 << 12, /// Enable x86 FMA instruction
                   FMA4      = 1 << 13, /// Enable x86 (AMD) FMA4 instruction set
                   F16C      = 1 << 14  /// Enable x86 16-bit float support
    };

    /** A bitmask that stores the active features. */
    uint64_t features;

    Target() : os(OSUnknown), arch(ArchUnknown), bits(0), features(0) {}
    Target(OS o, Arch a, int b, uint64_t f) : os(o), arch(a), bits(b), features(f) {}

    bool has_gpu_feature() const {
        return (features & (CUDA|OpenCL|OpenGL)) != 0;
    }

    bool operator==(const Target &other) const {
      return os == other.os &&
          arch == other.arch &&
          bits == other.bits &&
          features == other.features;
    }

    bool operator!=(const Target &other) const {
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