<commit_before>/* Copyright 2013-2016 IBM Corp.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * 	http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
 * implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __PHB4_REGS_H
#define __PHB4_REGS_H

/*
 * PHB registers
 */

/* PHB Fundamental register set A */
/* phb4_spec_036.pdf, page 80, "5.4.1 ETU/RSB HV Register Address Map" */
/* FIXME: check these (phb3 currently below) */
#define PHB_LSI_SOURCE_ID		0x100
#define   PHB_LSI_SRC_ID		PPC_BITMASK(4,12)
#define PHB_DMA_CHAN_STATUS		0x110
#define   PHB_DMA_CHAN_ANY_ERR		PPC_BIT(27)
#define   PHB_DMA_CHAN_ANY_ERR1		PPC_BIT(28)
#define   PHB_DMA_CHAN_ANY_FREEZE	PPC_BIT(29)
#define PHB_CPU_LOADSTORE_STATUS	0x120
#define   PHB_CPU_LS_ANY_ERR		PPC_BIT(27)
#define   PHB_CPU_LS_ANY_ERR1		PPC_BIT(28)
#define   PHB_CPU_LS_ANY_FREEZE		PPC_BIT(29)
#define PHB_DMA_MSI_NODE_ID		0x128
#define   PHB_DMAMSI_NID_FIXED		PPC_BIT(0)
#define   PHB_DMAMSI_NID		PPC_BITMASK(24,31)
#define PHB_CONFIG_DATA			0x130
#define PHB_LOCK0			0x138
#define PHB_CONFIG_ADDRESS		0x140
#define   PHB_CA_ENABLE			PPC_BIT(0)
#define	  PHB_CA_STATUS			PPC_BITMASK(1,3)
#define	  PHB_CA_BUS			PPC_BITMASK(4,11)
#define   PHB_CA_DEV			PPC_BITMASK(12,16)
#define   PHB_CA_FUNC			PPC_BITMASK(17,19)
#define   PHB_CA_BDFN			PPC_BITMASK(4,19) /* bus,dev,func */
#define   PHB_CA_REG			PPC_BITMASK(20,31)
#define   PHB_CA_PE			PPC_BITMASK(39,47)
#define PHB_LOCK1			0x148
#define PHB_IVT_BAR			0x150
#define   PHB_IVT_BAR_ENABLE		PPC_BIT(0)
#define   PHB_IVT_BASE_ADDRESS		PPC_BITMASK(14,48)
#define   PHB_IVT_LENGTH		PPC_BITMASK(52,63)
#define PHB_RBA_BAR			0x158
#define   PHB_RBA_BAR_ENABLE		PPC_BIT(0)
#define   PHB_RBA_BASE_ADDRESS		PPC_BITMASK(14,55)
#define PHB_PHB4_CONFIG			0x160
#define   PHB_PHB4C_32BIT_MSI_EN	PPC_BIT(8)
#define   PHB_PHB4C_64BIT_MSI_EN	PPC_BIT(14)
#define PHB_RTT_BAR			0x168
#define   PHB_RTT_BAR_ENABLE		PPC_BIT(0)
#define   PHB_RTT_BASE_ADDRESS		PPC_BITMASK(8,46)
#define PHB_PELTV_BAR			0x188
#define   PHB_PELTV_BAR_ENABLE		PPC_BIT(0)
#define   PHB_PELTV_BASE_ADDRESS	PPC_BITMASK(8,50)
#define PHB_M32_BASE_ADDR		0x190
#define PHB_M32_BASE_MASK		0x198
#define PHB_M32_START_ADDR		0x1a0
#define PHB_PEST_BAR			0x1a8
#define   PHB_PEST_BAR_ENABLE		PPC_BIT(0)
#define   PHB_PEST_BASE_ADDRESS		PPC_BITMASK(8,51)
#define PHB_PBL_ASN_CMPM		0x1C0
#define   PHB_PBL_ASN_ENABLE		PPC_BIT(63)
#define PHB_CAPI_CMPM			0x1C8
#define   PHB_CAPI_CMPM_ENABLE		PPC_BIT(63)
#define PHB_M64_UPPER_BITS		0x1f0
#define PHB_NXLATE_PREFIX		0x1f8
#define PHB_DMARD_SYNC			0x200
#define   PHB_DMARD_SYNC_START		PPC_BIT(0)
#define   PHB_DMARD_SYNC_COMPLETE	PPC_BIT(1)
#define PHB_RTC_INVALIDATE		0x208
#define   PHB_RTC_INVALIDATE_ALL	PPC_BIT(0)
#define   PHB_RTC_INVALIDATE_RID	PPC_BITMASK(16,31)
#define PHB_TCE_KILL			0x210
#define   PHB_TCE_KILL_ALL		PPC_BIT(0)
#define   PHB_TCE_KILL_PE		PPC_BIT(1)
#define   PHB_TCE_KILL_ONE		PPC_BIT(2)
#define	  PHB_TCE_KILL_PSEL		PPC_BIT(3)
#define	  PHB_TCE_KILL_64K		0x1000 /* Address override */
#define	  PHB_TCE_KILL_2M		0x2000 /* Address override */
#define	  PHB_TCE_KILL_1G		0x3000 /* Address override */
#define	  PHB_TCE_KILL_PENUM		PPC_BITMASK(55,63)
#define PHB_TCE_SPEC_CTL		0x218
#define PHB_IODA_ADDR			0x220
#define   PHB_IODA_AD_AUTOINC		PPC_BIT(0)
#define	  PHB_IODA_AD_TSEL		PPC_BITMASK(11,15)
#define	  PHB_IODA_AD_MIST_PWV		PPC_BITMASK(28,31)
#define	  PHB_IODA_AD_TADR		PPC_BITMASK(55,63)
#define PHB_IODA_DATA0			0x228
#define PHB_FFI_REQUEST			0x238
#define   PHB_FFI_LOCK_CLEAR		PPC_BIT(3)
#define   PHB_FFI_REQUEST_ISN		PPC_BITMASK(49,59)
#define PHB_FFI_LOCK			0x240
#define PHB_XIVE_UPDATE			0x248 /* Broken in DD1 */
#define PHB_PHB4_GEN_CAP		0x250
#define PHB_PHB4_TCE_CAP		0x258
#define PHB_PHB4_IRQ_CAP		0x260
#define PHB_PHB4_EEH_CAP		0x268
#define PHB_PAPR_ERR_INJ_CTL		0x2b0
#define   PHB_PAPR_ERR_INJ_CTL_INB	PPC_BIT(0)
#define   PHB_PAPR_ERR_INJ_CTL_OUTB	PPC_BIT(1)
#define   PHB_PAPR_ERR_INJ_CTL_STICKY	PPC_BIT(2)
#define   PHB_PAPR_ERR_INJ_CTL_CFG	PPC_BIT(3)
#define   PHB_PAPR_ERR_INJ_CTL_RD	PPC_BIT(4)
#define   PHB_PAPR_ERR_INJ_CTL_WR	PPC_BIT(5)
#define   PHB_PAPR_ERR_INJ_CTL_FREEZE	PPC_BIT(6)
#define PHB_PAPR_ERR_INJ_ADDR		0x2b8
#define   PHB_PAPR_ERR_INJ_ADDR_MMIO		PPC_BITMASK(16,63)
#define PHB_PAPR_ERR_INJ_MASK		0x2c0
#define   PHB_PAPR_ERR_INJ_MASK_CFG		PPC_BITMASK(4,11)
#define   PHB_PAPR_ERR_INJ_MASK_CFG_ALL		PPC_BITMASK(4,19)
#define   PHB_PAPR_ERR_INJ_MASK_MMIO		PPC_BITMASK(16,63)
#define PHB_ETU_ERR_SUMMARY		0x2c8
#define PHB_INT_NOTIFY_ADDR		0x300
#define PHB_INT_NOTIFY_INDEX		0x308<commit_msg>phb4: Fix number of index bits in IODA tables<commit_after>/* Copyright 2013-2016 IBM Corp.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * 	http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
 * implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __PHB4_REGS_H
#define __PHB4_REGS_H

/*
 * PHB registers
 */

/* PHB Fundamental register set A */
/* phb4_spec_036.pdf, page 80, "5.4.1 ETU/RSB HV Register Address Map" */
/* FIXME: check these (phb3 currently below) */
#define PHB_LSI_SOURCE_ID		0x100
#define   PHB_LSI_SRC_ID		PPC_BITMASK(4,12)
#define PHB_DMA_CHAN_STATUS		0x110
#define   PHB_DMA_CHAN_ANY_ERR		PPC_BIT(27)
#define   PHB_DMA_CHAN_ANY_ERR1		PPC_BIT(28)
#define   PHB_DMA_CHAN_ANY_FREEZE	PPC_BIT(29)
#define PHB_CPU_LOADSTORE_STATUS	0x120
#define   PHB_CPU_LS_ANY_ERR		PPC_BIT(27)
#define   PHB_CPU_LS_ANY_ERR1		PPC_BIT(28)
#define   PHB_CPU_LS_ANY_FREEZE		PPC_BIT(29)
#define PHB_DMA_MSI_NODE_ID		0x128
#define   PHB_DMAMSI_NID_FIXED		PPC_BIT(0)
#define   PHB_DMAMSI_NID		PPC_BITMASK(24,31)
#define PHB_CONFIG_DATA			0x130
#define PHB_LOCK0			0x138
#define PHB_CONFIG_ADDRESS		0x140
#define   PHB_CA_ENABLE			PPC_BIT(0)
#define	  PHB_CA_STATUS			PPC_BITMASK(1,3)
#define	  PHB_CA_BUS			PPC_BITMASK(4,11)
#define   PHB_CA_DEV			PPC_BITMASK(12,16)
#define   PHB_CA_FUNC			PPC_BITMASK(17,19)
#define   PHB_CA_BDFN			PPC_BITMASK(4,19) /* bus,dev,func */
#define   PHB_CA_REG			PPC_BITMASK(20,31)
#define   PHB_CA_PE			PPC_BITMASK(39,47)
#define PHB_LOCK1			0x148
#define PHB_IVT_BAR			0x150
#define   PHB_IVT_BAR_ENABLE		PPC_BIT(0)
#define   PHB_IVT_BASE_ADDRESS		PPC_BITMASK(14,48)
#define   PHB_IVT_LENGTH		PPC_BITMASK(52,63)
#define PHB_RBA_BAR			0x158
#define   PHB_RBA_BAR_ENABLE		PPC_BIT(0)
#define   PHB_RBA_BASE_ADDRESS		PPC_BITMASK(14,55)
#define PHB_PHB4_CONFIG			0x160
#define   PHB_PHB4C_32BIT_MSI_EN	PPC_BIT(8)
#define   PHB_PHB4C_64BIT_MSI_EN	PPC_BIT(14)
#define PHB_RTT_BAR			0x168
#define   PHB_RTT_BAR_ENABLE		PPC_BIT(0)
#define   PHB_RTT_BASE_ADDRESS		PPC_BITMASK(8,46)
#define PHB_PELTV_BAR			0x188
#define   PHB_PELTV_BAR_ENABLE		PPC_BIT(0)
#define   PHB_PELTV_BASE_ADDRESS	PPC_BITMASK(8,50)
#define PHB_M32_BASE_ADDR		0x190
#define PHB_M32_BASE_MASK		0x198
#define PHB_M32_START_ADDR		0x1a0
#define PHB_PEST_BAR			0x1a8
#define   PHB_PEST_BAR_ENABLE		PPC_BIT(0)
#define   PHB_PEST_BASE_ADDRESS		PPC_BITMASK(8,51)
#define PHB_PBL_ASN_CMPM		0x1C0
#define   PHB_PBL_ASN_ENABLE		PPC_BIT(63)
#define PHB_CAPI_CMPM			0x1C8
#define   PHB_CAPI_CMPM_ENABLE		PPC_BIT(63)
#define PHB_M64_UPPER_BITS		0x1f0
#define PHB_NXLATE_PREFIX		0x1f8
#define PHB_DMARD_SYNC			0x200
#define   PHB_DMARD_SYNC_START		PPC_BIT(0)
#define   PHB_DMARD_SYNC_COMPLETE	PPC_BIT(1)
#define PHB_RTC_INVALIDATE		0x208
#define   PHB_RTC_INVALIDATE_ALL	PPC_BIT(0)
#define   PHB_RTC_INVALIDATE_RID	PPC_BITMASK(16,31)
#define PHB_TCE_KILL			0x210
#define   PHB_TCE_KILL_ALL		PPC_BIT(0)
#define   PHB_TCE_KILL_PE		PPC_BIT(1)
#define   PHB_TCE_KILL_ONE		PPC_BIT(2)
#define	  PHB_TCE_KILL_PSEL		PPC_BIT(3)
#define	  PHB_TCE_KILL_64K		0x1000 /* Address override */
#define	  PHB_TCE_KILL_2M		0x2000 /* Address override */
#define	  PHB_TCE_KILL_1G		0x3000 /* Address override */
#define	  PHB_TCE_KILL_PENUM		PPC_BITMASK(55,63)
#define PHB_TCE_SPEC_CTL		0x218
#define PHB_IODA_ADDR			0x220
#define   PHB_IODA_AD_AUTOINC		PPC_BIT(0)
#define	  PHB_IODA_AD_TSEL		PPC_BITMASK(11,15)
#define	  PHB_IODA_AD_MIST_PWV		PPC_BITMASK(28,31)
#define	  PHB_IODA_AD_TADR		PPC_BITMASK(54,63)
#define PHB_IODA_DATA0			0x228
#define PHB_FFI_REQUEST			0x238
#define   PHB_FFI_LOCK_CLEAR		PPC_BIT(3)
#define   PHB_FFI_REQUEST_ISN		PPC_BITMASK(49,59)
#define PHB_FFI_LOCK			0x240
#define PHB_XIVE_UPDATE			0x248 /* Broken in DD1 */
#define PHB_PHB4_GEN_CAP		0x250
#define PHB_PHB4_TCE_CAP		0x258
#define PHB_PHB4_IRQ_CAP		0x260
#define PHB_PHB4_EEH_CAP		0x268
#define PHB_PAPR_ERR_INJ_CTL		0x2b0
#define   PHB_PAPR_ERR_INJ_CTL_INB	PPC_BIT(0)
#define   PHB_PAPR_ERR_INJ_CTL_OUTB	PPC_BIT(1)
#define   PHB_PAPR_ERR_INJ_CTL_STICKY	PPC_BIT(2)
#define   PHB_PAPR_ERR_INJ_CTL_CFG	PPC_BIT(3)
#define   PHB_PAPR_ERR_INJ_CTL_RD	PPC_BIT(4)
#define   PHB_PAPR_ERR_INJ_CTL_WR	PPC_BIT(5)
#define   PHB_PAPR_ERR_INJ_CTL_FREEZE	PPC_BIT(6)
#define PHB_PAPR_ERR_INJ_ADDR		0x2b8
#define   PHB_PAPR_ERR_INJ_ADDR_MMIO		PPC_BITMASK(16,63)
#define PHB_PAPR_ERR_INJ_MASK		0x2c0
#define   PHB_PAPR_ERR_INJ_MASK_CFG		PPC_BITMASK(4,11)
#define   PHB_PAPR_ERR_INJ_MASK_CFG_ALL		PPC_BITMASK(4,19)
#define   PHB_PAPR_ERR_INJ_MASK_MMIO		PPC_BITMASK(16,63)
#define PHB_ETU_ERR_SUMMARY		0x2c8
#define PHB_INT_NOTIFY_ADDR		0x300
#define PHB_INT_NOTIFY_INDEX		0x308
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{'dir': 'git-commits-cleaned', 'id': '6675727', 'n_tokens_mistral': 5320, 'n_tokens_neox': 4975, 'n_words': 851}