<commit_before>#ifndef NPY_SIMD
    #error "Not a standalone header"
#endif

#ifndef _NPY_SIMD_SSE_MISC_H
#define _NPY_SIMD_SSE_MISC_H

// vector with zero lanes
#define npyv_zero_u8  _mm_setzero_si128
#define npyv_zero_s8  _mm_setzero_si128
#define npyv_zero_u16 _mm_setzero_si128
#define npyv_zero_s16 _mm_setzero_si128
#define npyv_zero_u32 _mm_setzero_si128
#define npyv_zero_s32 _mm_setzero_si128
#define npyv_zero_u64 _mm_setzero_si128
#define npyv_zero_s64 _mm_setzero_si128
#define npyv_zero_f32 _mm_setzero_ps
#define npyv_zero_f64 _mm_setzero_pd

// vector with a specific value set to all lanes
#define npyv_setall_u8(VAL)  _mm_set1_epi8((char)VAL)
#define npyv_setall_s8(VAL)  _mm_set1_epi8((char)VAL)
#define npyv_setall_u16(VAL) _mm_set1_epi16((short)VAL)
#define npyv_setall_s16(VAL) _mm_set1_epi16((short)VAL)
#define npyv_setall_u32(VAL) _mm_set1_epi32((int)VAL)
#define npyv_setall_s32(VAL) _mm_set1_epi32(VAL)
#if !defined(__x86_64__) && !defined(_M_X64)
    #define npyv_setall_u64(VAL) _mm_set_epi32((int)(VAL >> 32), (int)VAL, (int)(VAL >> 32), (int)VAL)
    #define npyv_setall_s64 npyv_setall_u64
#else
    #define npyv_setall_u64(VAL) _mm_set1_epi64x(VAL)
    #define npyv_setall_s64(VAL) _mm_set1_epi64x(VAL)
#endif
#define npyv_setall_f32(VAL) _mm_set1_ps(VAL)
#define npyv_setall_f64(VAL) _mm_set1_pd(VAL)

/**
 * vector with specific values set to each lane and
 * set a specific value to all remained lanes
 *
 * Args that generated by NPYV__SET_FILL_* not going to expand if
 * _mm_setr_* are defined as macros.
 */
NPY_FINLINE __m128i npyv__setr_epi8(
    char i0, char i1, char i2,  char i3,  char i4,  char i5,  char i6,  char i7,<commit_msg>SIMD, BUG: fix passing immediate values to npyv_setall_u64 on SSE/32-bit<commit_after>#ifndef NPY_SIMD
    #error "Not a standalone header"
#endif

#ifndef _NPY_SIMD_SSE_MISC_H
#define _NPY_SIMD_SSE_MISC_H

// vector with zero lanes
#define npyv_zero_u8  _mm_setzero_si128
#define npyv_zero_s8  _mm_setzero_si128
#define npyv_zero_u16 _mm_setzero_si128
#define npyv_zero_s16 _mm_setzero_si128
#define npyv_zero_u32 _mm_setzero_si128
#define npyv_zero_s32 _mm_setzero_si128
#define npyv_zero_u64 _mm_setzero_si128
#define npyv_zero_s64 _mm_setzero_si128
#define npyv_zero_f32 _mm_setzero_ps
#define npyv_zero_f64 _mm_setzero_pd

// vector with a specific value set to all lanes
#define npyv_setall_u8(VAL)  _mm_set1_epi8((char)(VAL))
#define npyv_setall_s8(VAL)  _mm_set1_epi8((char)(VAL))
#define npyv_setall_u16(VAL) _mm_set1_epi16((short)(VAL))
#define npyv_setall_s16(VAL) _mm_set1_epi16((short)(VAL))
#define npyv_setall_u32(VAL) _mm_set1_epi32((int)(VAL))
#define npyv_setall_s32(VAL) _mm_set1_epi32((int)(VAL))
#define npyv_setall_u64(VAL) _mm_set1_epi64x((npy_int64)(VAL))
#define npyv_setall_s64(VAL) _mm_set1_epi64x((npy_int64)(VAL))
#define npyv_setall_f32 _mm_set1_ps
#define npyv_setall_f64 _mm_set1_pd

/**
 * vector with specific values set to each lane and
 * set a specific value to all remained lanes
 *
 * Args that generated by NPYV__SET_FILL_* not going to expand if
 * _mm_setr_* are defined as macros.
 */
NPY_FINLINE __m128i npyv__setr_epi8(
    char i0, char i1, char i2,  char i3,  char i4,  char i5,  char i6,  char i7,
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