<commit_before>#!/usr/bin/env python
# Copyright (c) 2015 <NAME> (<<EMAIL>>)
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.

from myhdl import Signal
from myhdl import modbv
from myhdl import enum
from myhdl import concat
from myhdl import always
from myhdl import always_comb
from myhdl import instances


class WishboneIntercon:
    """
    Defines an Wishbone IO interface.

    :ivar clk.    System clock
    :ivar rst:    System reset
    :ivar addr:   Address
    :ivar data_o: Data output
    :ivar data_i: Data input
    :ivar sel:    Select byte to write
    :ivar cti:    Cycle Type Identifier
    :ivar cyc:    Valid bus cycle in progress
    :ivar we:     Write enable
    :ivar stb:    Valid data transfer cycle
    :ivar stall:  Pipeline stall: Slave is not able to accept the transfer in the transaction queue
    :ivar ack:    Normal termination of a bus cycle
    :ivar err:    Abnormal cycle termination
    """
    def __init__(self):
        """
        Initializes the IO ports.
        """
        self.clk   = Signal(False)
        self.rst   = Signal(False)
        self.addr  = Signal(modbv(0)[32:])
        self.dat_o = Signal(modbv(0)[32:])
        self.dat_i = Signal(modbv(0)[32:])
        self.sel   = Signal(modbv(0)[4:])
        self.cti   = Signal(modbv(0)[3:])
        self.cyc   = Signal(False)
        self.we    = Signal(False)
        self.stb   = Signal(False)
        self.stall = Signal(False)
        self.ack   = Signal(False)
        self.err   = Signal(False)


class WishboneMaster:
    """
    Defines the wishbone master signals.

    :param intercon: the intercon bus.
    """
    def __init__(self, intercon):
        """
        Initializes the IO ports.
        """
        if not isinstance(intercon, WishboneIntercon):
            raise AttributeError("Unknown intercon type for {0}".format(str(intercon)))

        self.clk_i   = intercon.clk
        self.rst_i   = intercon.rst
        self.addr_o  = intercon.addr
        self.dat_o   = intercon.dat_o
        self.dat_i   = intercon.dat_i
        self.sel_o   = intercon.sel
        self.cti_o   = intercon.cti
        self.cyc_o   = intercon.cyc
        self.we_o    = intercon.we
        self.stb_o   = intercon.stb
        self.stall_i = intercon.stall
        self.ack_i   = intercon.ack
        self.err_i   = intercon.err


class WishboneSlave:
    """
    Defines the wishbone slave signals

    :param intercon: the intercon bus.
    """
    def __init__(self, intercon):
        """
        Initializes the IO ports.
        """
        if not isinstance(intercon, WishboneIntercon):
            raise AttributeError("Unknown intercon type for {0}".format(str(intercon)))

        self.clk_i   = intercon.clk
        self.rst_i   = intercon.rst
        self.addr_i  = intercon.addr
        self.dat_o   = intercon.dat_i
        self.dat_i   = intercon.dat_o
        self.sel_i   = intercon.sel
        self.cti_i   = intercon.cti
        self.cyc_i   = intercon.cyc
        self.we_i    = intercon.we
        self.stb_i   = intercon.stb
        self.stall_o = intercon.stall
        self.ack_o   = intercon.ack
        self.err_o   = intercon.err


class WishboneMasterGenerator():
    def __init__(self, master_signals, flagread, flagwrite, flagrmw):
        if isinstance(master_signals, WishboneMaster):
            self.wbmsig = master_signals
        else:
            raise AttributeError("Argument slave_signals must be of type WishboneSlave. Argument: {0}".format(str(master_signals)))

        self.flagread  = flagread
        self.flagwrite = flagwrite
        self.flagrmw   = flagrmw

    def gen_wbm(self):
        """
        State machine for master.
        Generates the state signals for the master.
        """
        self.wbm_states_t = enum('WBM_IDLE',
                                 'WBM_INCYCLE',
                                 'WBM_READ_WAIT',
                                 'WBM_WRITE_WAIT',
                                 'WBM_RMW_RD_WAIT',
                                 'WBM_RMW_MID_WAIT',
                                 'WBM_RMW_WR_WAIT')
        self.wbm_state = Signal(self.wbm_states_t.WBM_IDLE)

        self.list_trig_signals = []
        for i in zip(('trig_rd', 'trig_wr', 'trig_rmw'), self.wbm_states_t._names[2:5], (self.flagread, self.flagwrite, self.flagrmw)):
            self.list_trig_signals.append({"name": i[0], "initstate": getattr(self.wbm_states_t, i[1]), "trig": i[2]})

        trig_vector = Signal(modbv(0)[len(self.list_trig_signals):])
        trig_list   = (x['trig'] for x in self.list_trig_signals)
        ack_vector     = Signal(modbv(0)[2:])

        @always_comb
        def concat_trig_vector():
            trig_vector.next = concat(*trig_list)

        @always_comb<commit_msg>Explicit use of signals.<commit_after>#!/usr/bin/env python
# Copyright (c) 2015 <NAME> (<<EMAIL>>)
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
# THE SOFTWARE.

from myhdl import Signal
from myhdl import modbv
from myhdl import enum
from myhdl import concat
from myhdl import always
from myhdl import always_comb
from myhdl import instances


class WishboneIntercon:
    """
    Defines an Wishbone IO interface.

    :ivar clk.    System clock
    :ivar rst:    System reset
    :ivar addr:   Address
    :ivar data_o: Data output
    :ivar data_i: Data input
    :ivar sel:    Select byte to write
    :ivar cti:    Cycle Type Identifier
    :ivar cyc:    Valid bus cycle in progress
    :ivar we:     Write enable
    :ivar stb:    Valid data transfer cycle
    :ivar stall:  Pipeline stall: Slave is not able to accept the transfer in the transaction queue
    :ivar ack:    Normal termination of a bus cycle
    :ivar err:    Abnormal cycle termination
    """
    def __init__(self):
        """
        Initializes the IO ports.
        """
        self.clk   = Signal(False)
        self.rst   = Signal(False)
        self.addr  = Signal(modbv(0)[32:])
        self.dat_o = Signal(modbv(0)[32:])
        self.dat_i = Signal(modbv(0)[32:])
        self.sel   = Signal(modbv(0)[4:])
        self.cti   = Signal(modbv(0)[3:])
        self.cyc   = Signal(False)
        self.we    = Signal(False)
        self.stb   = Signal(False)
        self.stall = Signal(False)
        self.ack   = Signal(False)
        self.err   = Signal(False)


class WishboneMaster:
    """
    Defines the wishbone master signals.

    :param intercon: the intercon bus.
    """
    def __init__(self, intercon):
        """
        Initializes the IO ports.
        """
        if not isinstance(intercon, WishboneIntercon):
            raise AttributeError("Unknown intercon type for {0}".format(str(intercon)))

        self.clk_i   = intercon.clk
        self.rst_i   = intercon.rst
        self.addr_o  = intercon.addr
        self.dat_o   = intercon.dat_o
        self.dat_i   = intercon.dat_i
        self.sel_o   = intercon.sel
        self.cti_o   = intercon.cti
        self.cyc_o   = intercon.cyc
        self.we_o    = intercon.we
        self.stb_o   = intercon.stb
        self.stall_i = intercon.stall
        self.ack_i   = intercon.ack
        self.err_i   = intercon.err


class WishboneSlave:
    """
    Defines the wishbone slave signals

    :param intercon: the intercon bus.
    """
    def __init__(self, intercon):
        """
        Initializes the IO ports.
        """
        if not isinstance(intercon, WishboneIntercon):
            raise AttributeError("Unknown intercon type for {0}".format(str(intercon)))

        self.clk_i   = intercon.clk
        self.rst_i   = intercon.rst
        self.addr_i  = intercon.addr
        self.dat_o   = intercon.dat_i
        self.dat_i   = intercon.dat_o
        self.sel_i   = intercon.sel
        self.cti_i   = intercon.cti
        self.cyc_i   = intercon.cyc
        self.we_i    = intercon.we
        self.stb_i   = intercon.stb
        self.stall_o = intercon.stall
        self.ack_o   = intercon.ack
        self.err_o   = intercon.err


class WishboneMasterGenerator():
    def __init__(self, master_signals, flagread, flagwrite, flagrmw):
        if isinstance(master_signals, WishboneMaster):
            self.wbmsig = master_signals
        else:
            raise AttributeError("Argument slave_signals must be of type WishboneSlave. Argument: {0}".format(str(master_signals)))

        self.flagread  = flagread
        self.flagwrite = flagwrite
        self.flagrmw   = flagrmw

    def gen_wbm(self):
        """
        State machine for master.
        Generates the state signals for the master.
        """
        self.wbm_states_t = enum('WBM_IDLE',
                                 'WBM_INCYCLE',
                                 'WBM_READ_WAIT',
                                 'WBM_WRITE_WAIT',
                                 'WBM_RMW_RD_WAIT',
                                 'WBM_RMW_MID_WAIT',
                                 'WBM_RMW_WR_WAIT')
        self.wbm_state = Signal(self.wbm_states_t.WBM_IDLE)

        self.list_trig_signals = []
        for i in zip(('trig_rd', 'trig_wr', 'trig_rmw'), self.wbm_states_t._names[2:5], (self.flagread, self.flagwrite, self.flagrmw)):
            self.list_trig_signals.append({"name": i[0], "initstate": getattr(self.wbm_states_t, i[1]), "trig": i[2]})

        trig_vector = Signal(modbv(0)[len(self.list_trig_signals):])
        ack_vector     = Signal(modbv(0)[2:])

        @always_comb
        def concat_trig_vector():
            trig_vector.next = concat(self.flagread, self.flagwrite, self.flagrmw)

        @always_comb
{'fraction_non_alphanumeric': 0.08897937965690522, 'fraction_numerical': 0.004851845434066886, 'mean_word_length': 2.2792613636363637, 'pattern_counts': {'":': 6, '<': 9, '<?xml version=': 0, '>': 9, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 12, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3167968', 'n_tokens_mistral': 3715, 'n_tokens_neox': 3522, 'n_words': 1016}