<commit_before>import unittest
from hdl_toolkit.synthetisator.rtlLevel.signal import Signal
from hdl_toolkit.hdlObjects.types.defs import BIT, BOOL
from hdl_toolkit.hdlObjects.operatorDefs import AllOps

class Expr2CondTC(unittest.TestCase):    
    def setUp(self):
        unittest.TestCase.setUp(self)
        self.a = Signal("a", BIT)
        self.b = Signal("b", BIT)
        self.c = Signal("c", BIT)
    
    def testSignalTypes(self):
        self.assertEqual(self.a.defaultVal.vldMask, 0)
    
    def testSTD_LOGIC2BoolConversion(self):
        e = self.a
        cond = e._dtype.convert(e, BOOL)
        self.assertTrue(cond.origin.operator == AllOps.EQ)
        self.assertEqual(cond.origin.ops[0], self.a, 1)
        
    def testAndWithToBoolConversion(self):
        e = self.a & self.b
        cond = e._dtype.convert(e, BOOL)
        self.assertTrue(cond.origin.operator == AllOps.AND_LOG)
        andop = cond.origin
        aEq1 = andop.ops[0].origin
        bEq1 = andop.ops[1].origin
        
        self.assertEqual(aEq1.operator, AllOps.EQ)
        self.assertEqual(aEq1.ops[0], self.a)
        self.assertEqual(aEq1.ops[1].val, 1)
        
        self.assertEqual(bEq1.operator, AllOps.EQ)
        self.assertEqual(bEq1.ops[0], self.b)
        self.assertEqual(bEq1.ops[1].val, 1)
        
        
    def testNotAnd(self):
        e = ~(self.a & self.b)
        cond = e._dtype.convert(e, BOOL)
        # expr_debug(e)
        
        self.assertEqual(cond.origin.operator, AllOps.NOT)
        andOp = cond.origin.ops[0].origin
        self.assertEqual(andOp.operator, AllOps.AND_LOG)
        
        aEq1 = andOp.ops[0].origin
        bEq1 = andOp.ops[1].origin
        
        self.assertEqual(aEq1.operator, AllOps.EQ)
        self.assertEqual(bEq1.operator, AllOps.EQ)
        
        self.assertEqual(aEq1.ops[0], self.a)
        self.assertEqual(aEq1.ops[1].val, 1)
        
        self.assertEqual(bEq1.ops[0], self.b)
        self.assertEqual(bEq1.ops[1].val, 1)

        
        
        
        
    
if __name__ == '__main__':
    unittest.main(verbosity=3)<commit_msg>update to current type system<commit_after>import unittest
from hdl_toolkit.synthetisator.rtlLevel.signal import Signal
from hdl_toolkit.hdlObjects.types.defs import BIT, BOOL
from hdl_toolkit.hdlObjects.operatorDefs import AllOps

class Expr2CondTC(unittest.TestCase):    
    def setUp(self):
        unittest.TestCase.setUp(self)
        self.a = Signal("a", BIT)
        self.b = Signal("b", BIT)
        self.c = Signal("c", BIT)
    
    def testSignalTypes(self):
        self.assertEqual(self.a.defaultVal.vldMask, 0)
    
    def testSTD_LOGIC2BoolConversion(self):
        e = self.a
        cond = e._dtype.convert(e, BOOL)
        self.assertTrue(cond.origin.operator == AllOps.EQ)
        self.assertEqual(cond.origin.ops[0], self.a, 1)
        
    def testNotAnd(self):
        e = ~(self.a & self.b)
        self.assertEqual(e.origin.operator, AllOps.NOT)
        cond = e._convert(BOOL)
        
        self.assertEqual(cond.origin.operator, AllOps.EQ)
        _e = cond.origin.ops[0]
        self.assertEqual(e, _e)
        
        andOp = e.origin.ops[0].origin
        self.assertEqual(andOp.operator, AllOps.AND_LOG)
        
        op0 = andOp.ops[0]
        op1 = andOp.ops[1]
        
        self.assertEqual(op0, self.a)
        self.assertEqual(op1, self.b)
        

        
        
        
        
    
if __name__ == '__main__':
    unittest.main(verbosity=3)
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