<commit_before>package ucesoft.cbm.c128

import ucesoft.cbm.cpu.RAMComponent
import ucesoft.cbm.CBMComponentType
import ucesoft.cbm.Log
import ucesoft.cbm.ChipID
import java.io.ObjectOutputStream
import java.io.ObjectInputStream
import javax.swing.JFrame
import ucesoft.cbm.cpu.Memory

private[c128] class C128RAM extends RAMComponent {
  val name = "C128 RAM Blocks"
  val componentID = "C128_RAM"
  val isRom = false
  val startAddress = 0
  val length = 0x10000
  val componentType = CBMComponentType.MEMORY
  val isActive = true  
  
  // RAM BANKS 0,1,2,3 ------------------------------------
  private[this] final val mem = Array.ofDim[Array[Int]](4)
  private[this] var processorBank,VICbank = 0
  private[this] var expanded = false
  // common ram ------------------------------------
  private[this] final val NO_COMMON_RAM = 0
  private[this] final val BOTTOM_COMMON_RAM = 1
  private[this] final val TOP_COMMON_RAM = 2
  private[this] final val TOP_BOTTOM_COMMON_RAM = 3
  private[this] final val COMMON_RAM_SIZE_FROM_BOTTOM = Array(0,0x400,0x1000,0x2000,0x4000) // 1K,4K,8K,16K
  private[this] final val COMMON_RAM_SIZE_FROM_TOP = COMMON_RAM_SIZE_FROM_BOTTOM map { 0xFFFF - _ }
  private[this] var commonAreaSize = 0
  private[this] var commonArea = NO_COMMON_RAM
  private[this] var commonAreaBottomLimit = COMMON_RAM_SIZE_FROM_BOTTOM(commonAreaSize + 1)
  private[this] var commonAreaTopLimit = COMMON_RAM_SIZE_FROM_TOP(commonAreaSize + 1)
  // page 0 & 1 ------------------------------------
  private[this] var page_0,page_1,page_0_bank,page_1_bank = 0
  // -----------------------------------------------
  private object Bank0 extends Memory {
    val isRom = false
    val length = 0x10000
    val startAddress = 0
    val name = "RAM_bank0"
    
    def init {}
    def isActive = true  
    def read(address: Int, chipID: ChipID.ID = ChipID.CPU): Int = mem(0)(address)
    def write(address: Int, value: Int, chipID: ChipID.ID = ChipID.CPU) = mem(0)(address) = value
  }
  
  def getBank0 : Memory = Bank0
  
   override def getProperties = {
    super.getProperties
    properties.setProperty("Processor memory bank",processorBank.toString)
    properties.setProperty("VIC memory bank",VICbank.toString)
    val ca = commonArea match {
      case NO_COMMON_RAM => "None"
      case BOTTOM_COMMON_RAM => "Bottom"
      case TOP_COMMON_RAM => "Top"
      case TOP_BOTTOM_COMMON_RAM => "Bottom+Top"
    }
    properties.setProperty("Common area:",ca)
    properties.setProperty("Page 0 address:",Integer.toHexString(page_0 << 8 | page_0_bank << 16))
    properties.setProperty("Page 1 address:",Integer.toHexString(page_1 << 8 | page_1_bank << 16))
    properties
  }
  
  final def init {
    Log.info("Initialaizing C128 RAM memory ...")
    // only the first two banks are initialized
    mem(0) = Array.ofDim[Int](0x10000)
    mem(1) = Array.ofDim[Int](0x10000)
  }
  
  final def reset {
    processorBank = 0
    VICbank = 0
    commonAreaSize = 0
    commonArea = NO_COMMON_RAM
    commonAreaBottomLimit = COMMON_RAM_SIZE_FROM_BOTTOM(commonAreaSize + 1)
    commonAreaTopLimit = COMMON_RAM_SIZE_FROM_TOP(commonAreaSize + 1)
    page_0 = 0
    page_0_bank = 0
    page_1 = 1
    page_1_bank = 0
    for(m <- 0 until 4;if mem(m) != null) {
      var i = 0
      while (i < mem(m).length) {
        for(j <- 1 to 64) {
          mem(m)(i) = 0
          i += 1
        }
        for(j <- 1 to 64) {
          mem(m)(i) = 0xFF
          i += 1
        }
      }
    }
  }
  
  final def getBanksNumber : Int = if (expanded) 4 else 2
  /**
   * Set the bank that the processor sees
   * $D500/$FF00 (bit 7-6)
   */
  final def setProcessorBank(bank:Int) {
    if (expanded) processorBank = bank & 0x3 
    else processorBank = bank & 0x1
    Log.debug(s"Set processor bank to $processorBank")<commit_msg>Fixed memory reset: now the memory is not erased on reset<commit_after>package ucesoft.cbm.c128

import ucesoft.cbm.cpu.RAMComponent
import ucesoft.cbm.CBMComponentType
import ucesoft.cbm.Log
import ucesoft.cbm.ChipID
import java.io.ObjectOutputStream
import java.io.ObjectInputStream
import javax.swing.JFrame
import ucesoft.cbm.cpu.Memory

private[c128] class C128RAM extends RAMComponent {
  val name = "C128 RAM Blocks"
  val componentID = "C128_RAM"
  val isRom = false
  val startAddress = 0
  val length = 0x10000
  val componentType = CBMComponentType.MEMORY
  val isActive = true  
  
  // RAM BANKS 0,1,2,3 ------------------------------------
  private[this] final val mem = Array.ofDim[Array[Int]](4)
  private[this] var processorBank,VICbank = 0
  private[this] var expanded = false
  // common ram ------------------------------------
  private[this] final val NO_COMMON_RAM = 0
  private[this] final val BOTTOM_COMMON_RAM = 1
  private[this] final val TOP_COMMON_RAM = 2
  private[this] final val TOP_BOTTOM_COMMON_RAM = 3
  private[this] final val COMMON_RAM_SIZE_FROM_BOTTOM = Array(0,0x400,0x1000,0x2000,0x4000) // 1K,4K,8K,16K
  private[this] final val COMMON_RAM_SIZE_FROM_TOP = COMMON_RAM_SIZE_FROM_BOTTOM map { 0xFFFF - _ }
  private[this] var commonAreaSize = 0
  private[this] var commonArea = NO_COMMON_RAM
  private[this] var commonAreaBottomLimit = COMMON_RAM_SIZE_FROM_BOTTOM(commonAreaSize + 1)
  private[this] var commonAreaTopLimit = COMMON_RAM_SIZE_FROM_TOP(commonAreaSize + 1)
  // page 0 & 1 ------------------------------------
  private[this] var page_0,page_1,page_0_bank,page_1_bank = 0
  // -----------------------------------------------
  private object Bank0 extends Memory {
    val isRom = false
    val length = 0x10000
    val startAddress = 0
    val name = "RAM_bank0"
    
    def init {}
    def isActive = true  
    def read(address: Int, chipID: ChipID.ID = ChipID.CPU): Int = mem(0)(address)
    def write(address: Int, value: Int, chipID: ChipID.ID = ChipID.CPU) = mem(0)(address) = value
  }
  
  def getBank0 : Memory = Bank0
  
   override def getProperties = {
    super.getProperties
    properties.setProperty("Processor memory bank",processorBank.toString)
    properties.setProperty("VIC memory bank",VICbank.toString)
    val ca = commonArea match {
      case NO_COMMON_RAM => "None"
      case BOTTOM_COMMON_RAM => "Bottom"
      case TOP_COMMON_RAM => "Top"
      case TOP_BOTTOM_COMMON_RAM => "Bottom+Top"
    }
    properties.setProperty("Common area:",ca)
    properties.setProperty("Page 0 address:",Integer.toHexString(page_0 << 8 | page_0_bank << 16))
    properties.setProperty("Page 1 address:",Integer.toHexString(page_1 << 8 | page_1_bank << 16))
    properties
  }
  
  final def init {
    Log.info("Initialaizing C128 RAM memory ...")
    // only the first two banks are initialized
    mem(0) = Array.ofDim[Int](0x10000)
    mem(1) = Array.ofDim[Int](0x10000)
    for(m <- 0 until 4;if mem(m) != null) {
      var i = 0
      while (i < mem(m).length) {
        for(j <- 1 to 64) {
          mem(m)(i) = 0
          i += 1
        }
        for(j <- 1 to 64) {
          mem(m)(i) = 0xFF
          i += 1
        }
      }
    }
  }
  
  final def reset {
    processorBank = 0
    VICbank = 0
    commonAreaSize = 0
    commonArea = NO_COMMON_RAM
    commonAreaBottomLimit = COMMON_RAM_SIZE_FROM_BOTTOM(commonAreaSize + 1)
    commonAreaTopLimit = COMMON_RAM_SIZE_FROM_TOP(commonAreaSize + 1)
    page_0 = 0
    page_0_bank = 0
    page_1 = 1
    page_1_bank = 0    
  }
  
  final def getBanksNumber : Int = if (expanded) 4 else 2
  /**
   * Set the bank that the processor sees
   * $D500/$FF00 (bit 7-6)
   */
  final def setProcessorBank(bank:Int) {
    if (expanded) processorBank = bank & 0x3 
    else processorBank = bank & 0x1
    Log.debug(s"Set processor bank to $processorBank")
{'fraction_non_alphanumeric': 0.13552494802494802, 'fraction_numerical': 0.038721413721413724, 'mean_word_length': 2.738222438076736, 'pattern_counts': {'":': 0, '<': 27, '<?xml version=': 0, '>': 11, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3302311', 'n_tokens_mistral': 2856, 'n_tokens_neox': 2592, 'n_words': 637}