<commit_before>import os
from fusesoc import utils
from fusesoc.utils import Launcher, pr_warn

class Section(object):
    def __init__(self):
        self.name = ""
        self.strings = []
        self.lists  = []
        self.export_files = []

    def _add_listitem(self, listitem):
        self.lists += [listitem]
        setattr(self, listitem, [])

    def _add_stringitem(self, s):
        self.strings += [s]
        setattr(self, s, "")

    def export(self):
        return self.export_files

    def load_dict(self, items):
        for item in items:
            if item in self.lists:
                setattr(self, item, items.get(item).split())
            elif item in self.strings:
                setattr(self, item, items.get(item))
            else:
                pr_warn("Warning: Unknown item '{item}' in section '{section}'".format(item=item, section=self.name))

    def __str__(self):
        s = ''
        for item in self.lists:
            s += item + ' : ' + ';'.join(getattr(self, item)) + '\n'
        for item in self.strings:
            s += item + ' : ' + getattr(self, item) + '\n'
        return s

    @staticmethod
    def factory(type, items=None):
        if type == 'icarus'    : return IcarusSection(items)
        if type == 'modelsim'  : return ModelsimSection(items)
        if type == 'verilator' : return VerilatorSection(items)
        if type == 'vhdl'      : return VhdlSection(items)
        if type == 'verilog'   : return VerilogSection(items)
        if type == 'vpi'       : return VpiSection(items)
        raise Exception

class VhdlSection(Section):
    def __init__(self, items=None):
        super(VhdlSection, self).__init__()

        self._add_listitem('src_files')

        self.name = 'vhdl'

        if items:
            self.load_dict(items)
            self.export_files = self.src_files

class VerilogSection(Section):
    def __init__(self, items=None):
        super(VerilogSection, self).__init__()

        self.include_dirs = []
        self.tb_include_dirs = []

        self.name = 'verilog'
        self._add_listitem('src_files')
        self._add_listitem('include_files')
        self._add_listitem('tb_src_files')<commit_msg>section: Add IseSection to factory<commit_after>import os
from fusesoc import utils
from fusesoc.utils import Launcher, pr_warn

class Section(object):
    def __init__(self):
        self.name = ""
        self.strings = []
        self.lists  = []
        self.export_files = []

    def _add_listitem(self, listitem):
        self.lists += [listitem]
        setattr(self, listitem, [])

    def _add_stringitem(self, s):
        self.strings += [s]
        setattr(self, s, "")

    def export(self):
        return self.export_files

    def load_dict(self, items):
        for item in items:
            if item in self.lists:
                setattr(self, item, items.get(item).split())
            elif item in self.strings:
                setattr(self, item, items.get(item))
            else:
                pr_warn("Warning: Unknown item '{item}' in section '{section}'".format(item=item, section=self.name))

    def __str__(self):
        s = ''
        for item in self.lists:
            s += item + ' : ' + ';'.join(getattr(self, item)) + '\n'
        for item in self.strings:
            s += item + ' : ' + getattr(self, item) + '\n'
        return s

    @staticmethod
    def factory(type, items=None):
        if type == 'icarus'    : return IcarusSection(items)
        if type == 'modelsim'  : return ModelsimSection(items)
        if type == 'verilator' : return VerilatorSection(items)
        if type == 'ise'       : return IseSection(items)
        if type == 'vhdl'      : return VhdlSection(items)
        if type == 'verilog'   : return VerilogSection(items)
        if type == 'vpi'       : return VpiSection(items)
        raise Exception

class VhdlSection(Section):
    def __init__(self, items=None):
        super(VhdlSection, self).__init__()

        self._add_listitem('src_files')

        self.name = 'vhdl'

        if items:
            self.load_dict(items)
            self.export_files = self.src_files

class VerilogSection(Section):
    def __init__(self, items=None):
        super(VerilogSection, self).__init__()

        self.include_dirs = []
        self.tb_include_dirs = []

        self.name = 'verilog'
        self._add_listitem('src_files')
        self._add_listitem('include_files')
        self._add_listitem('tb_src_files')
{'fraction_non_alphanumeric': 0.12214079502553853, 'fraction_numerical': 0.0, 'mean_word_length': 2.185289957567185, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4709796', 'n_tokens_mistral': 1419, 'n_tokens_neox': 1380, 'n_words': 318}