<commit_before>from hdl_toolkit.synthetisator.interfaceLevel.interface import  Interface
from hdl_toolkit.synthetisator.param import Param
from hdl_toolkit.interfaces.std import s, D
from hdl_toolkit.hdlObjects.typeShortcuts import vecT


BURST_FIXED = 0b00
BURST_INCR = 0b01
BURST_WRAP = 0b10

BYTES_IN_TRANS_1 = 0b000
BYTES_IN_TRANS_2 = 0b001
BYTES_IN_TRANS_4 = 0b010
BYTES_IN_TRANS_8 = 0b011
BYTES_IN_TRANS_16 = 0b100
BYTES_IN_TRANS_32 = 0b101
BYTES_IN_TRANS_64 = 0b110
BYTES_IN_TRANS_128 = 0b111

CACHE_DEFAULT = 3
PROT_DEFAULT = 0
QOS_DEFAULT = 0
LOCK_DEFAULT = 0
RESP_OKAY = 0
RESP_EXOKAY = 1
RESP_SLVERR = 2
RESP_DECERR = 3

# http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf
    
class AxiStream_withoutSTRB(Interface):
    def _config(self):
        self.DATA_WIDTH = Param(64)

    def _declr(self):
        self.last = s(masterDir=D.OUT, alternativeNames=['tlast' ])
        self.data = s(masterDir=D.OUT, dtype=vecT(self.DATA_WIDTH), alternativeNames=['tdata' ])
        self.ready = s(masterDir=D.IN, alternativeNames=['tready' ])
        self.valid = s(masterDir=D.OUT, alternativeNames=['tvalid' ])

class AxiStream(AxiStream_withoutSTRB):
    def _declr(self):
        super(AxiStream, self)._declr()<commit_msg>BYTES_IN_TRANS as dictionary<commit_after>from hdl_toolkit.synthetisator.interfaceLevel.interface import  Interface
from hdl_toolkit.synthetisator.param import Param
from hdl_toolkit.interfaces.std import s, D
from hdl_toolkit.hdlObjects.typeShortcuts import vecT


BURST_FIXED = 0b00
BURST_INCR = 0b01
BURST_WRAP = 0b10

BYTES_IN_TRANS = {1 : 0b000,
                  2 : 0b001,
                  4 : 0b010,
                  8 : 0b011,
                  16: 0b100,
                  32: 0b101,
                  64: 0b110,
                  128 : 0b111
                  }

CACHE_DEFAULT = 3
PROT_DEFAULT = 0
QOS_DEFAULT = 0
LOCK_DEFAULT = 0
RESP_OKAY = 0
RESP_EXOKAY = 1
RESP_SLVERR = 2
RESP_DECERR = 3

# http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf
    
class AxiStream_withoutSTRB(Interface):
    def _config(self):
        self.DATA_WIDTH = Param(64)

    def _declr(self):
        self.last = s(masterDir=D.OUT, alternativeNames=['tlast' ])
        self.data = s(masterDir=D.OUT, dtype=vecT(self.DATA_WIDTH), alternativeNames=['tdata' ])
        self.ready = s(masterDir=D.IN, alternativeNames=['tready' ])
        self.valid = s(masterDir=D.OUT, alternativeNames=['tvalid' ])

class AxiStream(AxiStream_withoutSTRB):
    def _declr(self):
        super(AxiStream, self)._declr()
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