<commit_before>/* Exposes datatypes and functionaly of the VR4300 CPU. */

/*

CPU0

  00h = r0/reg0     08h = t0/reg8     10h = s0/reg16    18h = t8/reg24
  01h = at/reg1     09h = t1/reg9     11h = s1/reg17    19h = t9/reg25
  02h = v0/reg2     0Ah = t2/reg10    12h = s2/reg18    1Ah = k0/reg26
  03h = v1/reg3     0Bh = t3/reg11    13h = s3/reg19    1Bh = k1/reg27
  04h = a0/reg4     0Ch = t4/reg12    14h = s4/reg20    1Ch = gp/reg28
  05h = a1/reg5     0Dh = t5/reg13    15h = s5/reg21    1Dh = sp/reg29
  06h = a2/reg6     0Eh = t6/reg14    16h = s6/reg22    1Eh = s8/reg30
  07h = a3/reg7     0Fh = t7/reg15    17h = s7/reg23    1Fh = ra/reg31

COP0

  00h = Index       08h = BadVAddr    10h = Config      18h = *RESERVED*
  01h = Random      09h = Count       11h = LLAddr      19h = *RESERVED*
  02h = EntryLo0    0Ah = EntryHi     12h = WatchLo     1Ah = PErr
  03h = EntryLo1    0Bh = Compare     13h = WatchHi     1Bh = CacheErr
  04h = Context     0Ch = Status      14h = XContext    1Ch = TagLo
  05h = PageMask    0Dh = Cause       15h = *RESERVED*  1Dh = TagHi
  06h = Wired       0Eh = EPC         16h = *RESERVED*  1Eh = ErrorEPC
  07h = *RESERVED*  0Fh = PRevID      17h = *RESERVED*  1Fh = *RESERVED*

 */

 use n64::N64;
 use n64::mc;

/* Size of the general purpose register file. */
const GPR_SIZE: usize = 32;

pub struct CPU {

	/* The CPU's register file. */
	gpr: [u32; GPR_SIZE],

	/* The program counter. */
	pc: u32
}

impl CPU {
	pub fn new(pc: u32) -> CPU {
		CPU {
			/* Zero-initialize the general purpose registers. */
			gpr: [0; GPR_SIZE],
			/* Initialize the program counter. */
			pc: pc
		}
	}
}

/* Executes a single instruction on the given N64. */
pub fn cycle(n64: &mut N64) {
	/* Fetch the next instrution from memory. */
	let inst = mc::read(n64, n64.cpu.pc as usize);
	println!("Cycle. Read raw instruction {:#x}.", inst);
	/* Execute the instrution. */

	/* Increment the program counter. */
	n64.cpu.pc += 4;
}
<commit_msg>Added instruction extension to u32.<commit_after>/* Exposes datatypes and functionaly of the VR4300 CPU. */

/*

CPU0

  00h = r0/reg0     08h = t0/reg8     10h = s0/reg16    18h = t8/reg24
  01h = at/reg1     09h = t1/reg9     11h = s1/reg17    19h = t9/reg25
  02h = v0/reg2     0Ah = t2/reg10    12h = s2/reg18    1Ah = k0/reg26
  03h = v1/reg3     0Bh = t3/reg11    13h = s3/reg19    1Bh = k1/reg27
  04h = a0/reg4     0Ch = t4/reg12    14h = s4/reg20    1Ch = gp/reg28
  05h = a1/reg5     0Dh = t5/reg13    15h = s5/reg21    1Dh = sp/reg29
  06h = a2/reg6     0Eh = t6/reg14    16h = s6/reg22    1Eh = s8/reg30
  07h = a3/reg7     0Fh = t7/reg15    17h = s7/reg23    1Fh = ra/reg31

COP0

  00h = Index       08h = BadVAddr    10h = Config      18h = *RESERVED*
  01h = Random      09h = Count       11h = LLAddr      19h = *RESERVED*
  02h = EntryLo0    0Ah = EntryHi     12h = WatchLo     1Ah = PErr
  03h = EntryLo1    0Bh = Compare     13h = WatchHi     1Bh = CacheErr
  04h = Context     0Ch = Status      14h = XContext    1Ch = TagLo
  05h = PageMask    0Dh = Cause       15h = *RESERVED*  1Dh = TagHi
  06h = Wired       0Eh = EPC         16h = *RESERVED*  1Eh = ErrorEPC
  07h = *RESERVED*  0Fh = PRevID      17h = *RESERVED*  1Fh = *RESERVED*

 */

 use n64::N64;
 use n64::mc;

/* Size of the general purpose register file. */
const GPR_SIZE: usize = 32;

pub struct CPU {

	/* The CPU's register file. */
	gpr: [u32; GPR_SIZE],

	/* The program counter. */
	pc: u32
}

impl CPU {
	pub fn new(pc: u32) -> CPU {
		CPU {
			/* Zero-initialize the general purpose registers. */
			gpr: [0; GPR_SIZE],
			/* Initialize the program counter. */
			pc: pc
		}
	}
}

struct Inst(pub u32);

impl Inst {
	/* Returns the instruction's opcode. */
	pub fn op(&self) -> u8{
		((self.0 >> 26) & 0b111111) as u8
	}
	/* Returns the instruction's source register. */
	pub fn rs(&self) -> u8{
		((self.0 >> 21) & 0b11111) as u8
	}
	/* Returns the instruction's target register. */
	pub fn rt(&self) -> u8 {
		((self.0 >> 16) & 0b11111) as u8
	}
	/* Returns the instruciton's destination register. */
	pub fn rd(&self) -> u8 {
		((self.0 >> 11) & 0b11111) as u8
	}
	/* Returns the instruction's shift amount. */
	pub fn sa(&self) -> u8 {
		((self.0 >> 6) & 0b11111) as u8
	}
	/* Returns the instruction's immediate value. */
	pub fn imm(&self) -> u32 {
		self.0 & 0xffff
	}
	/* Return's the function's funct field. */
	pub fn funct(&self) -> u8 {
		0
	}
	/* Return's the instruction's target field. */
	pub fn target(&self) -> u32 {
		0
	}
}

/* Executes a single instruction on the given N64. */
pub fn cycle(n64: &mut N64) {
	/* Fetch the next instrution from memory. */
	let inst = Inst(mc::read(n64, n64.cpu.pc as usize));
	println!("Cycle. Read raw instruction {:#x}.", inst.0);
	/* Execute the instrution. */
	match inst.op() {
		_ => return
	}
	/* Increment the program counter. */
	n64.cpu.pc += 4;
}

{'fraction_non_alphanumeric': 0.13030116779348494, 'fraction_numerical': 0.10510141364474493, 'mean_word_length': 2.1135204081632653, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 24, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1633792', 'n_tokens_mistral': 2286, 'n_tokens_neox': 2025, 'n_words': 574}