<commit_before>/*
* File:    linux-ia64.c
* CVS:     $Id$
* Author:  <NAME>
*          <EMAIL>
* Mods:	   <NAME>
*	   <EMAIL>
*          <NAME>
*          <EMAIL>
*          <NAME>
*          <EMAIL>
*/

#include SUBSTRATE

#include "pfmwrap.h"

#ifdef PFM06A
static preset_search_t preset_search_map[] = { 
  {PAPI_L1_TCM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_RETIRED",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,DERIVED_SUB,{"L2_MISSES","L3_READS.INST_READS.ALL",0,0}},
  {PAPI_L2_ICM,0,{"L3_READS.INST_READS.ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS.INST_READS.MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS.DATA_READS.MISS","L3_WRITES.DATA_WRITES.MISS",0,0}},
  {PAPI_L3_LDM,DERIVED_ADD,{"L3_READS.DATA_READS.MISS","L3_READS.INST_READS.MISS",0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES.DATA_WRITES.MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,DERIVED_ADD,{"L3_READS.DATA_READS.ALL","L3_READS.INST_READS.ALL",0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES.ALL_WRITES.ALL",0,0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS.DATA_READS.HIT","L3_WRITES.DATA_WRITES.HIT",0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_RETIRED","L1D_READ_MISSES_RETIRED",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_RETIRED",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES.ALL",0,0,0}},
  {PAPI_L3_DCA,DERIVED_ADD,{"L3_READS.DATA_READS.ALL","L3_WRITES.DATA_WRITES.ALL",0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES.READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS.DATA_READS.ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES.WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES.DATA_WRITES.ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS.INST_READS.HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCH_READS","L1I_DEMAND_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCH_READS",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS.INST_READS.ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH",0,0,0}},
  {PAPI_MEM_SCY,0,{"MEMORY_CYCLE",0,0,0}},
  {PAPI_STL_ICY,0,{"INST_FETCH_CYCLE",0,0,0}},
  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}},
  {PAPI_BR_PRC,0,{"BRANCH_PREDICATOR.ALL.CORRECT_PREDICTIONS",0,0,0}},
  {PAPI_BR_MSP,DERIVED_ADD,{"BRANCH_PREDICATOR.ALL.WRONG_PATH","BRANCH_PREDICATOR.ALL.WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,DERIVED_ADD,{"FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0,0}},
  {PAPI_TOT_INS,0,{"IA64_INST_RETIRED",0,0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_FLOPS,DERIVED_ADD_PS,{"CPU_CYCLES","FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0}},
  {0,0,{0,0,0,0}}};
#else
#ifndef ITANIUM2
static preset_search_t preset_search_map[] = { 
  {PAPI_L1_TCM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_RETIRED",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,DERIVED_SUB,{"L2_MISSES","L3_READS_INST_READS_ALL",0,0}},
  {PAPI_L2_ICM,0,{"L3_READS_INST_READS_ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS_INST_READS_MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS_DATA_READS_MISS","L3_WRITES_DATA_WRITES_MISS",0,0}},
  {PAPI_L3_LDM,DERIVED_ADD,{"L3_READS_DATA_READS_MISS","L3_READS_INST_READS_MISS",0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES_DATA_WRITES_MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,DERIVED_ADD,{"L3_READS_DATA_READS_ALL","L3_READS_INST_READS_ALL",0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES_ALL_WRITES_ALL",0,0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS_DATA_READS_HIT","L3_WRITES_DATA_WRITES_HIT",0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_RETIRED","L1D_READ_MISSES_RETIRED",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_RETIRED",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES_ALL",0,0,0}},
  {PAPI_L3_DCA,DERIVED_ADD,{"L3_READS_DATA_READS_ALL","L3_WRITES_DATA_WRITES_ALL",0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES_READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS_DATA_READS_ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES_WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES_DATA_WRITES_ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS_INST_READS_HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCH_READS","L1I_DEMAND_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCH_READS",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS_INST_READS_ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH",0,0,0}},
  {PAPI_MEM_SCY,0,{"MEMORY_CYCLE",0,0,0}},
  {PAPI_STL_ICY,0,{"UNSTALLED_BACKEND_CYCLE",0,0,0}},
  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}}, 
  {PAPI_BR_PRC,0,{"BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS",0,0,0}}, 
  {PAPI_BR_MSP,DERIVED_ADD,{"BRANCH_PREDICTOR_ALL_WRONG_PATH","BRANCH_PREDICTOR_ALL_WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,DERIVED_ADD,{"FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0,0}},
  {PAPI_TOT_INS,0,{"IA64_INST_RETIRED",0,0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_LST_INS,DERIVED_ADD,{"LOADS_RETIRED","STORES_RETIRED",0,0}},
  {PAPI_FLOPS,DERIVED_ADD_PS,{"CPU_CYCLES","FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0}},
  {0,0,{0,0,0,0}}};
#else
static preset_search_t preset_search_map[] = {
  {PAPI_CA_SNP,0,{"BUS_SNOOPS_SELF",0,0,0}},
  {PAPI_CA_INV,DERIVED_ADD,{"BUS_MEM_READ_BRIL_SELF","BUS_MEM_READ_BIL_SELF",0,0}},
  {PAPI_TLB_TL,DERIVED_ADD,{"ITLB_MISSES_FETCH_L2ITLB","L2DTLB_MISSES",0,0}},
  {PAPI_STL_ICY,0,{"DISP_STALLED",0,0,0}},
  {PAPI_STL_CCY,0,{"BACK_END_BUBBLE_ALL",0,0,0}},
  {PAPI_TOT_IIS,0,{"INST_DISPERSED",0,0,0}},
  {PAPI_RES_STL,0,{"BE_EXE_BUBBLE_ALL",0,0,0}},
  {PAPI_FP_STAL,0,{"BE_EXE_BUBBLE_FRALL",0,0,0}},
  {PAPI_L2_TCR,DERIVED_ADD,{"L2_DATA_REFERENCES_L2_DATA_READS","L2_INST_DEMAND_READS","L2_INST_PREFETCHES",0}},
  {PAPI_L1_TCM,DERIVED_ADD,{"L2_INST_DEMAND_READS","L1D_READ_MISSES_ALL",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_ALL",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,0,{"L3_READS_DATA_READ_ALL",0,0,0}},
  {PAPI_L2_ICM,0,{"L3_READS_INST_FETCH_ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS_INST_FETCH_MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS_DATA_READ_MISS","L3_WRITES_DATA_WRITE_MISS",0,0}},
  {PAPI_L3_LDM,0,{"L3_READS_ALL_MISS",0,0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES_DATA_WRITE_MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_ALL","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,0,{"L3_READS_ALL_ALL",0,0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES_ALL_ALL",0,0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_SET1","L1D_READ_MISSES_ALL",0,0}},
  {PAPI_L2_DCH,DERIVED_SUB,{"L2_DATA_REFERENCES_L2_ALL","L2_MISSES",0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS_DATA_READ_HIT","L3_WRITES_DATA_WRITE_HIT",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_SET1",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES_L2_ALL",0,0,0}},
  {PAPI_L3_DCA,0,{"L3_REFERENCES",0,0,0}},
  {PAPI_L1_DCR,0,{"L1D_READS_SET1",0,0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES_L2_DATA_READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS_DATA_READ_ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES_L2_DATA_WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES_DATA_WRITE_ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS_DINST_FETCH_HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCHES","L1I_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCHES",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS_INST_FETCH_ALL",0,0,0}},
  {PAPI_L1_ICA,DERIVED_ADD,{"L1I_PREFETCHES","L1I_READS",0,0}},
  {PAPI_L2_TCH,DERIVED_SUB,{"L2_REFERENCES","L2_MISSES",0,0}},
  {PAPI_L3_TCH,DERIVED_SUB,{"L3_REFERENCES","L3_MISSES",0,0}},
  {PAPI_L2_TCA,0,{"L2_REFERENCES",0,0,0}},
  {PAPI_L3_TCA,0,{"L3_REFERENCES",0,0,0}},
  {PAPI_L3_TCR,0,{"L3_READS_ALL_ALL",0,0,0}},
  {PAPI_L3_TCW,0,{"L3_WRITES_ALL_ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"L2DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH_L2ITLB",0,0,0}},
  {PAPI_BR_INS,0,{"BR_MISPRED_DETAIL_ALL_ALL_PRED",0,0,0}},
/*  {PAPI_BR_INS,0,{"1000000037FFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}}, */
/*  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}}, Broken */
  {PAPI_BR_PRC,0,{"BR_MISPRED_DETAIL_ALL_CORRECT_PRED",0,0,0}},
  {PAPI_BR_MSP,DERIVED_ADD,{"BR_MISPRED_DETAIL_ALL_WRONG_PATH","BR_MISPRED_DETAIL_ALL_WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,0,{"FP_OPS_RETIRED",0,0,0}},
  {PAPI_TOT_INS,DERIVED_ADD,{"IA64_INST_RETIRED","IA32_INST_RETIRED",0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_FLOPS,DERIVED_PS,{"CPU_CYCLES","FP_OPS_RETIRED",0,0}},
  /* First byte selects type (M, I, F, B), bits 3-30 set to 1 to mask the whole opcode,
   * bits 1 (ig_ad) and 2 (mandatory 1) are set */
  {PAPI_INT_INS,0,{"400000003FFFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}},
  {PAPI_FSQ_INS,0,{"2890000001BFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}},
  {0,0,{0,0,0,0}}};
#endif
#endif
static hwd_preset_t preset_map[PAPI_MAX_PRESET_EVENTS];

#ifdef ITANIUM2
static pfmlib_ita2_param_t ita2_param[PAPI_MAX_PRESET_EVENTS];
#else
static pfmlib_ita_param_t ita_param[PAPI_MAX_PRESET_EVENTS];
#endif

extern void dispatch_profile(EventSetInfo *ESI, void *context,
                 long_long over, long_long threshold);


/* This substrate should never malloc anything. All allocation should be
   done by the high level API. */

/* The values defined in this file may be X86-specific (2 general 
   purpose counters, 1 special purpose counter, etc.*/

/* PAPI stuff */

/* Low level functions, should not handle errors, just return codes. */
<commit_msg>Fixed the bug manifested by sdsc.c.<commit_after>/*
* File:    linux-ia64.c
* CVS:     $Id$
* Author:  <NAME>
*          <EMAIL>
* Mods:	   <NAME>
*	   <EMAIL>
*          <NAME>
*          <EMAIL>
*          <NAME>
*          <EMAIL>
*/

#include SUBSTRATE

#include "pfmwrap.h"

#ifdef PFM06A
static preset_search_t preset_search_map[] = { 
  {PAPI_L1_TCM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_RETIRED",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,DERIVED_SUB,{"L2_MISSES","L3_READS.INST_READS.ALL",0,0}},
  {PAPI_L2_ICM,0,{"L3_READS.INST_READS.ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS.INST_READS.MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS.DATA_READS.MISS","L3_WRITES.DATA_WRITES.MISS",0,0}},
  {PAPI_L3_LDM,DERIVED_ADD,{"L3_READS.DATA_READS.MISS","L3_READS.INST_READS.MISS",0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES.DATA_WRITES.MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,DERIVED_ADD,{"L3_READS.DATA_READS.ALL","L3_READS.INST_READS.ALL",0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES.ALL_WRITES.ALL",0,0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS.DATA_READS.HIT","L3_WRITES.DATA_WRITES.HIT",0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_RETIRED","L1D_READ_MISSES_RETIRED",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_RETIRED",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES.ALL",0,0,0}},
  {PAPI_L3_DCA,DERIVED_ADD,{"L3_READS.DATA_READS.ALL","L3_WRITES.DATA_WRITES.ALL",0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES.READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS.DATA_READS.ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES.WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES.DATA_WRITES.ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS.INST_READS.HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCH_READS","L1I_DEMAND_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCH_READS",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS.INST_READS.ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH",0,0,0}},
  {PAPI_MEM_SCY,0,{"MEMORY_CYCLE",0,0,0}},
  {PAPI_STL_ICY,0,{"INST_FETCH_CYCLE",0,0,0}},
  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}},
  {PAPI_BR_PRC,0,{"BRANCH_PREDICATOR.ALL.CORRECT_PREDICTIONS",0,0,0}},
  {PAPI_BR_MSP,DERIVED_ADD,{"BRANCH_PREDICATOR.ALL.WRONG_PATH","BRANCH_PREDICATOR.ALL.WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,DERIVED_ADD,{"FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0,0}},
  {PAPI_TOT_INS,0,{"IA64_INST_RETIRED",0,0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_FLOPS,DERIVED_ADD_PS,{"CPU_CYCLES","FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0}},
  {0,0,{0,0,0,0}}};
#else
#ifndef ITANIUM2
static preset_search_t preset_search_map[] = { 
  {PAPI_L1_TCM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_RETIRED",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,DERIVED_SUB,{"L2_MISSES","L3_READS_INST_READS_ALL",0,0}},
  {PAPI_L2_ICM,0,{"L3_READS_INST_READS_ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS_INST_READS_MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS_DATA_READS_MISS","L3_WRITES_DATA_WRITES_MISS",0,0}},
  {PAPI_L3_LDM,DERIVED_ADD,{"L3_READS_DATA_READS_MISS","L3_READS_INST_READS_MISS",0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES_DATA_WRITES_MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_RETIRED","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,DERIVED_ADD,{"L3_READS_DATA_READS_ALL","L3_READS_INST_READS_ALL",0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES_ALL_WRITES_ALL",0,0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS_DATA_READS_HIT","L3_WRITES_DATA_WRITES_HIT",0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_RETIRED","L1D_READ_MISSES_RETIRED",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_RETIRED",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES_ALL",0,0,0}},
  {PAPI_L3_DCA,DERIVED_ADD,{"L3_READS_DATA_READS_ALL","L3_WRITES_DATA_WRITES_ALL",0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES_READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS_DATA_READS_ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES_WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES_DATA_WRITES_ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS_INST_READS_HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCH_READS","L1I_DEMAND_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCH_READS",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS_INST_READS_ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH",0,0,0}},
  {PAPI_MEM_SCY,0,{"MEMORY_CYCLE",0,0,0}},
  {PAPI_STL_ICY,0,{"UNSTALLED_BACKEND_CYCLE",0,0,0}},
  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}}, 
  {PAPI_BR_PRC,0,{"BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS",0,0,0}}, 
  {PAPI_BR_MSP,DERIVED_ADD,{"BRANCH_PREDICTOR_ALL_WRONG_PATH","BRANCH_PREDICTOR_ALL_WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,DERIVED_ADD,{"FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0,0}},
  {PAPI_TOT_INS,0,{"IA64_INST_RETIRED",0,0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_LST_INS,DERIVED_ADD,{"LOADS_RETIRED","STORES_RETIRED",0,0}},
  {PAPI_FLOPS,DERIVED_ADD_PS,{"CPU_CYCLES","FP_OPS_RETIRED_HI","FP_OPS_RETIRED_LO",0}},
  {0,0,{0,0,0,0}}};
#else
static preset_search_t preset_search_map[] = {
  {PAPI_CA_SNP,0,{"BUS_SNOOPS_SELF",0,0,0}},
  {PAPI_CA_INV,DERIVED_ADD,{"BUS_MEM_READ_BRIL_SELF","BUS_MEM_READ_BIL_SELF",0,0}},
  {PAPI_TLB_TL,DERIVED_ADD,{"ITLB_MISSES_FETCH_L2ITLB","L2DTLB_MISSES",0,0}},
  {PAPI_STL_ICY,0,{"DISP_STALLED",0,0,0}},
  {PAPI_STL_CCY,0,{"BACK_END_BUBBLE_ALL",0,0,0}},
  {PAPI_TOT_IIS,0,{"INST_DISPERSED",0,0,0}},
  {PAPI_RES_STL,0,{"BE_EXE_BUBBLE_ALL",0,0,0}},
  {PAPI_FP_STAL,0,{"BE_EXE_BUBBLE_FRALL",0,0,0}},
  {PAPI_L2_TCR,DERIVED_ADD,{"L2_DATA_REFERENCES_L2_DATA_READS","L2_INST_DEMAND_READS","L2_INST_PREFETCHES",0}},
  {PAPI_L1_TCM,DERIVED_ADD,{"L2_INST_DEMAND_READS","L1D_READ_MISSES_ALL",0,0}},
  {PAPI_L1_ICM,0,{"L2_INST_DEMAND_READS",0,0,0}},
  {PAPI_L1_DCM,0,{"L1D_READ_MISSES_ALL",0,0,0}},
  {PAPI_L2_TCM,0,{"L2_MISSES",0,0,0}},
  {PAPI_L2_DCM,0,{"L3_READS_DATA_READ_ALL",0,0,0}},
  {PAPI_L2_ICM,0,{"L3_READS_INST_FETCH_ALL",0,0,0}},
  {PAPI_L3_TCM,0,{"L3_MISSES",0,0,0}},
  {PAPI_L3_ICM,0,{"L3_READS_INST_FETCH_MISS",0,0,0}},
  {PAPI_L3_DCM,DERIVED_ADD,{"L3_READS_DATA_READ_MISS","L3_WRITES_DATA_WRITE_MISS",0,0}},
  {PAPI_L3_LDM,0,{"L3_READS_ALL_MISS",0,0,0}},
  {PAPI_L3_STM,0,{"L3_WRITES_DATA_WRITE_MISS",0,0,0}},
  {PAPI_L1_LDM,DERIVED_ADD,{"L1D_READ_MISSES_ALL","L2_INST_DEMAND_READS",0,0}},
  {PAPI_L2_LDM,0,{"L3_READS_ALL_ALL",0,0,0}},
  {PAPI_L2_STM,0,{"L3_WRITES_ALL_ALL",0,0,0}},
  {PAPI_L1_DCH,DERIVED_SUB,{"L1D_READS_SET1","L1D_READ_MISSES_ALL",0,0}},
  {PAPI_L2_DCH,DERIVED_SUB,{"L2_DATA_REFERENCES_L2_ALL","L2_MISSES",0,0}},
  {PAPI_L3_DCH,DERIVED_ADD,{"L3_READS_DATA_READ_HIT","L3_WRITES_DATA_WRITE_HIT",0,0}},
  {PAPI_L1_DCA,0,{"L1D_READS_SET1",0,0,0}},
  {PAPI_L2_DCA,0,{"L2_DATA_REFERENCES_L2_ALL",0,0,0}},
  {PAPI_L3_DCA,0,{"L3_REFERENCES",0,0,0}},
  {PAPI_L1_DCR,0,{"L1D_READS_SET1",0,0,0}},
  {PAPI_L2_DCR,0,{"L2_DATA_REFERENCES_L2_DATA_READS",0,0,0}},
  {PAPI_L3_DCR,0,{"L3_READS_DATA_READ_ALL",0,0,0}},
  {PAPI_L2_DCW,0,{"L2_DATA_REFERENCES_L2_DATA_WRITES",0,0,0}},
  {PAPI_L3_DCW,0,{"L3_WRITES_DATA_WRITE_ALL",0,0,0}},
  {PAPI_L3_ICH,0,{"L3_READS_DINST_FETCH_HIT",0,0,0}},
  {PAPI_L1_ICR,DERIVED_ADD,{"L1I_PREFETCHES","L1I_READS",0,0}},
  {PAPI_L2_ICR,DERIVED_ADD,{"L2_INST_DEMAND_READS","L2_INST_PREFETCHES",0,0}},
  {PAPI_L3_ICR,0,{"L3_READS_INST_FETCH_ALL",0,0,0}},
  {PAPI_L1_ICA,DERIVED_ADD,{"L1I_PREFETCHES","L1I_READS",0,0}},
  {PAPI_L2_TCH,DERIVED_SUB,{"L2_REFERENCES","L2_MISSES",0,0}},
  {PAPI_L3_TCH,DERIVED_SUB,{"L3_REFERENCES","L3_MISSES",0,0}},
  {PAPI_L2_TCA,0,{"L2_REFERENCES",0,0,0}},
  {PAPI_L3_TCA,0,{"L3_REFERENCES",0,0,0}},
  {PAPI_L3_TCR,0,{"L3_READS_ALL_ALL",0,0,0}},
  {PAPI_L3_TCW,0,{"L3_WRITES_ALL_ALL",0,0,0}},
  {PAPI_TLB_DM,0,{"L2DTLB_MISSES",0,0,0}},
  {PAPI_TLB_IM,0,{"ITLB_MISSES_FETCH_L2ITLB",0,0,0}},
  {PAPI_BR_INS,0,{"BR_MISPRED_DETAIL_ALL_ALL_PRED",0,0,0}},
/*  {PAPI_BR_INS,0,{"1000000037FFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}}, */
/*  {PAPI_BR_INS,0,{"BRANCH_EVENT",0,0,0}}, Broken */
  {PAPI_BR_PRC,0,{"BR_MISPRED_DETAIL_ALL_CORRECT_PRED",0,0,0}},
  {PAPI_BR_MSP,DERIVED_ADD,{"BR_MISPRED_DETAIL_ALL_WRONG_PATH","BR_MISPRED_DETAIL_ALL_WRONG_TARGET",0,0}},
  {PAPI_TOT_CYC,0,{"CPU_CYCLES",0,0,0}},
  {PAPI_FP_INS,0,{"FP_OPS_RETIRED",0,0,0}},
  {PAPI_TOT_INS,DERIVED_ADD,{"IA64_INST_RETIRED","IA32_INST_RETIRED",0,0}},
  {PAPI_LD_INS,0,{"LOADS_RETIRED",0,0,0}},
  {PAPI_SR_INS,0,{"STORES_RETIRED",0,0,0}},
  {PAPI_FLOPS,DERIVED_PS,{"CPU_CYCLES","FP_OPS_RETIRED",0,0}},
  /* First byte selects type (M, I, F, B), bits 3-30 set to 1 to mask the whole opcode,
   * bits 1 (ig_ad) and 2 (mandatory 1) are set */
  /* These are commented out as the substrate breaks when
     these events are multiplexed. */
#if 0
  {PAPI_INT_INS,0,{"400000003FFFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}},
  {PAPI_FSQ_INS,0,{"2890000001BFFFFF@IA64_TAGGED_INST_RETIRED_IBRP0_PMC8",0,0,0}},
#endif
  {0,0,{0,0,0,0}}};
#endif
#endif
static hwd_preset_t preset_map[PAPI_MAX_PRESET_EVENTS];

#ifdef ITANIUM2
static pfmlib_ita2_param_t ita2_param[PAPI_MAX_PRESET_EVENTS];
#else
static pfmlib_ita_param_t ita_param[PAPI_MAX_PRESET_EVENTS];
#endif

extern void dispatch_profile(EventSetInfo *ESI, void *context,
                 long_long over, long_long threshold);


/* This substrate should never malloc anything. All allocation should be
   done by the high level API. */

/* The values defined in this file may be X86-specific (2 general 
   purpose counters, 1 special purpose counter, etc.*/

/* PAPI stuff */

/* Low level functions, should not handle errors, just return codes. */

{'fraction_non_alphanumeric': 0.20192645361962575, 'fraction_numerical': 0.07871369086439572, 'mean_word_length': 11.680661577608143, 'pattern_counts': {'":': 0, '<': 19, '<?xml version=': 0, '>': 19, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 6, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1826303', 'n_tokens_mistral': 11717, 'n_tokens_neox': 11278, 'n_words': 575}