<commit_before># TCL File Generated by Component Editor 13.0sp1
# Tue Jul 15 11:08:56 CEST 2014
# DO NOT MODIFY


# 
# spi_slave_to_avalon_master "SPI Slave to Avalon Master" v0.1.1
# NTB (ntb.ch.inf) 2014.07.15.11:08:56
# Interface between spi slave and avalon master
# 

# 
# request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1


# 
# module spi_slave_to_avalon_master
# 
set_module_property DESCRIPTION "Interface between spi slave and avalon master"
set_module_property NAME spi_slave_to_avalon_master
set_module_property VERSION 0.1.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP fLink
set_module_property AUTHOR "NTB (ntb.ch.inf)"
set_module_property DISPLAY_NAME "SPI Slave to Avalon Master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL spi_slave_to_avalon_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file spi_slave_to_avalon_master.m.vhd VHDL PATH ../../../../vhdl-library/avalonComponents/spi_slave_to_avalon_master/trunk/src/spi_slave_to_avalon_master.m.vhd TOP_LEVEL_FILE
add_fileset_file spi_slave.m.vhd VHDL PATH ../../../../vhdl-library/functionalBlocks/spi_slave/trunk/src/spi_slave.m.vhd
add_fileset_file flink_definitions.vhd VHDL PATH ../../../../vhdl-library/fLink/core/flink_definitions.vhd


# 
# parameters
# 
add_parameter TRANSFER_WIDTH INTEGER 8
set_parameter_property TRANSFER_WIDTH DEFAULT_VALUE 8
set_parameter_property TRANSFER_WIDTH DISPLAY_NAME TRANSFER_WIDTH
set_parameter_property TRANSFER_WIDTH TYPE INTEGER
set_parameter_property TRANSFER_WIDTH UNITS None
set_parameter_property TRANSFER_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property TRANSFER_WIDTH HDL_PARAMETER true
add_parameter CPOL STD_LOGIC 0
set_parameter_property CPOL DEFAULT_VALUE 0
set_parameter_property CPOL DISPLAY_NAME CPOL
set_parameter_property CPOL TYPE STD_LOGIC<commit_msg>changed paths from old location to new one<commit_after># TCL File Generated by Component Editor 13.0sp1
# Fri Jul 18 11:09:01 CEST 2014
# DO NOT MODIFY


# 
# spi_slave_to_avalon_master "SPI Slave to Avalon Master" v0.1.1
# NTB (ntb.ch.inf) 2014.07.18.11:09:01
# Interface between spi slave and avalon master
# 

# 
# request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1


# 
# module spi_slave_to_avalon_master
# 
set_module_property DESCRIPTION "Interface between spi slave and avalon master"
set_module_property NAME spi_slave_to_avalon_master
set_module_property VERSION 0.1.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP fLink
set_module_property AUTHOR "NTB (<EMAIL>)"
set_module_property DISPLAY_NAME "SPI Slave to Avalon Master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL spi_slave_to_avalon_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file spi_slave_to_avalon_master.m.vhd VHDL PATH spi_slave_to_avalon_master.m.vhd TOP_LEVEL_FILE
add_fileset_file flink_definitions.vhd VHDL PATH ../../../fLink/core/flink_definitions.vhd
add_fileset_file spi_slave.m.vhd VHDL PATH ../../../functionalBlocks/spi_slave/src/spi_slave.m.vhd


# 
# parameters
# 
add_parameter TRANSFER_WIDTH INTEGER 8
set_parameter_property TRANSFER_WIDTH DEFAULT_VALUE 8
set_parameter_property TRANSFER_WIDTH DISPLAY_NAME TRANSFER_WIDTH
set_parameter_property TRANSFER_WIDTH TYPE INTEGER
set_parameter_property TRANSFER_WIDTH UNITS None
set_parameter_property TRANSFER_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property TRANSFER_WIDTH HDL_PARAMETER true
add_parameter CPOL STD_LOGIC 0
set_parameter_property CPOL DEFAULT_VALUE 0
set_parameter_property CPOL DISPLAY_NAME CPOL
set_parameter_property CPOL TYPE STD_LOGIC
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