<commit_before># Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_0 {
  DIN_WIDTH 8 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
  NUM_PORTS 8
}

set prop_list {}
for {set i 0} {$i <= 7} {incr i} {
  lappend prop_list IN${i}_WIDTH 32
}
set_property -dict $prop_list [get_bd_cells concat_0]

for {set i 0} {$i <= 7} {incr i} {
  connect_bd_net [get_bd_pins concat_0/In$i] [get_bd_pins /adc_0/m_axis_tdata]
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_1 {
  NUM_PORTS 16
}

set prop_list {}
for {set i 0} {$i <= 15} {incr i} {
  lappend prop_list IN${i}_WIDTH 1
}
set_property -dict $prop_list [get_bd_cells concat_1]

for {set i 0} {$i <= 15} {incr i} {
  connect_bd_net [get_bd_pins concat_1/In$i] [get_bd_pins /adc_0/m_axis_tvalid]
}

# Create axis_switch
cell xilinx.com:ip:axis_switch:1.1 switch_0 {
  TDATA_NUM_BYTES.VALUE_SRC USER
  TDATA_NUM_BYTES 2
  ROUTING_MODE 1
  NUM_SI 16
  NUM_MI 8
} {
  s_axis_tdata concat_0/dout
  s_axis_tvalid concat_1/dout
  aclk /pll_0/clk_out1
  aresetn /rst_0/peripheral_aresetn
}

set prop_list {}
for {set i 0} {$i <= 7} {incr i} {
  for {set j 0} {$j <= 15} {incr j} {
    if {$i == $j / 2} continue
    lappend prop_list CONFIG.M[format %02d $i]_S[format %02d $j]_CONNECTIVITY 0
  }
}
set_property -dict $prop_list [get_bd_cells switch_0]

unset prop_list

for {set i 0} {$i <= 7} {incr i} {

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 slice_[expr $i + 1] {
    DIN_WIDTH 256 DIN_FROM [expr 32 * $i + 31] DIN_TO [expr 32 * $i] DOUT_WIDTH 32
  }

  # Create axis_constant
  cell pavel-demin:user:axis_constant:1.0 phase_$i {
    AXIS_TDATA_WIDTH 32
  } {
    cfg_data slice_[expr $i + 1]/Dout
    aclk /pll_0/clk_out1
  }

  # Create dds_compiler
  cell xilinx.com:ip:dds_compiler:6.0 dds_$i {
    DDS_CLOCK_RATE 125
    SPURIOUS_FREE_DYNAMIC_RANGE 138
    FREQUENCY_RESOLUTION 0.2
    PHASE_INCREMENT Streaming
    HAS_PHASE_OUT false
    PHASE_WIDTH 30
    OUTPUT_WIDTH 24
    DSP48_USE Minimal
    NEGATIVE_SINE true
  } {
    S_AXIS_PHASE phase_$i/M_AXIS
    aclk /pll_0/clk_out1
  }

}

# Create axis_lfsr
cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
  aclk /pll_0/clk_out1
  aresetn /rst_0/peripheral_aresetn
}

# Create xlconstant
cell xilinx.com:ip:xlconstant:1.1 const_0

for {set i 0} {$i <= 15} {incr i} {

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 adc_slice_$i {
    DIN_WIDTH 128 DIN_FROM [expr 16 * ($i / 2) + 13] DIN_TO [expr 16 * ($i / 2)] DOUT_WIDTH 14
  } {
    Din switch_0/m_axis_tdata
  }

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 dds_slice_$i {
    DIN_WIDTH 48 DIN_FROM [expr 24 * ($i % 2) + 23] DIN_TO [expr 24 * ($i % 2)] DOUT_WIDTH 24
  } {
    Din dds_[expr $i / 2]/m_axis_data_tdata
  }

  cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_$i {
    INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
    A_WIDTH.VALUE_SRC USER
    B_WIDTH.VALUE_SRC USER
    OUTPUT_PROPERTIES User_Defined
    A_WIDTH 24
    B_WIDTH 14
    P_WIDTH 25
  } {
    A dds_slice_$i/Dout
    B adc_slice_$i/Dout
    CARRYIN lfsr_0/m_axis_tdata
    CLK /pll_0/clk_out1
  }

  # Create cic_compiler
  cell xilinx.com:ip:cic_compiler:4.0 cic_$i {
    INPUT_DATA_WIDTH.VALUE_SRC USER
    FILTER_TYPE Decimation
    NUMBER_OF_STAGES 3
    SAMPLE_RATE_CHANGES Fixed
    FIXED_OR_INITIAL_RATE 250
    INPUT_SAMPLE_FREQUENCY 125
    CLOCK_FREQUENCY 125
    INPUT_DATA_WIDTH 24
    QUANTIZATION Truncation
    OUTPUT_DATA_WIDTH 24
    USE_XTREME_DSP_SLICE false
    HAS_DOUT_TREADY true
    HAS_ARESETN true
  } {
    s_axis_data_tdata mult_$i/P
    s_axis_data_tvalid const_0/dout
    aclk /pll_0/clk_out1
    aresetn /rst_0/peripheral_aresetn
  }<commit_msg>set cic_*/NUMBER_OF_STAGES to 6 in sdr_transceiver_wspr/rx.tcl<commit_after># Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_0 {
  DIN_WIDTH 8 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
  NUM_PORTS 8
}

set prop_list {}
for {set i 0} {$i <= 7} {incr i} {
  lappend prop_list IN${i}_WIDTH 32
}
set_property -dict $prop_list [get_bd_cells concat_0]

for {set i 0} {$i <= 7} {incr i} {
  connect_bd_net [get_bd_pins concat_0/In$i] [get_bd_pins /adc_0/m_axis_tdata]
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_1 {
  NUM_PORTS 16
}

set prop_list {}
for {set i 0} {$i <= 15} {incr i} {
  lappend prop_list IN${i}_WIDTH 1
}
set_property -dict $prop_list [get_bd_cells concat_1]

for {set i 0} {$i <= 15} {incr i} {
  connect_bd_net [get_bd_pins concat_1/In$i] [get_bd_pins /adc_0/m_axis_tvalid]
}

# Create axis_switch
cell xilinx.com:ip:axis_switch:1.1 switch_0 {
  TDATA_NUM_BYTES.VALUE_SRC USER
  TDATA_NUM_BYTES 2
  ROUTING_MODE 1
  NUM_SI 16
  NUM_MI 8
} {
  s_axis_tdata concat_0/dout
  s_axis_tvalid concat_1/dout
  aclk /pll_0/clk_out1
  aresetn /rst_0/peripheral_aresetn
}

set prop_list {}
for {set i 0} {$i <= 7} {incr i} {
  for {set j 0} {$j <= 15} {incr j} {
    if {$i == $j / 2} continue
    lappend prop_list CONFIG.M[format %02d $i]_S[format %02d $j]_CONNECTIVITY 0
  }
}
set_property -dict $prop_list [get_bd_cells switch_0]

unset prop_list

for {set i 0} {$i <= 7} {incr i} {

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 slice_[expr $i + 1] {
    DIN_WIDTH 256 DIN_FROM [expr 32 * $i + 31] DIN_TO [expr 32 * $i] DOUT_WIDTH 32
  }

  # Create axis_constant
  cell pavel-demin:user:axis_constant:1.0 phase_$i {
    AXIS_TDATA_WIDTH 32
  } {
    cfg_data slice_[expr $i + 1]/Dout
    aclk /pll_0/clk_out1
  }

  # Create dds_compiler
  cell xilinx.com:ip:dds_compiler:6.0 dds_$i {
    DDS_CLOCK_RATE 125
    SPURIOUS_FREE_DYNAMIC_RANGE 138
    FREQUENCY_RESOLUTION 0.2
    PHASE_INCREMENT Streaming
    HAS_PHASE_OUT false
    PHASE_WIDTH 30
    OUTPUT_WIDTH 24
    DSP48_USE Minimal
    NEGATIVE_SINE true
  } {
    S_AXIS_PHASE phase_$i/M_AXIS
    aclk /pll_0/clk_out1
  }

}

# Create axis_lfsr
cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
  aclk /pll_0/clk_out1
  aresetn /rst_0/peripheral_aresetn
}

# Create xlconstant
cell xilinx.com:ip:xlconstant:1.1 const_0

for {set i 0} {$i <= 15} {incr i} {

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 adc_slice_$i {
    DIN_WIDTH 128 DIN_FROM [expr 16 * ($i / 2) + 13] DIN_TO [expr 16 * ($i / 2)] DOUT_WIDTH 14
  } {
    Din switch_0/m_axis_tdata
  }

  # Create xlslice
  cell xilinx.com:ip:xlslice:1.0 dds_slice_$i {
    DIN_WIDTH 48 DIN_FROM [expr 24 * ($i % 2) + 23] DIN_TO [expr 24 * ($i % 2)] DOUT_WIDTH 24
  } {
    Din dds_[expr $i / 2]/m_axis_data_tdata
  }

  cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_$i {
    INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
    A_WIDTH.VALUE_SRC USER
    B_WIDTH.VALUE_SRC USER
    OUTPUT_PROPERTIES User_Defined
    A_WIDTH 24
    B_WIDTH 14
    P_WIDTH 25
  } {
    A dds_slice_$i/Dout
    B adc_slice_$i/Dout
    CARRYIN lfsr_0/m_axis_tdata
    CLK /pll_0/clk_out1
  }

  # Create cic_compiler
  cell xilinx.com:ip:cic_compiler:4.0 cic_$i {
    INPUT_DATA_WIDTH.VALUE_SRC USER
    FILTER_TYPE Decimation
    NUMBER_OF_STAGES 6
    SAMPLE_RATE_CHANGES Fixed
    FIXED_OR_INITIAL_RATE 250
    INPUT_SAMPLE_FREQUENCY 125
    CLOCK_FREQUENCY 125
    INPUT_DATA_WIDTH 24
    QUANTIZATION Truncation
    OUTPUT_DATA_WIDTH 24
    USE_XTREME_DSP_SLICE false
    HAS_DOUT_TREADY true
    HAS_ARESETN true
  } {
    s_axis_data_tdata mult_$i/P
    s_axis_data_tvalid const_0/dout
    aclk /pll_0/clk_out1
    aresetn /rst_0/peripheral_aresetn
  }
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