<commit_before>// OOK/RSSI RF69 driver

template< typename SPI >
class RF69A : public RF69<SPI> {
public:
    void init (uint8_t id, uint8_t group, int freq);
    uint8_t readRSSI();
    void setThd(uint8_t thd);
    void setBW(uint8_t bw);
    void setFrequency(uint32_t frq);
    void setBitrate(uint32_t br);

    //test functions
    void DataModule(uint8_t module);
    void OOKthdMode(uint8_t thdmode);
    //void readAllRegs();
    //int readStatus();
    //int16_t readAFC();
    //int16_t readFEI(bool start);

    uint8_t myGroup;

protected:
    enum {
        REG_FIFO          = 0x00,
        REG_OPMODE        = 0x01,
        REG_DATAMOD       = 0x02,
        REG_BRMSB         = 0x03,
        REG_FRFMSB        = 0x07,
        REG_PALEVEL       = 0x11,
        REG_OOKPEAK       = 0x1B,
        REG_OOKFIX        = 0x1D,
        REG_AFCFEI        = 0x1E,
        REG_AFCMSB        = 0x1F,
        REG_AFCLSB        = 0x20,
        REG_FEIMSB        = 0x21,
        REG_FEILSB        = 0x22,
        REG_RSSICONFIG    = 0x23,
        REG_RSSIVALUE     = 0x24,
        REG_IRQFLAGS1     = 0x27,
        REG_IRQFLAGS2     = 0x28,
        REG_SYNCVALUE1    = 0x2F,
        REG_SYNCVALUE2    = 0x30,
        REG_NODEADDR      = 0x39,
        REG_BCASTADDR     = 0x3A,
        REG_PKTCONFIG2    = 0x3D,
        REG_AESKEYMSB     = 0x3E,
        
        REG_TEMP1         = 0x4E,
        REG_TEMP2         = 0x4F,

        MODE_SLEEP        = 0<<2,
        MODE_TRANSMIT     = 3<<2,
        MODE_RECEIVE      = 4<<2,

        IRQ1_MODEREADY    = 1<<7,
        IRQ1_RXREADY      = 1<<6,

        IRQ2_FIFOFULL     = 1<<7,
        IRQ2_FIFONOTEMPTY = 1<<6,
        IRQ2_FIFOOVERRUN  = 1<<4,
        IRQ2_PACKETSENT   = 1<<3,
        IRQ2_PAYLOADREADY = 1<<2,
    };
};

// driver implementation

static const uint8_t configRegsOOK [] = {
    0x01, 0x04, // OpMode = standby
    0x02, 0x68, // DataModul = conti mode, ook, no shaping
    0x03, 0x03, // BitRateMsb, 32768bps
    0x04, 0xD1, // BitRateLsb, divider = 32 MHz / 650
    0x0B, 0x20, // AfcCtrl, afclowbetaon
    0x18, 0x81, // LNA fixed highest gain, Z=200ohm
    0x19, 0x40, // RxBw DCC=4%, Man=00b Exp = 0 =>BWOOK=250.0kHz
    0x1B, 0x40, // OOK peak, 0.5dB once/chip
    0x1C, 0x80, // OOK avg thresh /4pi
    0x1D, 0x38, // OOK fixed thresh
    0x1E, 0x00, // No auto AFC
    0x25, 0x80, // Dio 0: RSSI 1: Dclk 2: Data 3: RSSI
    0x26, 0x37, // Dio 5: ModeReady, CLKOUT = OFF
    0x29, 0xFF, // RssiThresh: lowest possible threshold to start receive
    0x2E, 0x00, // SyncConfig = sync off
    //0x58, 0x2D, // Sensitivity boost (TestLNA)
    0x6F, 0x20, // TestDagc ...
    0
};

template< typename SPI >
void RF69A<SPI>::init (uint8_t id, uint8_t group, int freq) {
    RF69<SPI>::init(id, group, freq);
    this->configure(configRegsOOK);
    //clear AFC. Essential for wideband OOK signals. No other way to reset from SW.
    this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
    //this->writeReg(REG_AFCFEI, this->readReg(REG_AFCFEI) | (1 << 1)); //does not work
    myGroup = group;
    this->setMode(MODE_RECEIVE);
}

template< typename SPI >
uint8_t RF69A<SPI>::readRSSI() {
    uint8_t rssi = 0;
    //  if (true)
    //  {
    //    //RSSI trigger not needed if DAGC is in continuous mode
    //    writeReg(REG_RSSICONFIG, RF_RSSI_START);
    //    while ((readReg(REG_RSSICONFIG) & RF_RSSI_DONE) == 0x00); // Wait for RSSI_Ready
    //  }
    rssi = this->readReg(REG_RSSIVALUE);
    //rssi >>= 1;
    return rssi;
}

template< typename SPI >
void RF69A<SPI>::setThd (uint8_t thd) {
    this->writeReg(REG_OOKFIX, thd);
}
template< typename SPI >
void RF69A<SPI>::setBW (uint8_t bw) {
    this->writeReg(0x19, 0x40 | bw);
}
template< typename SPI >
void RF69A<SPI>::setFrequency (uint32_t frq) {
    this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
    RF69<SPI>::setFrequency(frq);

//    // accept any frequency scale as input, including KHz and MHz
//    while (frq < 100000000)
//        frq *= 10;
//    uint64_t frf = ((uint64_t)frq << 8) / (32000000L >> 11);
//    this->writeReg(REG_FRFMSB, frf >> 16);
//    this->writeReg(REG_FRFMSB+1, frf >> 8);
//    this->writeReg(REG_FRFMSB+2, frf);
}

template< typename SPI >
void RF69A<SPI>::setBitrate (uint32_t br) {
    if (br < 489) {
        br = 0xFFFF;
    } else {
        br = 32000000L / br;
    }
    this->writeReg(REG_BRMSB, br >> 8);
    this->writeReg(REG_BRMSB+1, br);
}

template< typename SPI >
void RF69A<SPI>::DataModule(uint8_t module) {
    this->setMode(MODE_SLEEP);
    this->writeReg(REG_DATAMOD, module);
    //FIXME: chThdSleepMilliseconds(400);
    this->setMode(MODE_RECEIVE);
}

template< typename SPI >
void RF69A<SPI>::OOKthdMode(uint8_t thdmode) {
    this->writeReg(REG_OOKPEAK, thdmode);
}


//for debugging
//template< typename SPI >
//void RF69A<SPI>::readAllRegs() {
////    uint8_t regVal;
//
//    printf("     0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  D"
//    "\r\n00: 00");
////    for (uint8_t regAddr = 1; regAddr <= 0x4F; regAddr++) {
////        this->spi.enable();
////        this->spi.transfer(regAddr & 0x7f);   // send address + r/w bit
////        regVal = this->spi.transfer(0);
////        this->spi.disable();
////
////        if (regAddr % 16 == 0)
////        printf("\r\n%02X:", regAddr);
////        printf(" %02x", regVal);
////    }
//    printf("\r\n");
//}
//
//template< typename SPI >
//int RF69A<SPI>::readStatus() {
//    switch (this->mode) {
//    case MODE_RECEIVE:
//    case MODE_TRANSMIT:
//        uint8_t f1 = readReg(REG_IRQFLAGS1);
//        uint8_t f2 = readReg(REG_IRQFLAGS2);
//        if (f1 & 0x08) {
//            //printf(BYTETOBINARYPATTERN, BYTETOBINARY(f1));
//            //printf("  ");
//            //printf(BYTETOBINARYPATTERN, BYTETOBINARY(f2));
//            //printf("  ");
//            //fixthd += 1;
//            //writeReg(0x1D, fixthd);
//            //printf("%02x %02x\r\n", fixthd, readRSSI());
//        }
//        break;
//    default:
//        break;
//    }
//    return 0;
//}
//template< typename SPI >
//int16_t RF69A<SPI>::readFEI(bool start) {
//    int16_t fei = 0;
//      if (start)
//      {
//        this->writeReg(REG_AFCFEI, 1 << 5);
//        while ((this->readReg(REG_AFCFEI) & (1 << 6)) == 0x00); // Wait for RSSI_Ready
//      }
//    fei = this->readReg(REG_FEILSB);
//    fei |= (this->readReg(REG_FEIMSB) << 8);
//    return fei;
//}
//
//template< typename SPI >
//int16_t RF69A<SPI>::readAFC() {
//    int16_t afc = 0;
//    //  if (true)
//    //  {
//    //    //RSSI trigger not needed if DAGC is in continuous mode
//    //    writeReg(REG_RSSICONFIG, RF_RSSI_START);
//    //    while ((readReg(REG_RSSICONFIG) & RF_RSSI_DONE) == 0x00); // Wait for RSSI_Ready
//    //  }
//    afc = this->readReg(REG_AFCLSB);
//    afc |= (this->readReg(REG_AFCMSB) << 8);
//    //reset AFC
////    if (true)
////    {
////        this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
////        //this->writeReg(REG_AFCFEI, this->readReg(REG_AFCFEI) | (1 << 1)); //does not work
////        //while ((this->readReg(REG_AFCFEI) & (1 << 6)) == 0x00); // Wait for RSSI_Ready
////    }
//    return afc;
//}

<commit_msg>Slow-down PEAK-THD decay in view of 32kbps bitrate<commit_after>// OOK/RSSI RF69 driver

template< typename SPI >
class RF69A : public RF69<SPI> {
public:
    void init (uint8_t id, uint8_t group, int freq);
    uint8_t readRSSI();
    void setThd(uint8_t thd);
    void setBW(uint8_t bw);
    void setFrequency(uint32_t frq);
    void setBitrate(uint32_t br);

    //test functions
    void DataModule(uint8_t module);
    void OOKthdMode(uint8_t thdmode);
    //void readAllRegs();
    //int readStatus();
    //int16_t readAFC();
    //int16_t readFEI(bool start);

    uint8_t myGroup;

protected:
    enum {
        REG_FIFO          = 0x00,
        REG_OPMODE        = 0x01,
        REG_DATAMOD       = 0x02,
        REG_BRMSB         = 0x03,
        REG_FRFMSB        = 0x07,
        REG_PALEVEL       = 0x11,
        REG_OOKPEAK       = 0x1B,
        REG_OOKFIX        = 0x1D,
        REG_AFCFEI        = 0x1E,
        REG_AFCMSB        = 0x1F,
        REG_AFCLSB        = 0x20,
        REG_FEIMSB        = 0x21,
        REG_FEILSB        = 0x22,
        REG_RSSICONFIG    = 0x23,
        REG_RSSIVALUE     = 0x24,
        REG_IRQFLAGS1     = 0x27,
        REG_IRQFLAGS2     = 0x28,
        REG_SYNCVALUE1    = 0x2F,
        REG_SYNCVALUE2    = 0x30,
        REG_NODEADDR      = 0x39,
        REG_BCASTADDR     = 0x3A,
        REG_PKTCONFIG2    = 0x3D,
        REG_AESKEYMSB     = 0x3E,
        
        REG_TEMP1         = 0x4E,
        REG_TEMP2         = 0x4F,

        MODE_SLEEP        = 0<<2,
        MODE_TRANSMIT     = 3<<2,
        MODE_RECEIVE      = 4<<2,

        IRQ1_MODEREADY    = 1<<7,
        IRQ1_RXREADY      = 1<<6,

        IRQ2_FIFOFULL     = 1<<7,
        IRQ2_FIFONOTEMPTY = 1<<6,
        IRQ2_FIFOOVERRUN  = 1<<4,
        IRQ2_PACKETSENT   = 1<<3,
        IRQ2_PAYLOADREADY = 1<<2,
    };
};

// driver implementation

static const uint8_t configRegsOOK [] = {
    0x01, 0x04, // OpMode = standby
    0x02, 0x68, // DataModul = conti mode, ook, no shaping
    0x03, 0x03, // BitRateMsb, 32768bps
    0x04, 0xD1, // BitRateLsb, divider = 32 MHz / 650
    0x0B, 0x20, // AfcCtrl, afclowbetaon
    0x18, 0x81, // LNA fixed highest gain, Z=200ohm
    0x19, 0x40, // RxBw DCC=4%, Man=00b Exp = 0 =>BWOOK=250.0kHz
    0x1B, 0x43, // OOK peak, 0.5dB once/8 chips (slowest)
    0x1C, 0x80, // OOK avg thresh /4pi
    0x1D, 0x38, // OOK fixed thresh
    0x1E, 0x00, // No auto AFC
    0x25, 0x80, // Dio 0: RSSI 1: Dclk 2: Data 3: RSSI
    0x26, 0x37, // Dio 5: ModeReady, CLKOUT = OFF
    0x29, 0xFF, // RssiThresh: lowest possible threshold to start receive
    0x2E, 0x00, // SyncConfig = sync off
    //0x58, 0x2D, // Sensitivity boost (TestLNA)
    0x6F, 0x20, // TestDagc ...
    0
};

template< typename SPI >
void RF69A<SPI>::init (uint8_t id, uint8_t group, int freq) {
    RF69<SPI>::init(id, group, freq);
    this->configure(configRegsOOK);
    //clear AFC. Essential for wideband OOK signals. No other way to reset from SW.
    this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
    //this->writeReg(REG_AFCFEI, this->readReg(REG_AFCFEI) | (1 << 1)); //does not work
    myGroup = group;
    this->setMode(MODE_RECEIVE);
}

template< typename SPI >
uint8_t RF69A<SPI>::readRSSI() {
    uint8_t rssi = 0;
    //  if (true)
    //  {
    //    //RSSI trigger not needed if DAGC is in continuous mode
    //    writeReg(REG_RSSICONFIG, RF_RSSI_START);
    //    while ((readReg(REG_RSSICONFIG) & RF_RSSI_DONE) == 0x00); // Wait for RSSI_Ready
    //  }
    rssi = this->readReg(REG_RSSIVALUE);
    //rssi >>= 1;
    return rssi;
}

template< typename SPI >
void RF69A<SPI>::setThd (uint8_t thd) {
    this->writeReg(REG_OOKFIX, thd);
}
template< typename SPI >
void RF69A<SPI>::setBW (uint8_t bw) {
    this->writeReg(0x19, 0x40 | bw);
}
template< typename SPI >
void RF69A<SPI>::setFrequency (uint32_t frq) {
    this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
    RF69<SPI>::setFrequency(frq);

//    // accept any frequency scale as input, including KHz and MHz
//    while (frq < 100000000)
//        frq *= 10;
//    uint64_t frf = ((uint64_t)frq << 8) / (32000000L >> 11);
//    this->writeReg(REG_FRFMSB, frf >> 16);
//    this->writeReg(REG_FRFMSB+1, frf >> 8);
//    this->writeReg(REG_FRFMSB+2, frf);
}

template< typename SPI >
void RF69A<SPI>::setBitrate (uint32_t br) {
    if (br < 489) {
        br = 0xFFFF;
    } else {
        br = 32000000L / br;
    }
    this->writeReg(REG_BRMSB, br >> 8);
    this->writeReg(REG_BRMSB+1, br);
}

template< typename SPI >
void RF69A<SPI>::DataModule(uint8_t module) {
    this->setMode(MODE_SLEEP);
    this->writeReg(REG_DATAMOD, module);
    //FIXME: chThdSleepMilliseconds(400);
    this->setMode(MODE_RECEIVE);
}

template< typename SPI >
void RF69A<SPI>::OOKthdMode(uint8_t thdmode) {
    this->writeReg(REG_OOKPEAK, thdmode);
}


//for debugging
//template< typename SPI >
//void RF69A<SPI>::readAllRegs() {
////    uint8_t regVal;
//
//    printf("     0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  D"
//    "\r\n00: 00");
////    for (uint8_t regAddr = 1; regAddr <= 0x4F; regAddr++) {
////        this->spi.enable();
////        this->spi.transfer(regAddr & 0x7f);   // send address + r/w bit
////        regVal = this->spi.transfer(0);
////        this->spi.disable();
////
////        if (regAddr % 16 == 0)
////        printf("\r\n%02X:", regAddr);
////        printf(" %02x", regVal);
////    }
//    printf("\r\n");
//}
//
//template< typename SPI >
//int RF69A<SPI>::readStatus() {
//    switch (this->mode) {
//    case MODE_RECEIVE:
//    case MODE_TRANSMIT:
//        uint8_t f1 = readReg(REG_IRQFLAGS1);
//        uint8_t f2 = readReg(REG_IRQFLAGS2);
//        if (f1 & 0x08) {
//            //printf(BYTETOBINARYPATTERN, BYTETOBINARY(f1));
//            //printf("  ");
//            //printf(BYTETOBINARYPATTERN, BYTETOBINARY(f2));
//            //printf("  ");
//            //fixthd += 1;
//            //writeReg(0x1D, fixthd);
//            //printf("%02x %02x\r\n", fixthd, readRSSI());
//        }
//        break;
//    default:
//        break;
//    }
//    return 0;
//}
//template< typename SPI >
//int16_t RF69A<SPI>::readFEI(bool start) {
//    int16_t fei = 0;
//      if (start)
//      {
//        this->writeReg(REG_AFCFEI, 1 << 5);
//        while ((this->readReg(REG_AFCFEI) & (1 << 6)) == 0x00); // Wait for RSSI_Ready
//      }
//    fei = this->readReg(REG_FEILSB);
//    fei |= (this->readReg(REG_FEIMSB) << 8);
//    return fei;
//}
//
//template< typename SPI >
//int16_t RF69A<SPI>::readAFC() {
//    int16_t afc = 0;
//    //  if (true)
//    //  {
//    //    //RSSI trigger not needed if DAGC is in continuous mode
//    //    writeReg(REG_RSSICONFIG, RF_RSSI_START);
//    //    while ((readReg(REG_RSSICONFIG) & RF_RSSI_DONE) == 0x00); // Wait for RSSI_Ready
//    //  }
//    afc = this->readReg(REG_AFCLSB);
//    afc |= (this->readReg(REG_AFCMSB) << 8);
//    //reset AFC
////    if (true)
////    {
////        this->writeReg(REG_AFCFEI, (1<<1)); //clear AFC
////        //this->writeReg(REG_AFCFEI, this->readReg(REG_AFCFEI) | (1 << 1)); //does not work
////        //while ((this->readReg(REG_AFCFEI) & (1 << 6)) == 0x00); // Wait for RSSI_Ready
////    }
//    return afc;
//}


{'fraction_non_alphanumeric': 0.16090037515631514, 'fraction_numerical': 0.059677643462553845, 'mean_word_length': 2.0064745196324143, 'pattern_counts': {'":': 0, '<': 149, '<?xml version=': 0, '>': 147, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 2, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2455053', 'n_tokens_mistral': 6368, 'n_tokens_neox': 5822, 'n_words': 1203}