<commit_before># Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# File: C:\Users\silvernegi\Documents\dsdl\lab1\dsdl_lab1.csv
# Generated on: Sat Apr 23 23:52:31 2016

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.

To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Differential Pair
ledg[8],Output,PIN_AC14,8,B8_N0,PIN_AC14,,,,
ledg[7],Output,,,,PIN_F18,,,,
ledg[6],Output,,,,PIN_AK5,,,,
ledg[5],Output,,,,PIN_A12,,,,
ledg[4],Output,,,,PIN_L10,,,,
ledg[3],Output,,,,PIN_C28,,,,
ledg[2],Output,,,,PIN_AH24,,,,
ledg[1],Output,,,,PIN_AF4,,,,
ledg[0],Output,,,,PIN_AK8,,,,
ledr[17],Output,PIN_AJ7,8,B8_N2,PIN_AJ7,,,,
ledr[16],Output,PIN_AD8,8,B8_N3,PIN_AD8,,,,
ledr[15],Output,PIN_AD9,8,B8_N2,PIN_AD9,,,,
ledr[14],Output,PIN_AC11,8,B8_N2,PIN_AC11,,,,
ledr[13],Output,PIN_AB12,8,B8_N1,PIN_AB12,,,,
ledr[12],Output,PIN_AC12,8,B8_N2,PIN_AC12,,,,
ledr[11],Output,PIN_AB13,8,B8_N0,PIN_AB13,,,,
ledr[10],Output,PIN_AC13,8,B8_N1,PIN_AC13,,,,
ledr[9],Output,PIN_AD14,8,B8_N0,PIN_AD14,,,,
ledr[8],Output,PIN_AH3,8,B8_N3,PIN_AH3,,,,
ledr[7],Output,PIN_AJ2,8,B8_N3,PIN_AJ2,,,,
ledr[6],Output,PIN_AJ3,8,B8_N3,PIN_AJ3,,,,
ledr[5],Output,,,,PIN_AE23,,,,
ledr[4],Output,,,,PIN_F20,,,,
ledr[3],Output,,,,PIN_AD22,,,,
ledr[2],Output,,,,PIN_D21,,,,
ledr[1],Output,,,,PIN_AG20,,,,
ledr[0],Output,,,,PIN_P24,,,,
seg7_out[39],Output,PIN_L6,2,B2_N1,PIN_L6,,,,
seg7_out[38],Output,PIN_M2,2,B2_N3,PIN_M2,,,,
seg7_out[37],Output,PIN_M1,2,B2_N3,PIN_M1,,,,
seg7_out[36],Output,PIN_N3,2,B2_N3,PIN_N3,,,,
seg7_out[35],Output,PIN_N2,2,B2_N3,PIN_N2,,,,
seg7_out[34],Output,PIN_P3,2,B2_N3,PIN_P3,,,,
seg7_out[33],Output,PIN_P2,2,B2_N3,PIN_P2,,,,
seg7_out[32],Output,PIN_P1,2,B2_N3,PIN_P1,,,,
seg7_out[31],Output,PIN_M4,2,B2_N3,PIN_M4,,,,
seg7_out[30],Output,PIN_M6,2,B2_N2,PIN_M6,,,,
seg7_out[29],Output,PIN_M7,2,B2_N2,PIN_M7,,,,
seg7_out[28],Output,PIN_M8,2,B2_N1,PIN_M8,,,,
seg7_out[27],Output,PIN_N7,2,B2_N2,PIN_N7,,,,
seg7_out[26],Output,PIN_N10,2,B2_N2,PIN_N10,,,,
seg7_out[25],Output,PIN_P4,2,B2_N3,PIN_P4,,,,
seg7_out[24],Output,PIN_P6,2,B2_N3,PIN_P6,,,,
seg7_out[23],Output,PIN_AC19,7,B7_N1,PIN_AC19,,,,
seg7_out[22],Output,PIN_AE19,7,B7_N1,PIN_AE19,,,,
seg7_out[21],Output,PIN_AB19,7,B7_N1,PIN_AB19,,,,
seg7_out[20],Output,PIN_AB18,7,B7_N1,PIN_AB18,,,,
seg7_out[19],Output,PIN_AG4,8,B8_N3,PIN_AG4,,,,
seg7_out[18],Output,PIN_AH5,8,B8_N3,PIN_AH5,,,,
seg7_out[17],Output,PIN_AF7,8,B8_N3,PIN_AF7,,,,
seg7_out[16],Output,PIN_AE7,8,B8_N3,PIN_AE7,,,,
seg7_out[15],Output,PIN_AC17,7,B7_N2,PIN_AC17,,,,
seg7_out[14],Output,PIN_AD17,7,B7_N2,PIN_AD17,,,,
seg7_out[13],Output,PIN_AF17,7,B7_N2,PIN_AF17,,,,
seg7_out[12],Output,PIN_AE17,7,B7_N3,PIN_AE17,,,,
seg7_out[11],Output,PIN_AG16,7,B7_N3,PIN_AG16,,,,
seg7_out[10],Output,PIN_AF16,7,B7_N3,PIN_AF16,,,,
seg7_out[9],Output,PIN_AE16,7,B7_N3,PIN_AE16,,,,
seg7_out[8],Output,PIN_AG13,8,B8_N0,PIN_AG13,,,,
seg7_out[7],Output,PIN_AF12,8,B8_N1,PIN_AF12,,,,
seg7_out[6],Output,PIN_AD12,8,B8_N1,PIN_AD12,,,,
seg7_out[5],Output,PIN_AD11,8,B8_N2,PIN_AD11,,,,
seg7_out[4],Output,PIN_AF10,8,B8_N2,PIN_AF10,,,,
seg7_out[3],Output,PIN_AD10,8,B8_N2,PIN_AD10,,,,
seg7_out[2],Output,PIN_AH9,8,B8_N1,PIN_AH9,,,,
seg7_out[1],Output,PIN_AF9,8,B8_N2,PIN_AF9,,,,
seg7_out[0],Output,PIN_AE8,8,B8_N3,PIN_AE8,,,,
sw[17],Input,PIN_L8,2,B2_N1,PIN_L8,,,,
sw[16],Input,PIN_L7,2,B2_N1,PIN_L7,,,,
sw[15],Input,PIN_L4,2,B2_N2,PIN_L4,,,,
sw[14],Input,PIN_L5,2,B2_N1,PIN_L5,,,,
sw[13],Input,PIN_T9,1,B1_N0,PIN_T9,,,,
sw[12],Input,PIN_U9,1,B1_N0,PIN_U9,,,,
sw[11],Input,PIN_V10,1,B1_N1,PIN_V10,,,,
sw[10],Input,PIN_W5,1,B1_N1,PIN_W5,,,,
sw[9],Input,PIN_AE27,6,B6_N2,PIN_AE27,,,,
sw[8],Input,PIN_AD24,6,B6_N3,PIN_AD24,,,,
sw[7],Input,PIN_AD25,6,B6_N3,PIN_AD25,,,,
sw[6],Input,PIN_AC23,6,B6_N3,PIN_AC23,,,,
sw[5],Input,,,,PIN_D8,,,,
sw[4],Input,,,,PIN_E22,,,,
sw[3],Input,,,,PIN_F29,,,,
sw[2],Input,PIN_AB25,6,B6_N2,PIN_AB25,,,,
sw[1],Input,PIN_AB26,6,B6_N2,PIN_AB26,,,,
sw[0],Input,PIN_AA23,6,B6_N2,PIN_AA23,,,,
<commit_msg>complete some pins<commit_after># Copyright (C) 1991-2013 Altera Corporation,,,,,,,,,
# Your use of Altera Corporation's design tools, logic functions ,,,,,,,,
# and other software and tools, and its AMPP partner logic ,,,,,,,,
# functions, and any output files from any of the foregoing ,,,,,,,,
# (including device programming or simulation files), and any ,,,,,,,,
# associated documentation or information are expressly subject ,,,,,,,,,
# to the terms and conditions of the Altera Program License ,,,,,,,,,
# Subscription Agreement, Altera MegaCore Function License ,,,,,,,,
# Agreement, or other applicable license agreement, including, ,,,,,,
# without limitation, that your use is for the sole purpose of ,,,,,,,,
# programming logic devices manufactured by Altera and sold by ,,,,,,,,,
# Altera or its authorized distributors.  Please refer to the ,,,,,,,,,
# applicable agreement for further details.,,,,,,,,,
,,,,,,,,,
# Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition,,,,,,,,,
# File: C:\Users\silvernegi\Documents\dsdl\lab1\dsdl_lab1.csv,,,,,,,,,
# Generated on: Sat Apr 23 23:52:31 2016,,,,,,,,,
,,,,,,,,,
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.,,,,,,,,,
,,,,,,,,,
To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Differential Pair
ledg[8],Output,PIN_AC14,8,B8_N0,PIN_AC14,,,,
ledg[7],Output,,,,PIN_F18,,,,
ledg[6],Output,,,,PIN_AK5,,,,
ledg[5],Output,,,,PIN_A12,,,,
ledg[4],Output,,,,PIN_L10,,,,
ledg[3],Output,,,,PIN_C28,,,,
ledg[2],Output,,,,PIN_AH24,,,,
ledg[1],Output,,,,PIN_AF4,,,,
ledg[0],Output,,,,PIN_AK8,,,,
ledr[17],Output,PIN_AJ7,8,B8_N2,PIN_AJ7,,,,
ledr[16],Output,PIN_AD8,8,B8_N3,PIN_AD8,,,,
ledr[15],Output,PIN_AD9,8,B8_N2,PIN_AD9,,,,
ledr[14],Output,PIN_AC11,8,B8_N2,PIN_AC11,,,,
ledr[13],Output,PIN_AB12,8,B8_N1,PIN_AB12,,,,
ledr[12],Output,PIN_AC12,8,B8_N2,PIN_AC12,,,,
ledr[11],Output,PIN_AB13,8,B8_N0,PIN_AB13,,,,
ledr[10],Output,PIN_AC13,8,B8_N1,PIN_AC13,,,,
ledr[9],Output,PIN_AD14,8,B8_N0,PIN_AD14,,,,
ledr[8],Output,PIN_AH3,8,B8_N3,PIN_AH3,,,,
ledr[7],Output,PIN_AJ2,8,B8_N3,PIN_AJ2,,,,
ledr[6],Output,PIN_AJ3,8,B8_N3,PIN_AJ3,,,,
ledr[5],Output,PIN_AH4,,,PIN_AE23,,,,
ledr[4],Output,PIN_AK3,,,PIN_F20,,,,
ledr[3],Output,PIN_AJ4,,,PIN_AD22,,,,
ledr[2],Output,PIN_AJ5,,,PIN_D21,,,,
ledr[1],Output,PIN_AK5,,,PIN_AG20,,,,
ledr[0],Output,PIN_AJ6,,,PIN_P24,,,,
seg7_out[39],Output,PIN_L6,2,B2_N1,PIN_L6,,,,
seg7_out[38],Output,PIN_M2,2,B2_N3,PIN_M2,,,,
seg7_out[37],Output,PIN_M1,2,B2_N3,PIN_M1,,,,
seg7_out[36],Output,PIN_N3,2,B2_N3,PIN_N3,,,,
seg7_out[35],Output,PIN_N2,2,B2_N3,PIN_N2,,,,
seg7_out[34],Output,PIN_P3,2,B2_N3,PIN_P3,,,,
seg7_out[33],Output,PIN_P2,2,B2_N3,PIN_P2,,,,
seg7_out[32],Output,PIN_P1,2,B2_N3,PIN_P1,,,,
seg7_out[31],Output,PIN_M4,2,B2_N3,PIN_M4,,,,
seg7_out[30],Output,PIN_M6,2,B2_N2,PIN_M6,,,,
seg7_out[29],Output,PIN_M7,2,B2_N2,PIN_M7,,,,
seg7_out[28],Output,PIN_M8,2,B2_N1,PIN_M8,,,,
seg7_out[27],Output,PIN_N7,2,B2_N2,PIN_N7,,,,
seg7_out[26],Output,PIN_N10,2,B2_N2,PIN_N10,,,,
seg7_out[25],Output,PIN_P4,2,B2_N3,PIN_P4,,,,
seg7_out[24],Output,PIN_P6,2,B2_N3,PIN_P6,,,,
seg7_out[23],Output,PIN_AC19,7,B7_N1,PIN_AC19,,,,
seg7_out[22],Output,PIN_AE19,7,B7_N1,PIN_AE19,,,,
seg7_out[21],Output,PIN_AB19,7,B7_N1,PIN_AB19,,,,
seg7_out[20],Output,PIN_AB18,7,B7_N1,PIN_AB18,,,,
seg7_out[19],Output,PIN_AG4,8,B8_N3,PIN_AG4,,,,
seg7_out[18],Output,PIN_AH5,8,B8_N3,PIN_AH5,,,,
seg7_out[17],Output,PIN_AF7,8,B8_N3,PIN_AF7,,,,
seg7_out[16],Output,PIN_AE7,8,B8_N3,PIN_AE7,,,,
seg7_out[15],Output,PIN_AC17,7,B7_N2,PIN_AC17,,,,
seg7_out[14],Output,PIN_AD17,7,B7_N2,PIN_AD17,,,,
seg7_out[13],Output,PIN_AF17,7,B7_N2,PIN_AF17,,,,
seg7_out[12],Output,PIN_AE17,7,B7_N3,PIN_AE17,,,,
seg7_out[11],Output,PIN_AG16,7,B7_N3,PIN_AG16,,,,
seg7_out[10],Output,PIN_AF16,7,B7_N3,PIN_AF16,,,,
seg7_out[9],Output,PIN_AE16,7,B7_N3,PIN_AE16,,,,
seg7_out[8],Output,PIN_AG13,8,B8_N0,PIN_AG13,,,,
seg7_out[7],Output,PIN_AF12,8,B8_N1,PIN_AF12,,,,
seg7_out[6],Output,PIN_AD12,8,B8_N1,PIN_AD12,,,,
seg7_out[5],Output,PIN_AD11,8,B8_N2,PIN_AD11,,,,
seg7_out[4],Output,PIN_AF10,8,B8_N2,PIN_AF10,,,,
seg7_out[3],Output,PIN_AD10,8,B8_N2,PIN_AD10,,,,
seg7_out[2],Output,PIN_AH9,8,B8_N1,PIN_AH9,,,,
seg7_out[1],Output,PIN_AF9,8,B8_N2,PIN_AF9,,,,
seg7_out[0],Output,PIN_AE8,8,B8_N3,PIN_AE8,,,,
sw[17],Input,PIN_L8,2,B2_N1,PIN_L8,,,,
sw[16],Input,PIN_L7,2,B2_N1,PIN_L7,,,,
sw[15],Input,PIN_L4,2,B2_N2,PIN_L4,,,,
sw[14],Input,PIN_L5,2,B2_N1,PIN_L5,,,,
sw[13],Input,PIN_T9,1,B1_N0,PIN_T9,,,,
sw[12],Input,PIN_U9,1,B1_N0,PIN_U9,,,,
sw[11],Input,PIN_V10,1,B1_N1,PIN_V10,,,,
sw[10],Input,PIN_W5,1,B1_N1,PIN_W5,,,,
sw[9],Input,PIN_AE27,6,B6_N2,PIN_AE27,,,,
sw[8],Input,PIN_AD24,6,B6_N3,PIN_AD24,,,,
sw[7],Input,PIN_AD25,6,B6_N3,PIN_AD25,,,,
sw[6],Input,PIN_AC23,6,B6_N3,PIN_AC23,,,,
sw[5],Input,PIN_AC24,,,PIN_D8,,,,
sw[4],Input,PIN_AC26,,,PIN_E22,,,,
sw[3],Input,PIN_AC27,,,PIN_F29,,,,
sw[2],Input,PIN_AB25,6,B6_N2,PIN_AB25,,,,
sw[1],Input,PIN_AB26,6,B6_N2,PIN_AB26,,,,
sw[0],Input,PIN_AA23,6,B6_N2,PIN_AA23,,,,

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{'dir': 'git-commits-cleaned', 'id': '6842687', 'n_tokens_mistral': 5378, 'n_tokens_neox': 5172, 'n_words': 490}