<commit_before>/*
 * Copyright 2014, NICTA
 *
 * This software may be distributed and modified according to the terms of
 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
 * See "LICENSE_BSD2.txt" for details.
 *
 * @TAG(NICTA_BSD)
 */

#ifndef __ARCH_ARMV7A_SEL4BENCH_H__
#define __ARCH_ARMV7A_SEL4BENCH_H__

#include "sel4bench_private_armv7a.h"

//expose common event definitions
#define SEL4BENCH_EVENT_CACHE_L1I_MISS      SEL4BENCH_ARMV7A_EVENT_CACHE_L1I_MISS
#define SEL4BENCH_EVENT_CACHE_L1D_MISS      SEL4BENCH_ARMV7A_EVENT_CACHE_L1D_MISS
#define SEL4BENCH_EVENT_TLB_L1I_MISS        SEL4BENCH_ARMV7A_EVENT_TLB_L1I_MISS
#define SEL4BENCH_EVENT_TLB_L1D_MISS        SEL4BENCH_ARMV7A_EVENT_TLB_L1D_MISS
#define SEL4BENCH_EVENT_MEMORY_ACCESS       SEL4BENCH_ARMV7A_EVENT_MEMORY_ACCESS
#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION SEL4BENCH_ARMV7A_EVENT_EXECUTE_INSTRUCTION
#define SEL4BENCH_EVENT_BRANCH_MISPREDICT   SEL4BENCH_ARMV7A_EVENT_BRANCH_MISPREDICT


//utility macros
#ifndef BIT
#define BIT(x) (1ul << (x))
#endif
#define MODIFY_PMCR(op, val) sel4bench_private_write_pmcr(sel4bench_private_read_pmcr() op (val))

/* Silence warnings about including the following functions when seL4_DebugRun
 * is not enabled when we are not calling them. If we actually call these
 * functions without seL4_DebugRun enabled, we'll get a link failure, so this
 * should be OK.
 */
void seL4_DebugRun(void (* userfn) (void *), void* userarg);

static FASTFN void sel4bench_init() {
	//do kernel-mode PMC init
#ifndef CONFIG_EXPORT_PMU_USER
	seL4_DebugRun(&sel4bench_private_init, NULL);
#endif

	//ensure all counters are in the stopped state
	sel4bench_private_write_cntenc(-1);

	//Clear div 64 flag
	MODIFY_PMCR(&, ~SEL4BENCH_ARMV7A_PMCR_DIV64);

    //Reset all counters
	MODIFY_PMCR(|, SEL4BENCH_ARMV7A_PMCR_RESET_ALL | SEL4BENCH_ARMV7A_PMCR_RESET_CCNT);

	//Enable counters globally.
	MODIFY_PMCR(|, SEL4BENCH_ARMV7A_PMCR_ENABLE);

	//start CCNT
	sel4bench_private_write_cntens(BIT(SEL4BENCH_ARMV7A_COUNTER_CCNT));
}

static FASTFN void sel4bench_destroy() {
	//stop all performance counters
	sel4bench_private_write_cntenc(-1);

	//Disable counters globally.
	MODIFY_PMCR(&, ~SEL4BENCH_ARMV7A_PMCR_ENABLE);

	//disable user-mode performance-counter access
#ifndef CONFIG_EXPORT_PMU_USER
	seL4_DebugRun(&sel4bench_private_deinit, NULL);
#endif
}

static FASTFN seL4_Word sel4bench_get_num_counters() {
#ifdef CORTEX_A8
	return 4;
#else //CORTEX_A8
	return SEL4BENCH_ARMV7A_PMCR_N(sel4bench_private_read_pmcr());
#endif //CORTEX_A8
}

static FASTFN sel4bench_counter_t sel4bench_get_cycle_count() {
	uint32_t enable_word = sel4bench_private_read_cntens(); //store running state<commit_msg>When building the hyp kernel, setup instruction counters with PL2 cycles included by default<commit_after>/*
 * Copyright 2014, NICTA
 *
 * This software may be distributed and modified according to the terms of
 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
 * See "LICENSE_BSD2.txt" for details.
 *
 * @TAG(NICTA_BSD)
 */

#ifndef __ARCH_ARMV7A_SEL4BENCH_H__
#define __ARCH_ARMV7A_SEL4BENCH_H__

#include "sel4bench_private_armv7a.h"

//expose common event definitions
#define SEL4BENCH_EVENT_CACHE_L1I_MISS      SEL4BENCH_ARMV7A_EVENT_CACHE_L1I_MISS
#define SEL4BENCH_EVENT_CACHE_L1D_MISS      SEL4BENCH_ARMV7A_EVENT_CACHE_L1D_MISS
#define SEL4BENCH_EVENT_TLB_L1I_MISS        SEL4BENCH_ARMV7A_EVENT_TLB_L1I_MISS
#define SEL4BENCH_EVENT_TLB_L1D_MISS        SEL4BENCH_ARMV7A_EVENT_TLB_L1D_MISS
#define SEL4BENCH_EVENT_MEMORY_ACCESS       SEL4BENCH_ARMV7A_EVENT_MEMORY_ACCESS
#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION SEL4BENCH_ARMV7A_EVENT_EXECUTE_INSTRUCTION
#define SEL4BENCH_EVENT_BRANCH_MISPREDICT   SEL4BENCH_ARMV7A_EVENT_BRANCH_MISPREDICT


//utility macros
#ifndef BIT
#define BIT(x) (1ul << (x))
#endif
#define MODIFY_PMCR(op, val) sel4bench_private_write_pmcr(sel4bench_private_read_pmcr() op (val))

/* Silence warnings about including the following functions when seL4_DebugRun
 * is not enabled when we are not calling them. If we actually call these
 * functions without seL4_DebugRun enabled, we'll get a link failure, so this
 * should be OK.
 */
void seL4_DebugRun(void (* userfn) (void *), void* userarg);

static FASTFN void sel4bench_init() {
	//do kernel-mode PMC init
#ifndef CONFIG_EXPORT_PMU_USER
	seL4_DebugRun(&sel4bench_private_init, NULL);
#endif

	//ensure all counters are in the stopped state
	sel4bench_private_write_cntenc(-1);

	//Clear div 64 flag
	MODIFY_PMCR(&, ~SEL4BENCH_ARMV7A_PMCR_DIV64);

    //Reset all counters
	MODIFY_PMCR(|, SEL4BENCH_ARMV7A_PMCR_RESET_ALL | SEL4BENCH_ARMV7A_PMCR_RESET_CCNT);

	//Enable counters globally.
	MODIFY_PMCR(|, SEL4BENCH_ARMV7A_PMCR_ENABLE);

#ifdef ARM_HYP
	// Select instruction count incl. PL2 by default */
	sel4bench_private_write_pmnxsel(0x1f);
	sel4bench_private_write_evtsel(BIT(27));
#endif
	//start CCNT
	sel4bench_private_write_cntens(BIT(SEL4BENCH_ARMV7A_COUNTER_CCNT));
}

static FASTFN void sel4bench_destroy() {
	//stop all performance counters
	sel4bench_private_write_cntenc(-1);

	//Disable counters globally.
	MODIFY_PMCR(&, ~SEL4BENCH_ARMV7A_PMCR_ENABLE);

	//disable user-mode performance-counter access
#ifndef CONFIG_EXPORT_PMU_USER
	seL4_DebugRun(&sel4bench_private_deinit, NULL);
#endif
}

static FASTFN seL4_Word sel4bench_get_num_counters() {
#ifdef CORTEX_A8
	return 4;
#else //CORTEX_A8
	return SEL4BENCH_ARMV7A_PMCR_N(sel4bench_private_read_pmcr());
#endif //CORTEX_A8
}

static FASTFN sel4bench_counter_t sel4bench_get_cycle_count() {
	uint32_t enable_word = sel4bench_private_read_cntens(); //store running state
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