<commit_before>/* Copyright 2019 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* Cometlake chipset power control module for Chrome EC */

#include "chipset.h"
#include "console.h"
#include "gpio.h"
#include "intel_x86.h"
#include "power.h"
#include "power_button.h"
#include "task.h"
#include "timer.h"

/* Console output macros */
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)

/* Power signals list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
	[X86_SLP_S0_DEASSERTED] = {
		GPIO_PCH_SLP_S0_L,
		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
		"SLP_S0_DEASSERTED",
	},
	[X86_SLP_S3_DEASSERTED] = {
		SLP_S3_SIGNAL_L,
		POWER_SIGNAL_ACTIVE_HIGH,
		"SLP_S3_DEASSERTED",
	},
	[X86_SLP_S4_DEASSERTED] = {
		SLP_S4_SIGNAL_L,
		POWER_SIGNAL_ACTIVE_HIGH,
		"SLP_S4_DEASSERTED",
	},
	[X86_RSMRST_L_PGOOD] = {
		GPIO_RSMRST_L_PGOOD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"RSMRST_L_PGOOD",
	},
	[PP5000_A_PGOOD] = {
		GPIO_PP5000_A_PG_OD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"PP5000_A_PGOOD",
	},
	[ALL_SYS_PGOOD] = {
		GPIO_PG_EC_ALL_SYS_PWRGD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"ALL_SYS_PWRGD",
	},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);

static int forcing_shutdown;  /* Forced shutdown in progress? */

void chipset_force_shutdown(enum chipset_shutdown_reason reason)
{
	int timeout_ms = 50;

	CPRINTS("%s(%d)", __func__, reason);
	report_ap_reset(reason);

	/* Turn off RSMRST_L to meet tPCH12 */
	gpio_set_level(GPIO_EC_PCH_RSMRST_L, 0);

	/* Turn off A (except PP5000_A) rails*/
	gpio_set_level(GPIO_EN_A_RAILS, 0);

#ifdef CONFIG_POWER_PP5000_CONTROL
	/* Issue a request to turn off the rail. */
	power_5v_enable(task_get_current(), 0);
#else
	/* Turn off PP5000_A rail */
	gpio_set_level(GPIO_EN_PP5000_A, 0);
#endif

	/* Need to wait a min of 10 msec before check for power good */
	msleep(10);

	/*
	 * TODO(b/122264541): Replace this wait with
	 * power_wait_signals_timeout()
	 */
	/* Now wait for PP5000_A and RSMRST_L to go low */
	while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
		power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
		msleep(1);
		timeout_ms--;
	};

	if (!timeout_ms)
		CPRINTS("PP5000_A rail still up!  Assuming G3.");
}

void chipset_handle_espi_reset_assert(void)
{
	/*<commit_msg>cometlake: Remove TODO comment from chipset_force_shutdown<commit_after>/* Copyright 2019 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* Cometlake chipset power control module for Chrome EC */

#include "chipset.h"
#include "console.h"
#include "gpio.h"
#include "intel_x86.h"
#include "power.h"
#include "power_button.h"
#include "task.h"
#include "timer.h"

/* Console output macros */
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)

/* Power signals list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
	[X86_SLP_S0_DEASSERTED] = {
		GPIO_PCH_SLP_S0_L,
		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
		"SLP_S0_DEASSERTED",
	},
	[X86_SLP_S3_DEASSERTED] = {
		SLP_S3_SIGNAL_L,
		POWER_SIGNAL_ACTIVE_HIGH,
		"SLP_S3_DEASSERTED",
	},
	[X86_SLP_S4_DEASSERTED] = {
		SLP_S4_SIGNAL_L,
		POWER_SIGNAL_ACTIVE_HIGH,
		"SLP_S4_DEASSERTED",
	},
	[X86_RSMRST_L_PGOOD] = {
		GPIO_RSMRST_L_PGOOD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"RSMRST_L_PGOOD",
	},
	[PP5000_A_PGOOD] = {
		GPIO_PP5000_A_PG_OD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"PP5000_A_PGOOD",
	},
	[ALL_SYS_PGOOD] = {
		GPIO_PG_EC_ALL_SYS_PWRGD,
		POWER_SIGNAL_ACTIVE_HIGH,
		"ALL_SYS_PWRGD",
	},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);

static int forcing_shutdown;  /* Forced shutdown in progress? */

void chipset_force_shutdown(enum chipset_shutdown_reason reason)
{
	int timeout_ms = 50;

	CPRINTS("%s(%d)", __func__, reason);
	report_ap_reset(reason);

	/* Turn off RSMRST_L to meet tPCH12 */
	gpio_set_level(GPIO_EC_PCH_RSMRST_L, 0);

	/* Turn off A (except PP5000_A) rails*/
	gpio_set_level(GPIO_EN_A_RAILS, 0);

#ifdef CONFIG_POWER_PP5000_CONTROL
	/* Issue a request to turn off the rail. */
	power_5v_enable(task_get_current(), 0);
#else
	/* Turn off PP5000_A rail */
	gpio_set_level(GPIO_EN_PP5000_A, 0);
#endif

	/* Need to wait a min of 10 msec before check for power good */
	msleep(10);

	/* Now wait for PP5000_A and RSMRST_L to go low */
	while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
		power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
		msleep(1);
		timeout_ms--;
	};

	if (!timeout_ms)
		CPRINTS("PP5000_A rail still up!  Assuming G3.");
}

void chipset_handle_espi_reset_assert(void)
{
	/*
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