<commit_before>================
Welcome to SyDPy
================

SyDPy (**System Design in Python**) aims to become an alternative to SystemVerilog and 
[SystemC]: <http://www.accellera.org/downloads/standards/systemc> by providing the necessary tools to cover tasks of 
HDL design from system architecture design to HDL synthesis.

SyDPy comprises an event based simulator and various classes for describing and simulating a system, all written in Python. 
This allows an easy extension of the SyDPy with additional user classes or existing Python libraries

SyDPy was written with design reuse and iterable nature of the design process in mind. Smart channels enable cosimulation of 
module architectures written on various abstraction levels (of timing and functionality), without the need of explicit 
interface converters in the design. Modules with higher levels of abstraction can then serve as model checkers for lower
level modules. 

SyDPy features:
===============
 - RTL and TLM cosimulation
 - Smart channels for information exchange between various interfaces
 - Global simulator configuration for test setup
 - Basic randomization, sequencing and scoreboarding supported
 - Automatic model checking between different module architectures
 - Extendible simulator kernel
 
Soon available:
===============
 - Verilog cosimulation using [Verilator]: <http://www.veripool.org/wiki/verilator>
 - Python to Verilog conversion
 - Constrained-random verification using [SystemC Verification]: <http://www.accellera.org/downloads/standards/systemc> library
 
Getting started
===============

Installation
------------

Install SyDPy using pip::

  pip install sydpy

Install SyDPy using easy_install::

  easy_install sydpy
  
Install SyDPy from source::

  python setup.py install

Read the documentation
----------------------

Read the [SyDPy documentation]: <http://sydpy.readthedocs.org/en/latest/>

Checkout the examples
---------------------

Examples are located in the [examples]: <https://github.com/bogdanvuk/sydpy/tree/master/examples> repository folder.

Get involved
------------

Pull your copy from [github repository]: <https://github.com/bogdanvuk/sydpy>


 <commit_msg>- Some more README.md markup addaptations<commit_after>================
Welcome to SyDPy
================

SyDPy (**System Design in Python**) aims to become an alternative to SystemVerilog and 
[SystemC](<http://www.accellera.org/downloads/standards/systemc>) by providing the necessary tools to cover tasks of 
HDL design from system architecture design to HDL synthesis.

SyDPy comprises an event based simulator and various classes for describing and simulating a system, all written in Python. 
This allows an easy extension of the SyDPy with additional user classes or existing Python libraries

SyDPy was written with design reuse and iterable nature of the design process in mind. Smart channels enable cosimulation of 
module architectures written on various abstraction levels (of timing and functionality), without the need of explicit 
interface converters in the design. Modules with higher levels of abstraction can then serve as model checkers for lower
level modules. 

SyDPy features:
===============
 - RTL and TLM cosimulation
 - Smart channels for information exchange between various interfaces
 - Global simulatsor configuration for test setup
 - Basic randomization, sequencing and scoreboarding supported
 - Automatic model checking between different module architectures
 - Extendible simulator kernel
 
Soon available:
===============
 - Verilog cosimulation using [Verilator](<http://www.veripool.org/wiki/verilator>)
 - Python to Verilog conversion
 - Constrained-random verification using [SystemC Verification]( <http://www.accellera.org/downloads/standards/systemc>) library
 
Getting started
===============

Installation
------------

Install SyDPy using pip::

  `pip install sydpy`

Install SyDPy using easy_install::

  `easy_install sydpy`
  
Install SyDPy from source::

  `python setup.py install`

Read the documentation
----------------------

Read the [SyDPy documentation](<http://sydpy.readthedocs.org/en/latest/>)

Checkout the examples
---------------------

Examples are located in the [examples](<https://github.com/bogdanvuk/sydpy/tree/master/examples>) repository folder.

Get involved
------------

Pull your copy from [github repository](<https://github.com/bogdanvuk/sydpy>)


 
{'fraction_non_alphanumeric': 0.1201988251242657, 'fraction_numerical': 0.0, 'mean_word_length': 4.2143698468786805, 'pattern_counts': {'":': 0, '<': 15, '<?xml version=': 0, '>': 15, 'https://': 4, 'lorem ipsum': 0, 'www.': 6, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 4, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1130331', 'n_tokens_mistral': 1162, 'n_tokens_neox': 1081, 'n_words': 470}