Justia Patents Semiconductor Device Manufacturing: Process Patents Coating With Electrically Or Thermally Conductive Material Patents To Form Ohmic Contact To Semiconductive Material Patents Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Patents Including Use Of Antireflective Layer Patents (Class 438/636)
Including Use Of Antireflective Layer Patents (Class 438/636)
Semiconductor devices including active regions in RAM areas with deposition determined pitch
Patent number: 11257672
Abstract: The present disclosure provides manufacturing techniques in which the layout pattern of a RAM cell may be obtained on the basis of a single lithography step, followed by a sequence of two deposition processes, thereby resulting in a self-aligned mechanism for providing the most critical lateral dimensions for active regions. In this manner, the smallest pitch of approximately 80 nm and even less may be accomplished with superior device uniformity, while at the same time reducing overall manufacturing complexity.
Date of Patent: February 22, 2022
Assignee: GlobalFoundries U.S. Inc.
Inventor: Nan Wu
Manufacturing method of semiconductor chip, and kit
Abstract: The present invention provides a manufacturing method of a semiconductor chip, in which the manufacturing yield is excellent, and a kit. According to the present invention, a manufacturing method of a semiconductor chip includes Process 1 of forming an insulating layer on a base material, Process 2 of forming a patterned resist film on the insulating layer, Process 3 of forming the insulating layer having an opening portion by etching the insulating layer with the patterned resist film as a mask, Process 4 of removing the patterned resist film, Process 5 of filling the opening portion of the insulating layer with metal, and Process 6 of performing chemical-mechanical polishing on the insulating layer filled with metal.
Filed: March 29, 2019
Date of Patent: March 9, 2021
Assignee: FUJIFILM Corporation
Inventor: Tetsuya Kamimura
Method for forming semiconductor device structure with fine line pitch and fine end-to-end space
Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.
Date of Patent: June 9, 2020
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Hung-Hao Chen, Yu-Shu Chen, Yu-Cheng Liu
Atomically precise surface engineering for producing imagers
Abstract: High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.
Date of Patent: January 21, 2020
Assignee: California Institute of Technology
Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Michael E. Hoenk
Etching and structures formed thereby
Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.
Date of Patent: April 23, 2019
Inventors: Kuan-Wei Huang, Yu-Yu Chen, Chia-Nan Lin
Semiconductor device and manufacturing method thereof
Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
Filed: March 7, 2016
Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
Method of forming interconnect structures by self-aligned approach
Abstract: A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material.
Date of Patent: May 23, 2017
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors: Chih-Hao Chen, Ta-Ching Yu
Semiconductor device and semiconductor device manufacturing method using patterning and dry etching
Abstract: A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas.
Filed: December 14, 2015
Assignee: CANON KABUSHIKI KAISHA
Inventors: Koji Hara, Nobutaka Ukigaya, Takeshi Aoki, Yasuhiro Kawabata, Junya Tamaki, Norihiko Nakata, Satoshi Ogawa
Method of forming thin film of semiconductor device
Abstract: Provided is a method of forming a thin film of a semiconductor device. The method includes forming a precursor layer on a surface of a substrate by supplying a precursor gas into a chamber, discharging the precursor gas remaining in the chamber to an outside of the chamber by supplying a purge gas into the chamber, supplying a reactant gas into the chamber, generating plasma based on the reactant gas, forming a thin film by a chemical reaction between plasma and the precursor layer and radiating extreme ultraviolet (EUV) light into the chamber, and discharging the reactant gas and the plasma remaining in the chamber by supplying a purge gas into the chamber.
Date of Patent: February 7, 2017
Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior University
Inventors: Sam Hyung Sam Kim, Andrei Teodor Iancu, Friedrich B. Prinz, Michael C. Langston, Peter Schindler, Ki-Hyun Kim, Stephen P. Walch, Takane Usui
Double self aligned via patterning
Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
Date of Patent: May 3, 2016
Assignees: International Business Machines Corporation, Global Foundries Inc.
Inventors: Hsueh-Chung Chen, Yongan Xu, Yunpeng Yin, Ailian Zhao
Semiconductor device and method for manufacturing the same
Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
Date of Patent: November 24, 2015
Assignee: Semiconductor Energy Laboratory Co., Ltd.
Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
Unlocking layer and method
Abstract: A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a polymer resin which has repeating units within it. At least one of the repeating units comprises a locked unit which has a cyclic structure and a lock within the unit. After the anti-reflective layer has been applied and baked, irregularities such as voids and step heights differences that have occurred may be handled by unlocking the lock within the locked unit. This unlocking breaks the cyclic structure, allowing the polymer to take up more volume and causing the anti-reflective layer to self-expand, filling the voids and reducing the step-height. The unlocking may be performed by exposure or thermal treatments.
Filed: June 26, 2013
Date of Patent: November 3, 2015
Inventors: Chen-Yu Liu, Ching-Yu Chang
SEMICONDUCTOR DEVICE AND FABRICATION METHOD
Abstract: A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided.
Filed: February 19, 2014
Applicant: Semiconductor Manufactruing International (Shanghai) Corporation
Inventor: ZHONGSHAN HONG
Method of forming fine patterns of semiconductor device
Abstract: A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space.
Date of Patent: April 7, 2015
Assignee: Samsung Electronics Co., Ltd.
Inventor: Cha-won Koh
Applicants: Globalfoundries Inc., International Business Machines Corporation
Material with tunable index of refraction
Abstract: Devices are described including a component comprising an alloy of AlN and AlSb. The component has an index of refraction substantially the same as that of a semiconductor in the optoelectronic device, and has high transparency at wavelengths of light used in the optoelectronic device. The component is in contact with the semiconductor in the optoelectronic device. The alloy comprises between 0% and 100% AlN by weight and between 0% and 100% AlSb by weight. The semiconductor can be a III-V semiconductor such as GaAs or AlGaInP. The component can be used as a transparent insulator. The alloy can also be doped to form either a p-type conductor or an n-type conductor, and the component can be used as a transparent conductor. Methods of making and devices utilizing the alloy are also disclosed.
Filed: January 10, 2013
Date of Patent: December 2, 2014
Assignee: Intermolecular, Inc.
Inventors: Philip Kraus, Thai Cheng Chua, Yoga Saripalli
Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.
Date of Patent: October 7, 2014
Assignee: GLOBALFOUNDRIES, Inc.
Inventors: Richard A. Farrell, Gerard M. Schmid, xU Ji
Method and structure for reworking antireflective coating over semiconductor substrate
Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
Date of Patent: September 16, 2014
Assignee: International Business Machines Corporation
Inventors: Hakeem Akinmade-Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
Semiconductor light-emitting element, lamp, electronic device and machine
Abstract: A semiconductor light-emitting element (1) is provided which includes a semiconductor layer (10), an n-type electrode (18) which is provided on an exposed surface (12a) of an n-type semiconductor layer, wherein an exposed surface is exposed by removing a part of the semiconductor layer (10), a transparent conductive film which is provided on the semiconductor layer (10) and a p-type electrode (17) which is provided on the transparent conductive film; a light-reflecting layer (39) is provided between the semiconductor layer (10) and the transparent conductive film, wherein at least part of the light-reflecting layer overlaps with the p-type electrode (17) in the planar view; the p-type electrode (17) comprises a pad portion (P) and a linear portion (L) which linearly extends from the pad portion (P) and has an annular structure in the planar view; the n-type electrode (18) exists in an inner area which is surrounded by the linear portion (L) and exists on a straight line (L1) which goes through a center (17a)
Filed: July 5, 2011
Assignee: Toyoda Gosei Co., Ltd.
Inventors: Hironao Shinohara, Remi Ohba
Methods and apparatus for manufacturing semiconductor devices
Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.
Date of Patent: July 29, 2014
Assignee: Texas Instruments Incorporated
Inventors: Stanford Joseph Gautier, Jr., Rabah Mezenner, Randy Long
Pattern forming method
Abstract: A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
Assignee: United Microelectronics Corp.
Inventors: Shin-Chi Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Guang-Yaw Hwang
Charge dissipation of cavities
Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
Date of Patent: June 17, 2014
Assignee: Micron Technology, Inc.
Inventors: Brian Griffin, Russ Benson
Method for producing a metal contact structure of a photovoltaic solar cell
Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.
Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V.
Inventors: Daniel Biro, Benjamin Thaidigsmann, Florian Clement, Robert Woehl, Edgar-Allan Wotke
Method of manufacturing semiconductor device
Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.
Assignee: Renesas Electronics Corporation
Inventors: Naoyuki Teramoto, Megumu Fukazawa, Masayuki Kumashiro, Kiyoshi Kawagashira
Method of manufacturing semiconductor device having surface protective films on bond pad
Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.
Filed: February 6, 2013
Inventors: Takuro Honma, Yoshifumi Takata
Method and material for forming a double exposure lithography pattern
Abstract: Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.
Inventor: Ching-Yu Chang
Patterning method for fabrication of a semiconductor device
Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
Inventors: Erik P. Geiss, Peter Baars
Method for fabricating semiconductor device with buried gates
Abstract: A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.
Assignee: Hynix Semiconductor Inc.
Inventor: Sun-Hwan Hwang
Method for forming metal contacts
Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.
Assignees: Rohm and Haas Electronic Materials LLC, Alliance for Sustainable Energy, LLC
Inventors: Erik Reddington, Thomas C. Sutter, Lujia Bu, Alexandra Cannon, Susan E. Habas, Calvin J. Curtis, Alexander Miedaner, David S. Ginley, Marinus Franciscus Antonius Maria Van Hest
Capacitor and method for fabricating the same
Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.
Assignee: Magnachip Semiconductor, Ltd.
Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer
Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
Date of Patent: August 13, 2013
Inventors: Martin Burkhardt, Matthew E. Colburn, Allen H. Gabor, Oleg Gluschenkov, Scott D. Halle, Howard S. Landis, Helen Wang
Structure resulting from chemical shrink process over BARC (bottom anti-reflective coating)
Abstract: A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.
Inventors: Todd Christopher Bailey, Colin J. Brodsky, Allen H. Gabor
Double patterning strategy for contact hole and trench in photolithography
Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.
Inventors: Po-Cheng Shih, Kuan-Chen Wang, Chung-Chi Ko, Keng-Chu Lin, Tai-Yen Peng, Wen-Kuo Hsieh, Chih-Hao Chen
Interconnect structures with patternable low-k dielectrics and method of fabricating same
Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.
Inventors: Qinghuang Lin, Shyng-Tsong Chen
Side wall pore sealing for low-k dielectrics
Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric ("porogen") material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.
Assignee: NXP B.V.
Inventor: Willem Frederik Adrianus Besling
SEMICONDUCTOR DEVICE WITH FUSE
Abstract: A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.
Publication date: May 9, 2013
Inventor: Min-Yung LEE
Integrated circuit system with ultra-low k dielectric and method of manufacture thereof
Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.
Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Ravi Prakash Srivastava
Anti-reflective coatings for micro-fluid applications
Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.
Date of Patent: March 12, 2013
Assignee: Lexmark International, Inc.
Inventor: Byron V. Bell
Method for manufacturing mask
Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.
Assignee: Elpida Memory, Inc.
Inventor: Mitsunari Sukekawa
Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same
Abstract: A photoresist conversion that changes a patterned photoresist into a permanent patterned interconnect dielectric is described. The photoresist conversion process includes adding a dielectric enabling element into a patterned photoresist. The dielectric enabling element-containing photoresist is converted into a permanent patterned dielectric material by performing a curing step. In one embodiment, a method is described that includes providing at least one photoresist to an upper surface of a substrate. At least one interconnect pattern is formed into the at least one photoresist. A dielectric enabling element is added to the patterned photoresist and thereafter the patterned photoresist including the dielectric enabling element is cured into a cured permanent patterned dielectric material. The cured permanent patterned dielectric material includes the dielectric enabling therein.
Inventor: Qinghuang Lin
MAINTAINING MASK INTEGRITY TO FORM OPENINGS IN WAFERS
Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.
Inventors: Daisuke Shimizu, Jong Mun Kim
Multilayer low reflectivity hard mask and process therefor
Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
Assignee: Advanced Micro Devices, Inc.
Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
Dual damascene process
Abstract: A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
Date of Patent: October 30, 2012
Method for reworking antireflective coating over semiconductor substrate
Inventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
Process for the deposition of an anti-reflection film on a substrate
Abstract: A method for the deposition of an anti-reflection film on a substrate is disclosed. A substrate including a plurality of solar cell structures is provided and placed in a vacuum chamber with a target including silicon. A flow of a nitrogen-containing reactive gas into the vacuum chamber is set to a first value while a voltage between the target and ground is switched off and then increased to a second value. A voltage is applied between the target and ground, whereby a film of silicon and nitrogen is deposited on the substrate in a flow of the nitrogen-containing reactive gas which is higher than the first value.
Assignee: OC Oerlikon Balzers AG
Inventors: Oliver Rattunde, Stephan Voser
Abstract: The present invention provides an image sensor. The image sensor comprises: a substrate, a plurality of optical elements, a first insulation layer, an anti-reflective coating (ARC) layer, a second insulation layer, and a color filter array. The optical elements are disposed in the substrate. The first insulation layer is disposed on the substrate and the optical elements. The ARC layer is disposed on the first insulation layer. The second insulation layer is disposed on the ARC layer. The color filter array is disposed on the second insulation layer, and the color filter array comprises a plurality of color filters corresponding to a plurality of different colors of light, respectively. The ARC layer comprises a plurality of sections directly below the color filters in a vertical direction, respectively, and the sections have different inherent reflection characteristics. The image sensor of the present invention can increase sensitivity and reduce crosstalk.
Date of Patent: September 4, 2012
Assignee: Himax Imaging, Inc.
Inventor: Desmond Cheung
Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.
Plasma etching method and storage medium
Abstract: A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas.
Assignee: Tokyo Electron Limited
Inventors: Naotsugu Hoshi, Noriyuki Kobayashi
Solid-state image sensor and imaging system
Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.
Inventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
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