Q:

In verilog Part-select of vector reg array is illegal

reg [data_width-1:0]coeff[0:order-1];
wire[3:0]lsbcoeff;
wire [7:4]msbcoeff;

 lsbcoeff = coeff[3:0];
 msbcoeff = coeff[7:4];

In the above line of  code, im getting error 
Part-select of vector reg array 'coeff' is illegal
Illegal right hand side of blocking assignment
Please guide me , how to overcome this ?
Xilinx v14.2
Verilog coding

A:

You have coeff defined as a vector of coefficients, I am not sure what you expect coeff[3:0] to return? a vector of the LSBS? I think what you intended was something like coeff[0][3:0] Selecting the LSBs of the first vector. Code below shows a possible way of doing this:
module tb;

    localparam data_width = 8;
    localparam order      = 2;

    reg  [data_width-1:0]coeff[0:order-1];
    reg [3:0] lsbcoeff;
    reg [7:4] msbcoeff;
    reg [7:0] this_coeff;

    always @* begin
      lsbcoeff   = coeff[0][3:0];
      msbcoeff   = coeff[0][7:4];
    end

endmodule

and now I have read the comments I see this is what @Greg has already suggested.

