Q:

Simple makefile not producing output file(Correctly)

I have a simple make file as such:
all:
    gcc -ansi -pedantic -Wall -Werror ListImplementation.c ListType.h ListInterface.h  test.c -o test.out

    gcc -ansi -pedantic -Wall -Werror ListImplementation.c ListType.h ListInterface.h  sort.c -o sort.out

Where test.c is a file reliant on those other c files, and headerfiles.
The same goes for sort.c.
Now after typing "make" it compiles, however in my text editor (gedit),
sort.c is color coded blue for some reason. As such when I look in the directory (On Ubuntu after running make), test.out works fine (it's green color coded, but sort.out does not (it's white). Trying to run ./sort.out does not work as the file never turned into an output file, despite the name change, what could be going wrong here?

A:

Succinctly, the whole structure of the makefile is wrong.  For the code shown, you should be using something like:
PROG1 = test
PROG2 = sort
PROGRAMS = ${PROG1} ${PROG2}

LIST.c = ListImplementation.c
TEST.c = test.c
SORT.c = sort.c

LIST.o = ${LIST.c:.c=.o}
SORT.o = ${SORT.c:.c=.o}
TEST.o = ${TEST.c:.c=.o}

all: ${PROG1} ${PROG2}

${PROG1}: ${LIST.o} ${TEST.o}
    ${CC} -o $@ ${CFLAGS} ${LIST.o} ${TEST.o} ${LDFLAGS} ${LDLIBS}

${PROG2}: ${LIST.o} ${SORT.o}
    ${CC} -o $@ ${CFLAGS} ${LIST.o} ${SORT.o} ${LDFLAGS} ${LDLIBS}

${LIST.o}: ListType.h ListInterface.h
${SORT.o}: ListType.h ListInterface.h
${TEST.o}: ListType.h ListInterface.h

This will work with pretty much any version of make.  It assumes that the make program will define a C compiler in macro CC, that it defines compilation flags in macro CFLAGS, loader flags in macro LDFLAGS and libraries in LDLIBS.  It assumes that make can deduce that it can create sort.o from sort.c using a built-in rule equivalent to:
sort.o: sort.c
    ${CC} ${CFLAGS} -c -o $@ sort.c

where the -o $@ might not be specified on the command line.
If you're using GNU make, there are shorthands available that are not used.  Often, I'd define a macro for the object files for a program and then use the in the dependency list and in the linker command line.  Also, with GNU make, you could usefully add:
.PHONY: all

to tell make that there shouldn't be an actual file called all around.
Now, when you run make, it looks to find all.  When it doesn't find it, it makes it by ensuring the dependencies, ${PROG1} and ${PROG2} are each up to date, and then executing the (empty) list of commands for the all target.  To make ${PROG1}, it finds the rule, ensures the dependencies are up to date, and then runs the (non-empty) list of commands to create the ${PROG1} target.

