Q:

SR Latch settles on equilibrium state with lower voltage supply

I need to use SR latch for my design and it was working fine. Until I started it with lower voltages.

CON8 and O4 are the inputs. CON9 is the output.
When I use 15V supply, it works very fine:

But when I lower the supply to 9V, I get this:

it settles on a middle point. SR Latch circuit is standard as below, nothing fancy:

why does this happen?
This is the zoom in of the signals:

Output and input rises with the other input falling. Why this is happening? And why this is happening in lower supply voltages but not higher ones?

A:

You basically build this right ?

A 2 NAND SR latch.
Note how the outputs feed back to the inputs, you have a circuit which "bites it's own tail".
Since you implemented the NAND gates using the simplest possible circuit there are certain circumstances where it will not behave in the way you expect. You would expect it to behave as a digital circuit, so Q and Qnot are either low or high.
But this circuit will not always behave like that, there's a point where it can settle "in the middle" at an output voltage of around half the supply voltage. That's what you saw with a 9 V supply.
The 15 V supply case does work because the higher supply voltage makes more current flow and this increases the gain of the circuit making it more willing to "flip" to either supply rail.
It's even more interesting to do a DC simulation on such a circuit because often the DC solution will be that both Q and Qnot will be at roughly half the supply voltage ! In the real world this will never happen, the circuit will always end up in a certain state depending on noise and the transistors not being 100% equal (even on a chip where they're supposed to be very equal). If you make some transistors deliberately larger than the others, you can force it into a preferred startup state.

