Q:

How to Convert array_type (array) input to std_logic_vector?

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

 entity shift_unit is
 Port ( clk: in std_logic;
          a_0 : in  STD_LOGIC_VECTOR(15 downto 0);
       a_1 : in  STD_LOGIC_VECTOR(15 downto 0);
       b_0 : in  STD_LOGIC_VECTOR(15 downto 0);
       b_1 : in  STD_LOGIC_VECTOR(15 downto 0);
       a064 : out  STD_LOGIC_VECTOR(15 downto 0);
          a164 : out  STD_LOGIC_VECTOR(15 downto 0);
       c083,c036 : out  STD_LOGIC_VECTOR(15 downto 0);
          c183,c136 : out  STD_LOGIC_VECTOR(15 downto 0));
 end shift_unit;

 architecture Behavioral of shift_unit is
 type array_type is array (0 to 1) of std_logic_vector(15 downto 0);

 Component SA is
 port( clk: in std_logic;    
  bi: in std_logic_vector(15 downto 0);
  c83: out std_logic_vector(15 downto 0);
    c36: out std_logic_vector(15 downto 0));        
  end Component;
 signal b ,c_083,c_036: array_type;
  begin

      process(clk)
      variable i: integer:=0;
       begin
      if(rising_edge(clk)) then
       elsif(i=0) then
         b(i)<=b_0; 
         i:=i+1;
       elsif(i=1) then
          b(i)<=b_1;
          i:=0;
       end if;
     end process;

       SA_GEN: for I in 0 to 1 generate
         SA0 : SA port map(clk,b,c_083(I),c_036(I));  --error. Line 65
       end generate SA_GEN;

       end Behavioral;

Component SA is
entity SA is
port( clk: in std_logic;
  bi: in std_logic_vector(15 downto 0);
  c83: out std_logic_vector(15 downto 0);
    c36: out std_logic_vector(15 downto 0));        
end SA;

When I am Checking Syntex  it's give an error 
ERROR:HDLParsers:820 - "shift_unit_pk.vhdl" Line 65. Type of actual ports is not compatible with type of ports of SA.
Here b,c083 and c036 are of array_type  and the SA has i/p and o/p port in std_logic_vector.  I tried to convert it to std_logic_vector and then map to the SA, but it gives same error. So how can i do this Mapping / type conversion.

A:

Here is your code with some fixes and improvements:
library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     IEEE.NUMERIC_STD.ALL;

entity shift_unit is
  Port (
    clk: in std_logic;
    a_0 : in  STD_LOGIC_VECTOR(15 downto 0);
    a_1 : in  STD_LOGIC_VECTOR(15 downto 0);
    b_0 : in  STD_LOGIC_VECTOR(15 downto 0);
    b_1 : in  STD_LOGIC_VECTOR(15 downto 0);
    a064 : out  STD_LOGIC_VECTOR(15 downto 0);
    a164 : out  STD_LOGIC_VECTOR(15 downto 0);
    c083,c036 : out  STD_LOGIC_VECTOR(15 downto 0);
    c183,c136 : out  STD_LOGIC_VECTOR(15 downto 0)
  );
end shift_unit;

architecture Behavioral of shift_unit is
  type array_type is array (0 to 1) of std_logic_vector(15 downto 0);

  Component SA is
    port(
      clk: in std_logic;    
      bi: in std_logic_vector(15 downto 0);
      c83: out std_logic_vector(15 downto 0);
      c36: out std_logic_vector(15 downto 0)
    );
  end Component;

  signal b ,c_083,c_036: array_type;
begin

  process(clk)
    variable i: std_logic := '0';
  begin
    if(rising_edge(clk)) then
      if(i = '0') then
        b(0) <= b_0; 
      else
        b(1) <= b_1;
      end if;
      i <= not i;
    end if;
  end process;

  SA_GEN: for I in 0 to 1 generate
    SA0 : SA
      port map(
        clk => clk,
        bi =>  b(I),
        c83 => c_083(I),
        c36 => c_036(I)
      );
  end generate SA_GEN;
end;

If you are interested in VHDL types and functions for advanced std_logic_vector, std_logic_vector_vector and std_logic_matrix handling, then have a look for this post: https://codereview.stackexchange.com/questions/73708/vhdl-mux-in-need-of-generics/73794#73794

