Q:

General JTAG working flow in an embedded development system?

In my embedded project am using JTAG interface to download the code and to debug the downloaded application.But i don't know what is happening inside the JTAG set up.
Can anyone please give me basic idea/flow(high level view) of the JTAG set up wich will really help me to understand my development system better.
__Kanu

A:

To add to Cliffords answer, there are some pictures here:
http://www.fpga4fun.com/JTAG2.html
The tap controller state machine is something you will see published ad nauseum.  It is really the key to JTAG.  As Clifford said you access on chip debug registers.  The tap controller state machine is generic to all JTAG supported devices, but the address, length, etc of the registers you can get to through JTAG.  And the sequence of things you have to read or write in order to do something useful varies widely from vendor to vendor.  Some ARM Technical Reference Manuals (for various cores) for example have a Debug TAP controller chapter, with this picture and with the gory details on the procedure for reading and writing a register or memory or halting the processor, etc. 

