Q:

Choosing decoupling caps

I know there are other questions on this site about decoupling, but I do not feel they accurately cover the full decision process.
I am interested in knowing the decisions that go into choosing decoupling caps. I do not mean a microprocessor with a well laid out datasheet containing proper diagrams of the capacitors, and I do not want to concern this questions with layout as decoupling in layout is separate and a huge subject.
Let us take an i7 as an example. What are the steps that one would take in choosing decoupling caps? Certain things in the datasheet to model? ESR models? Signal speeds? I am just curious what rabbit holes I should go down if I want to be diligent and not rely on the manufacturers recommendations (which I am aware are important).

A:

The decoupling capacitor removes noise on the power rail.  It also functions to shunt high frequency currents (bypass the load).  We want to damp the transient response to reduce ringing and ripple.
At it's heart, this boils down to impedance matching... good 'ole
Z=R+j(ωL-1/ωC). Here ω is the angular frequency of your noise, L is inductance due to PCB traces and/or switching power supply inductance, and C is the load capacitance (which you increased by introducing your decoupling cap).  Low ESR parts don't contribute much to the R part, which is desirable.
If you want to go down the rabbit hole, you could determine the optimal values by using a spectrum analyzer to determine the frequency response and choosing C accordingly.  This is important for antenna and RF stuff, and usually not so important for power supply filtering.
The size of the capacitor(s) depends on the frequency of noise.  Ideally, you would decouple with several capacitors of varying size.  You may target a certain frequency response.  In high noise environments such as automotive applications, it is common to use a common mode choke.
Take a look at this article and this article for more information.  
Most of the time it's appropriate to haphazardly slap down a ceramic SMD low ESR 100nF, and maybe do a parallel 10uF.
Since you specifically mentioned i7... you could try to eliminate j at the CPU clock speed and your RAM speed (DDR?).

