# 環境

Windows 10  
Quartus Prime Lite 21.1

# 背景・現状

現在、<https://kazu1995.hatenablog.jp/entry/2017/11/18/202718>
を参考に、FPGAボードとPCのUSB通信を実現したいと思っています。  
そこで、公開されている以下のコードをQuartusでコンパイルしました。

```

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;
    
    
    entity Cyclone is
        port (
            SW      : in    std_logic_vector( 9 downto 0);
            LEDG    : inout std_logic_vector( 9 downto 0);
            HEX0_D  : inout std_logic_vector( 6 downto 0);
            HEX1_D  : inout std_logic_vector( 6 downto 0);
            HEX2_D  : inout std_logic_vector( 6 downto 0);
            HEX3_D  : inout std_logic_vector( 6 downto 0);
            HEX0_DP : inout std_logic;
            HEX1_DP : inout std_logic;
            HEX2_DP : inout std_logic;
            HEX3_DP : inout std_logic
        );
    end Cyclone;
    
    
    architecture RTL of Cyclone is
        signal i                    : integer;
        signal tck                  : std_logic;
        signal tdi                  : std_logic;
        signal tdo                  : std_logic;
        signal ir_in                : std_logic_vector(  7 downto 0);
        signal ir_out               : std_logic_vector(  7 downto 0);
        signal virtual_state_uir    : std_logic;
        signal virtual_state_sdr    : std_logic;
        signal r_ir                 : std_logic_vector(  7 downto 0);
        constant build_number       : std_logic_vector( 31 downto 0)
            := (conv_std_logic_vector(20171117, 32));
    
    begin
        top_connection : entity work.virtualjtag
            port map(
                tck             => tck,
                tdi             => tdi,
                tdo             => tdo,
                ir_in           => ir_in,
                ir_out          => ir_out,
                virtual_state_uir => virtual_state_uir,
                virtual_state_sdr => virtual_state_sdr
            );
    
        process(tck)
        begin
            if(tck'event and tck='1') then
                if(virtual_state_uir = '1') then
                    r_ir(7 downto 0) <= ir_in;
                    i <= 0;
                elsif(virtual_state_sdr='1') then
                    case r_ir is
                        when "00000000" =>
                            tdo <= SW(i);
                        when "00000001" =>
                            if(i < 10) then
                                LEDG(i) <= tdi;
                            end if;
                        when "00000011" =>
                            case i is
                                when  0 to  6   => HEX3_D(i) <= tdi;
                                when  7         => HEX3_DP   <= tdi;
                                when  8 to 14   => HEX2_D(i) <= tdi;
                                when 15         => HEX2_DP   <= tdi;
                                when 16 to 22   => HEX1_D(i) <= tdi;
                                when 23         => HEX1_DP   <= tdi;
                                when 24 to 30   => HEX0_D(i) <= tdi;
                                when 31         => HEX0_DP   <= tdi;
                                when others     => null;
                            end case;
                        when "00001010" =>
                            tdo <= build_number(i);
                        when others => null;
                    end case;
                    i <= i + 1;
                end if;
            end if;
        end process;
    end RTL;
    
```

すると、下記のコンパイルエラーが出現しました。

```

    top_connection : entity work.virtualjtagでError (10481): VHDL Use Clause error at RTL.vhd(37): design library "work" does not contain primary unit "virtualjtag". Verify that the primary unit exists in the library and has been successfully compiled.
    
```

調べたところ、ライブラリにvirtualjtagのIPを追加すればよいということまでは分かりました。

# 質問

QuartusでIPをライブラリに追加する方法、またライブラリをコンパイル時に参照できるようにする方法を教えてください。
CC BY-SA 4.0
2022-10-22T15:03:08.147
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2022-10-22T15:06:07.357
2022-10-22T15:06:07.357
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question
fpga vhdl
Quartusコンパイル時のライブラリ取り込み方を知りたい