# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_by_size(reg_class, reg_size):
#     """
#     @brief Determines the register by its size and class
#     @param reg_class The register class of the register
#     @param reg_size The size of the register
#     @return Name of the register
#     """
#     if reg_class >= len(_registerClasses):
#         return None
#     num_regs = len(_registerClasses[reg_class])
#     if num_regs < 4:
#         return None
#     reg_index = -1
#     if reg_size > 32: # 64-bit regs
#         reg_index = num_regs - 1
#     elif reg_size > 16: # 32-bit regs
#         reg_index = num_regs - 2
#     elif reg_size > 8: # 16-bit regs
#         reg_index = num_regs - 3
#     elif reg_size > 0: # 8-bit regs
#         reg_index = 0
#     else:
#         return None
#     return _registerClasses[reg_class][reg_index]


import idaapi
from idc import *
from idautils import *
from lib.Register import get_reg_class, get_reg_by_size
    if current_color in palette:
        pos = palette.index(current_color)
        if pos == len(palette) - 1:
            return palette[pos]
        else:
            return palette[pos + 1]

    return 0xFFFFFF


class CPU(object):
    def __init__(self):
        self.registers = {}
        self.st = {'ST0':0, 'ST1':0, 'ST2':0, 'ST3':0, 'ST4':0, 'ST5':0, 'ST6':0, 'ST7':0}
        self.ctrl = {'CTRL':0}
        self.segments = {'CS', 'DS', 'ES', 'FS', 'GS', 'SS'}
        self.registers = {'RAX', 'RBX', 'RCX', 'RDX', 'RSI', 'RDI', 'RBP', 'RSP', 'R8', 'R9', 'R10', 'R11', 'R12', 'R13',
                     'R14', 'R15'}
        self.flags = {}
        self.multimedia = {'XMM0':0, 'XMM1':0, 'XMM2':0, 'XMM3':0, 'XMM4':0, 'XMM5':0, 'XMM6':0, 'XMM7':0, 'XMM8':0, 'XMM9':0, 'XMM10':0, 'XMM11':0,
                      'XMM12':0, 'XMM13':0, 'XMM14':0, 'XMM15':0, 'MXCSR':0, 'MM0':0, 'MM1':0, 'MM2':0, 'MM3':0, 'MM4':0, 'MM5':0, 'MM6':0, 'MM7':0}


def get_reg(reg_string, reg_size):
    """
    returns the register name to be used as key with a Traceline.ctx object
    :param reg_string: any string representing a reg, e.g. rax, RAX, eax, ah, al, etc.
    :param reg_size: size in bit of the registers in Traceline.ctx, e.g. 64, 32, 16
    :return: reg_string of the ctx keys, e.g. rax
    """

# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_by_size(reg_class, reg_size):
#     """
#     @brief Determines the register by its size and class
#     @param reg_class The register class of the register
#     @param reg_size The size of the register
#     @return Name of the register
#     """
#     if reg_class >= len(_registerClasses):
#         return None
#     num_regs = len(_registerClasses[reg_class])
#     if num_regs < 4:
#         return None
#     reg_index = -1
#     if reg_size > 32: # 64-bit regs
#         reg_index = num_regs - 1
#     elif reg_size > 16: # 32-bit regs
#         reg_index = num_regs - 2
#     elif reg_size > 8: # 16-bit regs
#         reg_index = num_regs - 3
#     elif reg_size > 0: # 8-bit regs
#         reg_index = 0
#     else:
#         return None
#     return _registerClasses[reg_class][reg_index]


# Path: lib/Util.py
import idaapi
from idc import *
from idautils import *
from lib.Register import get_reg_class, get_reg_by_size

    if current_color in palette:
        pos = palette.index(current_color)
        if pos == len(palette) - 1:
            return palette[pos]
        else:
            return palette[pos + 1]

    return 0xFFFFFF


class CPU(object):
    def __init__(self):
        self.registers = {}
        self.st = {'ST0':0, 'ST1':0, 'ST2':0, 'ST3':0, 'ST4':0, 'ST5':0, 'ST6':0, 'ST7':0}
        self.ctrl = {'CTRL':0}
        self.segments = {'CS', 'DS', 'ES', 'FS', 'GS', 'SS'}
        self.registers = {'RAX', 'RBX', 'RCX', 'RDX', 'RSI', 'RDI', 'RBP', 'RSP', 'R8', 'R9', 'R10', 'R11', 'R12', 'R13',
                     'R14', 'R15'}
        self.flags = {}
        self.multimedia = {'XMM0':0, 'XMM1':0, 'XMM2':0, 'XMM3':0, 'XMM4':0, 'XMM5':0, 'XMM6':0, 'XMM7':0, 'XMM8':0, 'XMM9':0, 'XMM10':0, 'XMM11':0,
                      'XMM12':0, 'XMM13':0, 'XMM14':0, 'XMM15':0, 'MXCSR':0, 'MM0':0, 'MM1':0, 'MM2':0, 'MM3':0, 'MM4':0, 'MM5':0, 'MM6':0, 'MM7':0}


def get_reg(reg_string, reg_size):
    """
    returns the register name to be used as key with a Traceline.ctx object
    :param reg_string: any string representing a reg, e.g. rax, RAX, eax, ah, al, etc.
    :param reg_size: size in bit of the registers in Traceline.ctx, e.g. 64, 32, 16
    :return: reg_string of the ctx keys, e.g. rax
    """

    return get_reg_by_size(get_reg_class(reg_string), reg_size)