# Path: dragonpy/constants.py
# DRAGON32 = "Dragon32"
# DRAGON64 = "Dragon64"
# COCO2B = "CoCo2b"
# SBC09 = "sbc09"
# SIMPLE6809 = "Simple6809"
# MULTICOMP6809 = "Multicomp6809"
# VECTREX = "Vectrex"
# 
# Path: dragonpy/core/configs.py
# class BaseConfig:
#     #     # http address/port number for the CPU control server
#     #     CPU_CONTROL_ADDR = "127.0.0.1"
#     #     CPU_CONTROL_PORT = 6809
# 
#     # How many ops should be execute before make a control server update cycle?
#     BURST_COUNT = 10000
# 
#     DEFAULT_ROMS = {}
# 
#     def __init__(self, cfg_dict):
#         self.cfg_dict = cfg_dict
#         self.cfg_dict["cfg_module"] = self.__module__  # FIXME: !
# 
#         log.debug("cfg_dict: %s", repr(cfg_dict))
# 
# #         # socket address for internal bus I/O:
# #         if cfg_dict["bus_socket_host"] and cfg_dict["bus_socket_port"]:
# #             self.bus = True
# #             self.bus_socket_host = cfg_dict["bus_socket_host"]
# #             self.bus_socket_port = cfg_dict["bus_socket_port"]
# #         else:
# #             self.bus = None # Will be set in cpu6809.start_CPU()
# 
#         assert not hasattr(
#             cfg_dict, "ram"), f"cfg_dict.ram is deprecated! Remove it from: {self.cfg_dict.__class__.__name__}"
# 
# #         if cfg_dict["rom"]:
# #             raw_rom_cfg = cfg_dict["rom"]
# #             raise NotImplementedError("TODO: create rom cfg!")
# #         else:
#         self.rom_cfg = self.DEFAULT_ROMS
# 
#         if cfg_dict["trace"]:
#             self.trace = True
#         else:
#             self.trace = False
# 
#         self.verbosity = cfg_dict["verbosity"]
# 
#         self.mem_info = DummyMemInfo()
#         self.memory_byte_middlewares = {}
#         self.memory_word_middlewares = {}
# 
#     def _get_initial_Memory(self, size):
#         return [0x00] * size
# 
#     def get_initial_RAM(self):
#         return self._get_initial_Memory(self.RAM_SIZE)
# 
#     def get_initial_ROM(self):
#         return self._get_initial_Memory(self.ROM_SIZE)
# 
# #     def get_initial_ROM(self):
# #         start=cfg.ROM_START, size=cfg.ROM_SIZE
# #         self.start = start
# #         self.end = start + size
# #         self._mem = [0x00] * size
# 
#     def print_debug_info(self):
#         print(f"Config: '{self.__class__.__name__}'")
# 
#         for name, value in inspect.getmembers(self):  # , inspect.isdatadescriptor):
#             if name.startswith("_"):
#                 continue
# #             print name, type(value)
#             if not isinstance(value, (int, str, list, tuple, dict)):
#                 continue
#             if isinstance(value, int):
#                 print(f"{name:>20} = {value:<6} in hex: {hex(value):>7}")
#             else:
#                 print(f"{name:>20} = {value}")
# 
# Path: dragonpy/vectrex/mem_info.py
# class VectrexMemInfo(BaseMemoryInfo):
#     MEM_INFO = (
#         # TODO: Add info from:
#         # * http://www.playvectrex.com/designit/chrissalo/appendixa.htm#Other
#         # * http://www.playvectrex.com/designit/chrissalo/appendixb.htm
# 
#         (0x0000, 0x7FFF, "Cartridge ROM"),
#         (0x8000, 0xC7FF, "Unmapped space"),
#         (0xC800, 0xCFFF, "RAM"),
#         (0xD000, 0xD7FF, "6522 interface adapter"),
#         (0xD800, 0xDFFF, "6522 / RAM ?!?"),
#         (0xE000, 0xEFFF, "ROM - builtin Mine storm game"),
#         (0xF000, 0xFFFF, "ROM - vectrex BIOS Executive"),
# 
#         (0xbff0, 0xbfff, "6809 interrupt vectors mapped to $fff0-$ffff by SAM"),
#         (0xbff0, 0xfff1, "Reserved     ($0000)"),
#         (0xbff2, 0xbff3, "SWI3 vector  ($0100)"),
#         (0xbff4, 0xbff5, "SWI2 vector  ($0103)"),
#         (0xbff6, 0xbff7, "FIRQ vector  ($010f)"),
#         (0xbff8, 0xbff9, "IRQ vector   ($010c)"),
#         (0xbffa, 0xbffb, "SWI vector   ($0106)"),
#         (0xbffc, 0xbffd, "NMI vector   ($0109)"),
#         (0xbffe, 0xbfff, "RESET vector ($b3b4)"),
#     )
# 
# Path: dragonpy/vectrex/vectrex_rom.py
# class VectrexRom(ROMFile):
#     ROM_PATH = os.path.normpath(
#         os.path.abspath(os.path.dirname(__file__))
#     )
#     SHA1 = "65d07426b520ddd3115d40f255511e0fd2e20ae7"
#     FILENAME = "SYSTEM.IMG"
# 
#     def get_data(self):
#         if not os.path.isfile(self.rom_path):
#             raise RuntimeError(f"Rom file {self.rom_path!r} not there?!?")
# 
#         return super().get_data()


import logging
from dragonpy import constants
from dragonpy.core.configs import BaseConfig
from dragonpy.vectrex.mem_info import VectrexMemInfo
from dragonpy.vectrex.vectrex_rom import VectrexRom
"""
    DragonPy - Vectrex
    ==================

    https://en.wikipedia.org/wiki/Vectrex

    :created: 2014 by Jens Diemer - www.jensdiemer.de
    :copyleft: 2014 by the DragonPy team, see AUTHORS for more details.
    :license: GNU GPL v3 or above, see LICENSE for more details.
"""





log = logging.getLogger(__name__)


# from dragonlib.api import VectrexAPI

# Path: dragonpy/constants.py
# DRAGON32 = "Dragon32"
# DRAGON64 = "Dragon64"
# COCO2B = "CoCo2b"
# SBC09 = "sbc09"
# SIMPLE6809 = "Simple6809"
# MULTICOMP6809 = "Multicomp6809"
# VECTREX = "Vectrex"
# 
# Path: dragonpy/core/configs.py
# class BaseConfig:
#     #     # http address/port number for the CPU control server
#     #     CPU_CONTROL_ADDR = "127.0.0.1"
#     #     CPU_CONTROL_PORT = 6809
# 
#     # How many ops should be execute before make a control server update cycle?
#     BURST_COUNT = 10000
# 
#     DEFAULT_ROMS = {}
# 
#     def __init__(self, cfg_dict):
#         self.cfg_dict = cfg_dict
#         self.cfg_dict["cfg_module"] = self.__module__  # FIXME: !
# 
#         log.debug("cfg_dict: %s", repr(cfg_dict))
# 
# #         # socket address for internal bus I/O:
# #         if cfg_dict["bus_socket_host"] and cfg_dict["bus_socket_port"]:
# #             self.bus = True
# #             self.bus_socket_host = cfg_dict["bus_socket_host"]
# #             self.bus_socket_port = cfg_dict["bus_socket_port"]
# #         else:
# #             self.bus = None # Will be set in cpu6809.start_CPU()
# 
#         assert not hasattr(
#             cfg_dict, "ram"), f"cfg_dict.ram is deprecated! Remove it from: {self.cfg_dict.__class__.__name__}"
# 
# #         if cfg_dict["rom"]:
# #             raw_rom_cfg = cfg_dict["rom"]
# #             raise NotImplementedError("TODO: create rom cfg!")
# #         else:
#         self.rom_cfg = self.DEFAULT_ROMS
# 
#         if cfg_dict["trace"]:
#             self.trace = True
#         else:
#             self.trace = False
# 
#         self.verbosity = cfg_dict["verbosity"]
# 
#         self.mem_info = DummyMemInfo()
#         self.memory_byte_middlewares = {}
#         self.memory_word_middlewares = {}
# 
#     def _get_initial_Memory(self, size):
#         return [0x00] * size
# 
#     def get_initial_RAM(self):
#         return self._get_initial_Memory(self.RAM_SIZE)
# 
#     def get_initial_ROM(self):
#         return self._get_initial_Memory(self.ROM_SIZE)
# 
# #     def get_initial_ROM(self):
# #         start=cfg.ROM_START, size=cfg.ROM_SIZE
# #         self.start = start
# #         self.end = start + size
# #         self._mem = [0x00] * size
# 
#     def print_debug_info(self):
#         print(f"Config: '{self.__class__.__name__}'")
# 
#         for name, value in inspect.getmembers(self):  # , inspect.isdatadescriptor):
#             if name.startswith("_"):
#                 continue
# #             print name, type(value)
#             if not isinstance(value, (int, str, list, tuple, dict)):
#                 continue
#             if isinstance(value, int):
#                 print(f"{name:>20} = {value:<6} in hex: {hex(value):>7}")
#             else:
#                 print(f"{name:>20} = {value}")
# 
# Path: dragonpy/vectrex/mem_info.py
# class VectrexMemInfo(BaseMemoryInfo):
#     MEM_INFO = (
#         # TODO: Add info from:
#         # * http://www.playvectrex.com/designit/chrissalo/appendixa.htm#Other
#         # * http://www.playvectrex.com/designit/chrissalo/appendixb.htm
# 
#         (0x0000, 0x7FFF, "Cartridge ROM"),
#         (0x8000, 0xC7FF, "Unmapped space"),
#         (0xC800, 0xCFFF, "RAM"),
#         (0xD000, 0xD7FF, "6522 interface adapter"),
#         (0xD800, 0xDFFF, "6522 / RAM ?!?"),
#         (0xE000, 0xEFFF, "ROM - builtin Mine storm game"),
#         (0xF000, 0xFFFF, "ROM - vectrex BIOS Executive"),
# 
#         (0xbff0, 0xbfff, "6809 interrupt vectors mapped to $fff0-$ffff by SAM"),
#         (0xbff0, 0xfff1, "Reserved     ($0000)"),
#         (0xbff2, 0xbff3, "SWI3 vector  ($0100)"),
#         (0xbff4, 0xbff5, "SWI2 vector  ($0103)"),
#         (0xbff6, 0xbff7, "FIRQ vector  ($010f)"),
#         (0xbff8, 0xbff9, "IRQ vector   ($010c)"),
#         (0xbffa, 0xbffb, "SWI vector   ($0106)"),
#         (0xbffc, 0xbffd, "NMI vector   ($0109)"),
#         (0xbffe, 0xbfff, "RESET vector ($b3b4)"),
#     )
# 
# Path: dragonpy/vectrex/vectrex_rom.py
# class VectrexRom(ROMFile):
#     ROM_PATH = os.path.normpath(
#         os.path.abspath(os.path.dirname(__file__))
#     )
#     SHA1 = "65d07426b520ddd3115d40f255511e0fd2e20ae7"
#     FILENAME = "SYSTEM.IMG"
# 
#     def get_data(self):
#         if not os.path.isfile(self.rom_path):
#             raise RuntimeError(f"Rom file {self.rom_path!r} not there?!?")
# 
#         return super().get_data()


# Path: dragonpy/vectrex/config.py
import logging
from dragonpy import constants
from dragonpy.core.configs import BaseConfig
from dragonpy.vectrex.mem_info import VectrexMemInfo
from dragonpy.vectrex.vectrex_rom import VectrexRom

"""
    DragonPy - Vectrex
    ==================

    https://en.wikipedia.org/wiki/Vectrex

    :created: 2014 by Jens Diemer - www.jensdiemer.de
    :copyleft: 2014 by the DragonPy team, see AUTHORS for more details.
    :license: GNU GPL v3 or above, see LICENSE for more details.
"""





log = logging.getLogger(__name__)


# from dragonlib.api import VectrexAPI

class VectrexCfg(BaseConfig):