# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_class_lst(reg_class):
#     """
#     @return Returns the whole list of a given register class 
#     """
#     return _registerClasses[reg_class]
# 
# Path: lib/StartVal.py
# ASSEMBLER_64 = 64
# ASSEMBLER_32 = 32


from lib.Register import (get_reg_class,
                          get_reg_class_lst)
from lib import StartVal as SV
        @brief Replace plain VmInstruction representation with a
        push/pop representation. This representation needs temporal
        variables and each of these temporal variables is unique
        """
        ret = []
        if self.inst_class == IN2_OUT2:
            op0 = VariableOperand(VARIABLE_T, self.op_lst[0].size)
            op1 = VariableOperand(VARIABLE_T, self.op_lst[1].size)
            op0_size = self.op_lst[0].size / 8
            # vm does not support byte pop/push maybe worng place for this
            if op0_size < 2:
                op0_size = 2
            op1_size = self.op_lst[1].size / 8
            if op1_size < 2:
                op1_size = 2
            ret.append(PseudoInstruction('vpop', self.addr,
                                         [op0], op0_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op1],
                                         op1_size, POP_T))
            assign_op = VariableOperand(VARIABLE_T, self.size)
            assign_instruction = PseudoInstruction(
                self.mnem, self.addr,
                [assign_op, op0, op1], self.size,
                self.inst_type, ASSIGNEMENT_T
            )
            ret.append(assign_instruction)
            flagsop = VariableOperand(VARIABLE_T, self.size, True)
            ret.append(PseudoInstruction('vpush', self.addr, [assign_op],
                                         self.op_lst[0].size / 8, PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr, [flagsop],

# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_class_lst(reg_class):
#     """
#     @return Returns the whole list of a given register class 
#     """
#     return _registerClasses[reg_class]
# 
# Path: lib/StartVal.py
# ASSEMBLER_64 = 64
# ASSEMBLER_32 = 32


# Path: lib/PseudoInstruction.py
from lib.Register import (get_reg_class,
                          get_reg_class_lst)
from lib import StartVal as SV

        @brief Replace plain VmInstruction representation with a
        push/pop representation. This representation needs temporal
        variables and each of these temporal variables is unique
        """
        ret = []
        if self.inst_class == IN2_OUT2:
            op0 = VariableOperand(VARIABLE_T, self.op_lst[0].size)
            op1 = VariableOperand(VARIABLE_T, self.op_lst[1].size)
            op0_size = self.op_lst[0].size / 8
            # vm does not support byte pop/push maybe worng place for this
            if op0_size < 2:
                op0_size = 2
            op1_size = self.op_lst[1].size / 8
            if op1_size < 2:
                op1_size = 2
            ret.append(PseudoInstruction('vpop', self.addr,
                                         [op0], op0_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op1],
                                         op1_size, POP_T))
            assign_op = VariableOperand(VARIABLE_T, self.size)
            assign_instruction = PseudoInstruction(
                self.mnem, self.addr,
                [assign_op, op0, op1], self.size,
                self.inst_type, ASSIGNEMENT_T
            )
            ret.append(assign_instruction)
            flagsop = VariableOperand(VARIABLE_T, self.size, True)
            ret.append(PseudoInstruction('vpush', self.addr, [assign_op],
                                         self.op_lst[0].size / 8, PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr, [flagsop],

                                         SV.dissassm_type / 8, PUSH_T))