# Path: Core/core.py
# def CoreHDL(clk_i,
#             rst_i,
#             toHost,
#             imem_addr_o,
#             imem_dat_o,
#             imem_sel_o,
#             imem_cyc_o,
#             imem_we_o,
#             imem_stb_o,
#             imem_dat_i,
#             imem_ack_i,
#             imem_err_i,
#             dmem_addr_o,
#             dmem_dat_o,
#             dmem_sel_o,
#             dmem_cyc_o,
#             dmem_we_o,
#             dmem_stb_o,
#             dmem_dat_i,
#             dmem_ack_i,
#             dmem_err_i,
#             IC_BLOCK_WIDTH=3,
#             IC_SET_WIDTH=8,
#             IC_NUM_WAYS=2,
#             DC_BLOCK_WIDTH=3,
#             DC_SET_WIDTH=8,
#             DC_NUM_WAYS=2):
#     """
#     Core top Module.
#     This module use single ports for verilog translation and to avoid
#     generating ugly names for top ports.
#     """
# 
#     imem = WishboneIntercon()
#     dmem = WishboneIntercon()
#     core = Core(clk_i=clk_i,
#                 rst_i=rst_i,
#                 toHost=toHost,
#                 imem=imem,
#                 dmem=dmem,
#                 IC_BLOCK_WIDTH=IC_BLOCK_WIDTH,
#                 IC_SET_WIDTH=IC_SET_WIDTH,
#                 IC_NUM_WAYS=IC_NUM_WAYS,
#                 DC_BLOCK_WIDTH=DC_BLOCK_WIDTH,
#                 DC_SET_WIDTH=DC_SET_WIDTH,
#                 DC_NUM_WAYS=DC_NUM_WAYS)
# 
#     @always_comb
#     def assign():
#         # Instruction memory
#         imem_addr_o.next = imem.addr
#         imem_dat_o.next  = imem.dat_o
#         imem_sel_o.next  = imem.sel
#         imem_cyc_o.next  = imem.cyc
#         imem_we_o.next   = imem.we
#         imem_stb_o.next  = imem.stb
#         imem.dat_i.next  = imem_dat_i
#         imem.ack.next    = imem_ack_i
#         imem.err.next    = imem_err_i
#         # Data memory
#         dmem_addr_o.next = dmem.addr
#         dmem_dat_o.next  = dmem.dat_o
#         dmem_sel_o.next  = dmem.sel
#         dmem_cyc_o.next  = dmem.cyc
#         dmem_we_o.next   = dmem.we
#         dmem_stb_o.next  = dmem.stb
#         dmem.dat_i.next  = dmem_dat_i
#         dmem.ack.next    = dmem_ack_i
#         dmem.err.next    = dmem_err_i
# 
#     return core, assign


import argparse
import pytest
import os
import glob
import subprocess
from myhdl import toVerilog
from myhdl import Signal
from myhdl import modbv
from Core.core import CoreHDL


def clean_tests(args):
    make_process = subprocess.Popen("make clean", stderr=subprocess.STDOUT, cwd='Simulation/tests', shell=True)
    assert make_process.wait() == 0, 'Unable to clean test folder.'


def convert_to_verilog(args):
    clk          = Signal(False)
    rst          = Signal(False)
    imem_addr_o  = Signal(modbv(0)[32:])
    imem_dat_o   = Signal(modbv(0)[32:])
    imem_sel_o   = Signal(modbv(0)[4:])
    imem_cyc_o   = Signal(False)
    imem_we_o    = Signal(False)
    imem_stb_o   = Signal(False)
    imem_dat_i   = Signal(modbv(0)[32:])
    imem_ack_i   = Signal(False)
    imem_err_i   = Signal(False)
    dmem_addr_o  = Signal(modbv(0)[32:])
    dmem_dat_o   = Signal(modbv(0)[32:])
    dmem_sel_o   = Signal(modbv(0)[4:])
    dmem_cyc_o   = Signal(False)
    dmem_we_o    = Signal(False)
    dmem_stb_o   = Signal(False)
    dmem_dat_i   = Signal(modbv(0)[32:])
    dmem_ack_i   = Signal(False)
    dmem_err_i   = Signal(False)
    toHost       = Signal(modbv(0)[32:])


# Path: Core/core.py
# def CoreHDL(clk_i,
#             rst_i,
#             toHost,
#             imem_addr_o,
#             imem_dat_o,
#             imem_sel_o,
#             imem_cyc_o,
#             imem_we_o,
#             imem_stb_o,
#             imem_dat_i,
#             imem_ack_i,
#             imem_err_i,
#             dmem_addr_o,
#             dmem_dat_o,
#             dmem_sel_o,
#             dmem_cyc_o,
#             dmem_we_o,
#             dmem_stb_o,
#             dmem_dat_i,
#             dmem_ack_i,
#             dmem_err_i,
#             IC_BLOCK_WIDTH=3,
#             IC_SET_WIDTH=8,
#             IC_NUM_WAYS=2,
#             DC_BLOCK_WIDTH=3,
#             DC_SET_WIDTH=8,
#             DC_NUM_WAYS=2):
#     """
#     Core top Module.
#     This module use single ports for verilog translation and to avoid
#     generating ugly names for top ports.
#     """
# 
#     imem = WishboneIntercon()
#     dmem = WishboneIntercon()
#     core = Core(clk_i=clk_i,
#                 rst_i=rst_i,
#                 toHost=toHost,
#                 imem=imem,
#                 dmem=dmem,
#                 IC_BLOCK_WIDTH=IC_BLOCK_WIDTH,
#                 IC_SET_WIDTH=IC_SET_WIDTH,
#                 IC_NUM_WAYS=IC_NUM_WAYS,
#                 DC_BLOCK_WIDTH=DC_BLOCK_WIDTH,
#                 DC_SET_WIDTH=DC_SET_WIDTH,
#                 DC_NUM_WAYS=DC_NUM_WAYS)
# 
#     @always_comb
#     def assign():
#         # Instruction memory
#         imem_addr_o.next = imem.addr
#         imem_dat_o.next  = imem.dat_o
#         imem_sel_o.next  = imem.sel
#         imem_cyc_o.next  = imem.cyc
#         imem_we_o.next   = imem.we
#         imem_stb_o.next  = imem.stb
#         imem.dat_i.next  = imem_dat_i
#         imem.ack.next    = imem_ack_i
#         imem.err.next    = imem_err_i
#         # Data memory
#         dmem_addr_o.next = dmem.addr
#         dmem_dat_o.next  = dmem.dat_o
#         dmem_sel_o.next  = dmem.sel
#         dmem_cyc_o.next  = dmem.cyc
#         dmem_we_o.next   = dmem.we
#         dmem_stb_o.next  = dmem.stb
#         dmem.dat_i.next  = dmem_dat_i
#         dmem.ack.next    = dmem_ack_i
#         dmem.err.next    = dmem_err_i
# 
#     return core, assign


# Path: Simulation/run.py
import argparse
import pytest
import os
import glob
import subprocess
from myhdl import toVerilog
from myhdl import Signal
from myhdl import modbv
from Core.core import CoreHDL



def clean_tests(args):
    make_process = subprocess.Popen("make clean", stderr=subprocess.STDOUT, cwd='Simulation/tests', shell=True)
    assert make_process.wait() == 0, 'Unable to clean test folder.'


def convert_to_verilog(args):
    clk          = Signal(False)
    rst          = Signal(False)
    imem_addr_o  = Signal(modbv(0)[32:])
    imem_dat_o   = Signal(modbv(0)[32:])
    imem_sel_o   = Signal(modbv(0)[4:])
    imem_cyc_o   = Signal(False)
    imem_we_o    = Signal(False)
    imem_stb_o   = Signal(False)
    imem_dat_i   = Signal(modbv(0)[32:])
    imem_ack_i   = Signal(False)
    imem_err_i   = Signal(False)
    dmem_addr_o  = Signal(modbv(0)[32:])
    dmem_dat_o   = Signal(modbv(0)[32:])
    dmem_sel_o   = Signal(modbv(0)[4:])
    dmem_cyc_o   = Signal(False)
    dmem_we_o    = Signal(False)
    dmem_stb_o   = Signal(False)
    dmem_dat_i   = Signal(modbv(0)[32:])
    dmem_ack_i   = Signal(False)
    dmem_err_i   = Signal(False)
    toHost       = Signal(modbv(0)[32:])


    toVerilog(CoreHDL, clk, rst, toHost, imem_addr_o, imem_dat_o, imem_sel_o, imem_cyc_o, imem_we_o,