# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_class_lst(reg_class):
#     """
#     @return Returns the whole list of a given register class 
#     """
#     return _registerClasses[reg_class]
# 
# Path: lib/StartVal.py
# ASSEMBLER_64 = 64
# ASSEMBLER_32 = 32


from lib.Register import (get_reg_class,
                          get_reg_class_lst)
from lib import StartVal as SV
            if op1_size < 2:
                op1_size = 2
            opd_size = self.op_lst[2].size / 8
            if opd_size < 2:
                opd_size = 2
            ret.append(PseudoInstruction('vpop', self.addr, [op0],
                                         op0_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op1],
                                         op1_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op_divisor],
                                         opd_size, POP_T))
            assign_op = VariableOperand(VARIABLE_T, self.size)
            flagsop = VariableOperand(VARIABLE_T, self.size, True)
            assign_op2 = VariableOperand(VARIABLE_T, self.size)
            double_op = DoubleVariable(assign_op, assign_op2)
            assign_instruction = PseudoInstruction(
                self.mnem, self.addr,
                [double_op, op0, op1, op_divisor], self.size,
                self.inst_type, ASSIGNEMENT_T
            )
            ret.append(assign_instruction)
            flagsop2 = VariableOperand(VARIABLE_T, self.size, True)
            double_flags = DoubleVariable(flagsop, flagsop2)
            ret.append(PseudoInstruction('vpush', self.addr,
                                         [assign_op2], self.op_lst[0].size / 8,
                                         PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr,
                                         [assign_op], self.op_lst[0].size / 8,
                                         PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr, [double_flags],

# Path: lib/Register.py
# def get_reg_class(reg):
#     """
#     @brief Determines the register class of a given reg.
#     All different register names that address the same register
#     belong to the same register class e.g.: 'ax' and 'eax'
#     @param reg name of register
#     @return register class
#     """
#     lreg = reg.lower()
#     ret_value = None
#     for pos, reg_list in enumerate(_registerClasses):
#         for reg in reg_list:
#             found = False
#             if reg == lreg:
#                 found = True
#                 ret_value = pos
#                 break
#         if found:
#             break
#     return ret_value
# 
# def get_reg_class_lst(reg_class):
#     """
#     @return Returns the whole list of a given register class 
#     """
#     return _registerClasses[reg_class]
# 
# Path: lib/StartVal.py
# ASSEMBLER_64 = 64
# ASSEMBLER_32 = 32


# Path: lib/PseudoInstruction.py
from lib.Register import (get_reg_class,
                          get_reg_class_lst)
from lib import StartVal as SV

            if op1_size < 2:
                op1_size = 2
            opd_size = self.op_lst[2].size / 8
            if opd_size < 2:
                opd_size = 2
            ret.append(PseudoInstruction('vpop', self.addr, [op0],
                                         op0_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op1],
                                         op1_size, POP_T))
            ret.append(PseudoInstruction('vpop', self.addr, [op_divisor],
                                         opd_size, POP_T))
            assign_op = VariableOperand(VARIABLE_T, self.size)
            flagsop = VariableOperand(VARIABLE_T, self.size, True)
            assign_op2 = VariableOperand(VARIABLE_T, self.size)
            double_op = DoubleVariable(assign_op, assign_op2)
            assign_instruction = PseudoInstruction(
                self.mnem, self.addr,
                [double_op, op0, op1, op_divisor], self.size,
                self.inst_type, ASSIGNEMENT_T
            )
            ret.append(assign_instruction)
            flagsop2 = VariableOperand(VARIABLE_T, self.size, True)
            double_flags = DoubleVariable(flagsop, flagsop2)
            ret.append(PseudoInstruction('vpush', self.addr,
                                         [assign_op2], self.op_lst[0].size / 8,
                                         PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr,
                                         [assign_op], self.op_lst[0].size / 8,
                                         PUSH_T))
            ret.append(PseudoInstruction('vpush', self.addr, [double_flags],

                                         SV.dissassm_type / 8, PUSH_T))