# Path: hdmi/utils/clock_driver.py
# @block
# def clock_driver(clock, d=1):
# 
#     @instance
#     def drive_clock():
#         while True:
#             yield delay(d)
#             clock.next = not clock
# 
#     return drive_clock


from myhdl import block, instance, instances
from hdmi.utils import clock_driver
def pll_clock_generator(clock_feedback_out, pll_clock0, pll_clock1, pll_clock2,
                        pll_locked, clock_feedback_in, clock, reset, clock_fb_out_mult=10,
                        clock0_divide=1, clock1_divide=10, clock2_divide=5):

    """

    A block that generates clocks of three different frequencies and will be used by the
    receiver core. This will be replaced by the xilinx primitive PLL_BASE during conversion.

    Args:
        clock_feedback_out: A feedback signal
        pll_clock0: clock generated with time period 2*clock0_divide
        pll_clock1: clock generated with time period 2*clock1_divide
        pll_clock2: clock generated with time period 2*clock2_divide
        pll_locked: A signal denoting that the phase is locked
        clock_feedback_in: Input feedback signal
        clock: global clock
        reset: reset signal
        clock_fb_out_mult: The value to be multiplied with global clock frequency
        clock0_divide: The value to be divided from clock_fb_out_mult to get the frequency
        clock1_divide: The value to be divided from clock_fb_out_mult to get the frequency
        clock2_divide: The value to be divided from clock_fb_out_mult to get the frequency

    Returns:
        myhdl.instances() : A list of myhdl instances.

    """

    global inst_count
    clock0_inst = clock_driver(pll_clock0, clock0_divide)

# Path: hdmi/utils/clock_driver.py
# @block
# def clock_driver(clock, d=1):
# 
#     @instance
#     def drive_clock():
#         while True:
#             yield delay(d)
#             clock.next = not clock
# 
#     return drive_clock


# Path: hdmi/cores/primitives/phase_locked_loop_clock.py
from myhdl import block, instance, instances
from hdmi.utils import clock_driver

def pll_clock_generator(clock_feedback_out, pll_clock0, pll_clock1, pll_clock2,
                        pll_locked, clock_feedback_in, clock, reset, clock_fb_out_mult=10,
                        clock0_divide=1, clock1_divide=10, clock2_divide=5):

    """

    A block that generates clocks of three different frequencies and will be used by the
    receiver core. This will be replaced by the xilinx primitive PLL_BASE during conversion.

    Args:
        clock_feedback_out: A feedback signal
        pll_clock0: clock generated with time period 2*clock0_divide
        pll_clock1: clock generated with time period 2*clock1_divide
        pll_clock2: clock generated with time period 2*clock2_divide
        pll_locked: A signal denoting that the phase is locked
        clock_feedback_in: Input feedback signal
        clock: global clock
        reset: reset signal
        clock_fb_out_mult: The value to be multiplied with global clock frequency
        clock0_divide: The value to be divided from clock_fb_out_mult to get the frequency
        clock1_divide: The value to be divided from clock_fb_out_mult to get the frequency
        clock2_divide: The value to be divided from clock_fb_out_mult to get the frequency

    Returns:
        myhdl.instances() : A list of myhdl instances.

    """

    global inst_count
    clock0_inst = clock_driver(pll_clock0, clock0_divide)

    clock1_inst = clock_driver(pll_clock1, clock1_divide)