# Path: MC6809/tests/test_base.py
# class BaseCPUTestCase(BaseTestCase):
#     UNITTEST_CFG_DICT = {
#         "verbosity": None,
#         "display_cycle": False,
#         "trace": None,
#         "bus_socket_host": None,
#         "bus_socket_port": None,
#         "ram": None,
#         "rom": None,
#         "max_ops": None,
#         "use_bus": False,
#     }
# 
#     def setUp(self):
#         cfg = TestCfg(self.UNITTEST_CFG_DICT)
#         memory = Memory(cfg)
#         self.cpu = CPU(memory, cfg)
# 
#     def cpu_test_run(self, start, end, mem):
#         for cell in mem:
#             self.assertLess(-1, cell, f"${cell:x} < 0")
#             self.assertGreater(0x100, cell, f"${cell:x} > 0xff")
#         log.debug("memory load at $%x: %s", start,
#                   ", ".join("$%x" % i for i in mem)
#                   )
#         self.cpu.memory.load(start, mem)
#         if end is None:
#             end = start + len(mem)
#         self.cpu.test_run(start, end)
#     cpu_test_run.__test__ = False  # Exclude from nose
# 
#     def cpu_test_run2(self, start, count, mem):
#         for cell in mem:
#             self.assertLess(-1, cell, f"${cell:x} < 0")
#             self.assertGreater(0x100, cell, f"${cell:x} > 0xff")
#         self.cpu.memory.load(start, mem)
#         self.cpu.test_run2(start, count)
#     cpu_test_run2.__test__ = False  # Exclude from nose
# 
#     def assertMemory(self, start, mem):
#         for index, should_byte in enumerate(mem):
#             address = start + index
#             is_byte = self.cpu.memory.read_byte(address)
# 
#             msg = f"${is_byte:02x} is not ${should_byte:02x} at address ${address:04x} (index: {index:d})"
#             self.assertEqual(is_byte, should_byte, msg)


import logging
import sys
import unittest
from MC6809.tests.test_base import BaseCPUTestCase
            0x1F, 0xA8,  # TFR CC,A
        ])
        self.assertEqualHexByte(self.cpu.get_cc_value(), 0x89)
        self.assertEqualHexByte(self.cpu.accu_a.value, 0x89)

    def test_TFR_Y_B(self):
        """
        transfer 16 bit register in a 8 bit register
        TODO: verify this behaviour on real hardware!
        """
        self.cpu.index_y.set(0x1234)
        self.cpu.accu_b.set(0xab)
        self.cpu_test_run(start=0x4000, end=None, mem=[
            0x1F, 0x29,  # TFR Y,B
        ])
        self.assertEqualHexWord(self.cpu.index_y.value, 0x1234)
        self.assertEqualHexByte(self.cpu.accu_b.value, 0x34)

    def test_TFR_undefined_A(self):
        """
        transfer undefined register in a 8 bit register
        TODO: verify this behaviour on real hardware!
        """
        self.cpu.accu_a.set(0x12)
        self.cpu_test_run(start=0x4000, end=None, mem=[
            0x1F, 0x68,  # TFR undefined,A
        ])
        self.assertEqualHexByte(self.cpu.accu_a.value, 0xff)



# Path: MC6809/tests/test_base.py
# class BaseCPUTestCase(BaseTestCase):
#     UNITTEST_CFG_DICT = {
#         "verbosity": None,
#         "display_cycle": False,
#         "trace": None,
#         "bus_socket_host": None,
#         "bus_socket_port": None,
#         "ram": None,
#         "rom": None,
#         "max_ops": None,
#         "use_bus": False,
#     }
# 
#     def setUp(self):
#         cfg = TestCfg(self.UNITTEST_CFG_DICT)
#         memory = Memory(cfg)
#         self.cpu = CPU(memory, cfg)
# 
#     def cpu_test_run(self, start, end, mem):
#         for cell in mem:
#             self.assertLess(-1, cell, f"${cell:x} < 0")
#             self.assertGreater(0x100, cell, f"${cell:x} > 0xff")
#         log.debug("memory load at $%x: %s", start,
#                   ", ".join("$%x" % i for i in mem)
#                   )
#         self.cpu.memory.load(start, mem)
#         if end is None:
#             end = start + len(mem)
#         self.cpu.test_run(start, end)
#     cpu_test_run.__test__ = False  # Exclude from nose
# 
#     def cpu_test_run2(self, start, count, mem):
#         for cell in mem:
#             self.assertLess(-1, cell, f"${cell:x} < 0")
#             self.assertGreater(0x100, cell, f"${cell:x} > 0xff")
#         self.cpu.memory.load(start, mem)
#         self.cpu.test_run2(start, count)
#     cpu_test_run2.__test__ = False  # Exclude from nose
# 
#     def assertMemory(self, start, mem):
#         for index, should_byte in enumerate(mem):
#             address = start + index
#             is_byte = self.cpu.memory.read_byte(address)
# 
#             msg = f"${is_byte:02x} is not ${should_byte:02x} at address ${address:04x} (index: {index:d})"
#             self.assertEqual(is_byte, should_byte, msg)


# Path: MC6809/tests/test_6809_register_changes.py
import logging
import sys
import unittest
from MC6809.tests.test_base import BaseCPUTestCase

            0x1F, 0xA8,  # TFR CC,A
        ])
        self.assertEqualHexByte(self.cpu.get_cc_value(), 0x89)
        self.assertEqualHexByte(self.cpu.accu_a.value, 0x89)

    def test_TFR_Y_B(self):
        """
        transfer 16 bit register in a 8 bit register
        TODO: verify this behaviour on real hardware!
        """
        self.cpu.index_y.set(0x1234)
        self.cpu.accu_b.set(0xab)
        self.cpu_test_run(start=0x4000, end=None, mem=[
            0x1F, 0x29,  # TFR Y,B
        ])
        self.assertEqualHexWord(self.cpu.index_y.value, 0x1234)
        self.assertEqualHexByte(self.cpu.accu_b.value, 0x34)

    def test_TFR_undefined_A(self):
        """
        transfer undefined register in a 8 bit register
        TODO: verify this behaviour on real hardware!
        """
        self.cpu.accu_a.set(0x12)
        self.cpu_test_run(start=0x4000, end=None, mem=[
            0x1F, 0x68,  # TFR undefined,A
        ])
        self.assertEqualHexByte(self.cpu.accu_a.value, 0xff)



class Test6809_EXG(BaseCPUTestCase):