# Path: VM/ctypes_types.py



import ctypes
from .ctypes_types import ubyte, uword, udword
        _pack_ = 1
        _fields_ = [
            (f'e{letter}x', udword),
            (letter + 'x', uword)
        ]

    return _Reg32


def GenReg(tail: str):
    assert tail in REG_TAILS

    class _Reg32(ctypes.Union):
        _fields_ = [
            (f'e{tail}', udword),
            (tail, uword),
        ]

    return _Reg32


class _Eflags_bits(ctypes.LittleEndianStructure):
    _pack_ = 1
    _fields_ = [
        ('CF', uword, 1),
        ('__', uword, 1),
        ('PF', uword, 1),
        ('__', uword, 1),
        ('AF', uword, 1),
        ('__', uword, 1),

# Path: VM/ctypes_types.py



# Path: VM/Registers.py
import ctypes
from .ctypes_types import ubyte, uword, udword

        _pack_ = 1
        _fields_ = [
            (f'e{letter}x', udword),
            (letter + 'x', uword)
        ]

    return _Reg32


def GenReg(tail: str):
    assert tail in REG_TAILS

    class _Reg32(ctypes.Union):
        _fields_ = [
            (f'e{tail}', udword),
            (tail, uword),
        ]

    return _Reg32


class _Eflags_bits(ctypes.LittleEndianStructure):
    _pack_ = 1
    _fields_ = [
        ('CF', uword, 1),
        ('__', uword, 1),
        ('PF', uword, 1),
        ('__', uword, 1),
        ('AF', uword, 1),
        ('__', uword, 1),

        ('ZF', uword, 1),