# Path: VM/util.py
# def to_int(data: bytes, signed=False):
# def to_signed(num: int, bytes: int) -> int:
# def is_signed_out_of_range(num: int, size: int) -> bool:
#     def __init__(cls, name, bases, dct):
#     def __init__(cls, name, bases, dct):
#     def load_instruction(cls, instruction, opcode, implementation):
#     def __init__(self):
# class MissingOpcodeError(RuntimeError):
# class InstructionMeta(type):
# class CPUMeta(type):
# class Instruction(metaclass=InstructionMeta):
# class CPU(metaclass=CPUMeta):


from ..util import Instruction, SegmentRegs
from functools import partialmethod as P
    import logging
        }

    def m(vm, _8bit: bool) -> True:
        sz = 1 if _8bit else vm.operand_size

        eax = vm.reg.get(0, sz)
        edi = vm.reg.get(7, vm.address_size)

        vm.mem.segment_override = SegmentRegs.ES
        vm.mem.set(edi, sz, eax)
        vm.mem.segment_override = SegmentRegs.DS

        if not vm.reg.eflags.DF:
            edi += sz
        else:
            edi -= sz

        edi &= MAXVALS[vm.address_size]

        vm.reg.set(7, vm.address_size, edi)

        if __debug__:
            logger.debug(
                'stos%s [0x%x], eax=0x%x',
                'b' if sz == 1 else ('w' if sz == 2 else 'd'), edi, eax
            )

        return True



# Path: VM/util.py
# def to_int(data: bytes, signed=False):
# def to_signed(num: int, bytes: int) -> int:
# def is_signed_out_of_range(num: int, size: int) -> bool:
#     def __init__(cls, name, bases, dct):
#     def __init__(cls, name, bases, dct):
#     def load_instruction(cls, instruction, opcode, implementation):
#     def __init__(self):
# class MissingOpcodeError(RuntimeError):
# class InstructionMeta(type):
# class CPUMeta(type):
# class Instruction(metaclass=InstructionMeta):
# class CPU(metaclass=CPUMeta):


# Path: VM/instructions/repeatables.py
from ..util import Instruction, SegmentRegs
from functools import partialmethod as P
    import logging

        }

    def m(vm, _8bit: bool) -> True:
        sz = 1 if _8bit else vm.operand_size

        eax = vm.reg.get(0, sz)
        edi = vm.reg.get(7, vm.address_size)

        vm.mem.segment_override = SegmentRegs.ES
        vm.mem.set(edi, sz, eax)
        vm.mem.segment_override = SegmentRegs.DS

        if not vm.reg.eflags.DF:
            edi += sz
        else:
            edi -= sz

        edi &= MAXVALS[vm.address_size]

        vm.reg.set(7, vm.address_size, edi)

        if __debug__:
            logger.debug(
                'stos%s [0x%x], eax=0x%x',
                'b' if sz == 1 else ('w' if sz == 2 else 'd'), edi, eax
            )

        return True



class REP(Instruction):