# Path: backend/basicblock.py
# class BasicBlock(object):
#     def __init__(self):
#     def __getitem__(self,k):
#     def __setitem__(self,k,v):
#     def __delitem__(self,idx):
#     def insert(self,idx,op):
#     def prepend(self,op):
#     def append(self,op):
#     def __len__(self):
#     def __iter__(self):
#     def __repr__(self):
#     def removeInstructions(self,instructions):
#     def unsafeEnding(self):
#     def getSuccessors(self):
#     def getReachableBlocks(self):
#         def generator():
# 
# Path: backend/ir.py
# class VirtualRegister(object):
# class I32(VirtualRegister):
# class I16(VirtualRegister):
# class I8(VirtualRegister):
# class Pointer(VirtualRegister):
# class ConstantInt(object):
# class ConstantI32(ConstantInt):
# class ConstantI8(ConstantInt):
# class Instruction(object):
# class Binop(Instruction):
# class Unop(Instruction):
# class Call(Instruction):
# class LoadGlobalAddr(Instruction):
# class LoadParamAddr(Instruction):
# class LoadLocalAddr(Instruction):
# class LoadConstant(Instruction):
# class Deref(Instruction):
# class Store(Instruction):
# class Terminator(Instruction):
# class Ret(Terminator):
# class Branch(Terminator):
# class Jmp(Terminator):
# class Phi(Instruction):
# class Move(Instruction):
#     def __init__(self):
#     def isPhysical(self):
#     def __repr__(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def __init__(self,v):
#     def __repr__(self):
#     def __init__(self):
#     def getDagDisplayText(self):
#     def isTerminator(self):
#     def isBranch(self):
#     def swapVar(self,old,new):
#     def swapRead(self,old,new):
#     def swapAssigned(self,old,new):
#     def asm(self):
#     def getSuccessors(self):
#     def setSuccessors(self,new):
#     def swapSuccessor(self,old,new):
#     def getStackSlots(self):
#     def readsMem(self):
#     def writesMem(self):
#     def isMD(self):
#     def isMove(self):
#     def isCall(self):
#     def getClobberedRegisters(self):
#     def getPreClobberedRegisters(self):
#     def __init__(self,op,res,l,r):
#     def getDagDisplayText(self):
#     def __repr__(self):
#     def __init__(self,op,res,arg):
#     def __repr__(self):
#     def __init__(self,label):
#     def __repr__(self):
#     def isCall(self):
#     def readsMem(self):
#     def writesMem(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def getStackSlots(self):
#     def __init__(self,res,const):
#     def __repr__(self):
#     def __init__(self,out,p):
#     def __repr__(self):
#     def readsMem(self):
#     def __init__(self,p,val):
#     def __repr__(self):
#     def writesMem(self):
#     def isTerminator(self):
#     def getTemplateLookupStr(self):
#     def __init__(self,v=None):
#     def __repr__(self):
#     def __init__(self,v,t,f):
#     def __repr__(self):
#     def __init__(self,dest):
#     def __repr__(self):
#     def __init__(self,lhs,args):
#     def __repr__(self):
#     def __init__(self,l,r):
#     def isMove(self):
#     def __repr__(self):


import valtracker
import types
import operatorgen
from backend import basicblock
from backend import ir
    assert(bb[0].assigned[0] == newv.reg)
    assert(bb[0].op == 'zx')
    assert(len(bb) == 1)

    t = types.Char(signed=True)
    v = valtracker.ValTracker(False,t,None)
    v.createVirtualReg()
    assert(type(v.reg) == ir.I8)
    bb = basicblock.BasicBlock()
    newv = operatorgen.promoteToInt(bb,v)
    
    assert(len(bb) == 1)
    assert(newv.type.signed == True)
    assert(type(newv.type) == types.Int)
    assert(type(bb[0]) == ir.Unop)
    assert(bb[0].read[0] == v.reg)
    assert(bb[0].assigned[0] == newv.reg)
    assert(bb[0].op == 'sx')
    assert(len(bb) == 1)

    t = types.ShortInt(signed=False)
    v = valtracker.ValTracker(False,t,None)
    v.createVirtualReg()
    assert(type(v.reg) == ir.I16)
    bb = basicblock.BasicBlock()
    newv = operatorgen.promoteToInt(bb,v)
    
    assert(len(bb) == 1)
    assert(newv.type.signed == True)
    assert(type(newv.type) == types.Int)

# Path: backend/basicblock.py
# class BasicBlock(object):
#     def __init__(self):
#     def __getitem__(self,k):
#     def __setitem__(self,k,v):
#     def __delitem__(self,idx):
#     def insert(self,idx,op):
#     def prepend(self,op):
#     def append(self,op):
#     def __len__(self):
#     def __iter__(self):
#     def __repr__(self):
#     def removeInstructions(self,instructions):
#     def unsafeEnding(self):
#     def getSuccessors(self):
#     def getReachableBlocks(self):
#         def generator():
# 
# Path: backend/ir.py
# class VirtualRegister(object):
# class I32(VirtualRegister):
# class I16(VirtualRegister):
# class I8(VirtualRegister):
# class Pointer(VirtualRegister):
# class ConstantInt(object):
# class ConstantI32(ConstantInt):
# class ConstantI8(ConstantInt):
# class Instruction(object):
# class Binop(Instruction):
# class Unop(Instruction):
# class Call(Instruction):
# class LoadGlobalAddr(Instruction):
# class LoadParamAddr(Instruction):
# class LoadLocalAddr(Instruction):
# class LoadConstant(Instruction):
# class Deref(Instruction):
# class Store(Instruction):
# class Terminator(Instruction):
# class Ret(Terminator):
# class Branch(Terminator):
# class Jmp(Terminator):
# class Phi(Instruction):
# class Move(Instruction):
#     def __init__(self):
#     def isPhysical(self):
#     def __repr__(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def getSize(self):
#     def __init__(self,v):
#     def __repr__(self):
#     def __init__(self):
#     def getDagDisplayText(self):
#     def isTerminator(self):
#     def isBranch(self):
#     def swapVar(self,old,new):
#     def swapRead(self,old,new):
#     def swapAssigned(self,old,new):
#     def asm(self):
#     def getSuccessors(self):
#     def setSuccessors(self,new):
#     def swapSuccessor(self,old,new):
#     def getStackSlots(self):
#     def readsMem(self):
#     def writesMem(self):
#     def isMD(self):
#     def isMove(self):
#     def isCall(self):
#     def getClobberedRegisters(self):
#     def getPreClobberedRegisters(self):
#     def __init__(self,op,res,l,r):
#     def getDagDisplayText(self):
#     def __repr__(self):
#     def __init__(self,op,res,arg):
#     def __repr__(self):
#     def __init__(self,label):
#     def __repr__(self):
#     def isCall(self):
#     def readsMem(self):
#     def writesMem(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def __init__(self,res,sym):
#     def __repr__(self):
#     def getStackSlots(self):
#     def __init__(self,res,const):
#     def __repr__(self):
#     def __init__(self,out,p):
#     def __repr__(self):
#     def readsMem(self):
#     def __init__(self,p,val):
#     def __repr__(self):
#     def writesMem(self):
#     def isTerminator(self):
#     def getTemplateLookupStr(self):
#     def __init__(self,v=None):
#     def __repr__(self):
#     def __init__(self,v,t,f):
#     def __repr__(self):
#     def __init__(self,dest):
#     def __repr__(self):
#     def __init__(self,lhs,args):
#     def __repr__(self):
#     def __init__(self,l,r):
#     def isMove(self):
#     def __repr__(self):


# Path: c/test_operatorgen.py
import valtracker
import types
import operatorgen
from backend import basicblock
from backend import ir

    assert(bb[0].assigned[0] == newv.reg)
    assert(bb[0].op == 'zx')
    assert(len(bb) == 1)

    t = types.Char(signed=True)
    v = valtracker.ValTracker(False,t,None)
    v.createVirtualReg()
    assert(type(v.reg) == ir.I8)
    bb = basicblock.BasicBlock()
    newv = operatorgen.promoteToInt(bb,v)
    
    assert(len(bb) == 1)
    assert(newv.type.signed == True)
    assert(type(newv.type) == types.Int)
    assert(type(bb[0]) == ir.Unop)
    assert(bb[0].read[0] == v.reg)
    assert(bb[0].assigned[0] == newv.reg)
    assert(bb[0].op == 'sx')
    assert(len(bb) == 1)

    t = types.ShortInt(signed=False)
    v = valtracker.ValTracker(False,t,None)
    v.createVirtualReg()
    assert(type(v.reg) == ir.I16)
    bb = basicblock.BasicBlock()
    newv = operatorgen.promoteToInt(bb,v)
    
    assert(len(bb) == 1)
    assert(newv.type.signed == True)
    assert(type(newv.type) == types.Int)

    assert(type(bb[0]) == ir.Unop)